CN112309979B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112309979B
CN112309979B CN201910702025.9A CN201910702025A CN112309979B CN 112309979 B CN112309979 B CN 112309979B CN 201910702025 A CN201910702025 A CN 201910702025A CN 112309979 B CN112309979 B CN 112309979B
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fin
mask layer
forming
mask
substrate
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CN112309979A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a device region and an isolation region adjacent to the device region, and the device region is used for forming a device fin part; forming a first mask layer on a device region of a substrate, and forming a second mask layer on an isolation region of the substrate; etching the substrate by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part; removing the second mask layer, and taking the first mask layer as a fin mask layer after removing the second mask layer; and etching the initial substrate by taking the fin mask layer and the top fin of the isolation region as masks to form a substrate, a pseudo fin protruding out of the substrate of the isolation region and a bottom fin located between the top fin of the device region and the substrate, wherein the bottom fin and the top fin form the device fin. And when the initial substrate is etched, the top fin part of the isolation region is also etched, so that the top surface of the pseudo fin part is lower than the top surface of the bottom fin part, fin cutting is realized, and compared with the scheme of performing fin cutting by using a mask, the process window is enlarged.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend toward very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To accommodate the reduction in feature size, the channel length of the MOSFET is also correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely so-called short-channel effects (SCE), is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device region and an isolation region adjacent to the device region, and the device region is used for forming a device fin part; forming a first mask layer on a device region of the substrate, and forming a second mask layer on an isolation region of the substrate; etching the base with partial thickness by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part protruding out of the initial substrate; removing the second mask layer after the top fin portion is formed, and taking the first mask layer as a fin portion mask layer after the second mask layer is removed; and etching the initial substrate with partial thickness by taking the fin mask layer and the top fin of the isolation region as masks to form a substrate, a pseudo fin protruding out of the substrate of the isolation region and a bottom fin located between the top fin of the device region and the substrate, wherein the bottom fin and the top fin of the device region form the device fin.
Optionally, after forming the first mask layer and the second mask layer, a top surface of the second mask layer is lower than a top surface of the first mask layer; the method for forming the semiconductor structure further comprises the following steps: and in the process of removing the second mask layer, removing part of the first mask layer with the height, and taking the rest of the first mask layer as the fin part mask layer.
Optionally, the step of forming the first mask layer and the second mask layer includes: forming a core layer on the substrate; forming a mask side wall on the side wall of the core layer, wherein the mask side wall located in the device region is used as the first mask layer; removing part of the mask side wall at the height in the isolation region, wherein the remaining mask side wall in the isolation region is used as the second mask layer; and removing the core layer after removing the mask side wall of the isolation region with partial height.
Optionally, the step of removing the mask sidewall of the isolation region with a partial height includes: forming a shielding layer on the substrate, wherein the shielding layer covers the first mask layer and exposes a mask side wall positioned in the isolation region; etching the mask side wall with partial height in the isolation region by taking the shielding layer as a mask; and removing the shielding layer.
Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a side wall film which conformally covers the core layer and the substrate; and removing the side wall films on the substrate and the top of the core layer, and reserving the side wall films on the side wall of the core layer as the mask side wall.
Optionally, an anisotropic etching process is adopted to remove a part of the mask side wall with the height in the isolation region.
Optionally, after the first mask layer and the second mask layer are formed, the height of the second mask layer is 1/4 to 1/2 of the height of the first mask layer.
Optionally, in the step of forming a first mask layer on the substrate of the device region, a height of the first mask layer is 20nm to 50nm.
Optionally, in the step of forming the top fin, a height of the top fin is greater than or equal to an effective height of the device fin.
Optionally, the height of the top fin is 1 to 1.5 times the effective height of the device fin.
Optionally, an anisotropic etching process is used to remove the second mask layer and a portion of the first mask layer.
Optionally, the anisotropic etching process is an anisotropic dry etching process.
Optionally, the material of any one of the first mask layer and the second mask layer includes one or more of silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.
Optionally, the material of the core layer is amorphous silicon or amorphous carbon.
Optionally, after forming the device fin, the method further includes: and forming an isolation structure on the substrate exposed by the device fin part, wherein the isolation structure covers the pseudo fin part, and the top surface of the isolation structure is lower than the top surface of the device fin part.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: an initial substrate, wherein the initial substrate comprises a device region and an isolation region adjacent to the device region, and the device region is used for forming a device fin part; the top fin parts are respectively positioned on the device region and the isolation region of the initial substrate, and the top fin parts are made of the same material as the initial substrate; and the fin part mask layer is positioned at the top of the fin part at the top of the device region.
Optionally, the height of the top fin is greater than or equal to the effective height of the device fin.
Optionally, the height of the top fin is 1 to 1.5 times the effective height of the device fin.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the embodiment of the invention, after forming the first mask layer on the substrate of the device region and the second mask layer on the substrate of the isolation region, etching the substrate with partial thickness by taking the first mask layer and the second mask layer as masks, forming an initial substrate and a top fin part protruding out of the initial substrate, then removing the second mask layer, and after removing the second mask layer, enabling the first mask layer to serve as a fin part mask layer, and correspondingly, when etching the initial substrate with partial thickness, taking the fin part mask layer and the top fin part of the isolation region as masks; the material of the top Fin portion is the same as that of the initial substrate, the top Fin portion of the isolation region is correspondingly etched while the initial substrate exposed by the top Fin portion is etched, and when the top Fin portion of the isolation region is completely removed, the initial substrate material below the top Fin portion of the isolation region is continuously etched, so that after the dummy Fin portion (dummy Fin) and the bottom Fin portion are formed, the top of the dummy Fin portion is lower than the top of the bottom Fin portion, the technological effect of Fin cutting (Fin Cut) is achieved, and compared with the scheme of Fin cutting by directly adopting a mask (mask), the technological window is increased, and therefore damage to the device Fin portion can be reduced while the Fin cutting effect is guaranteed, and the performance of a semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of the semiconductor structure is still to be improved. Now, a method for forming a semiconductor structure is combined, and a fin post-cutting (Cut Last) process in a fin cutting process is taken as an example to analyze the reason that the performance of the semiconductor structure is still to be improved.
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 and a fin (not shown) protruding from the substrate 10 are formed, the fin including a device fin 12 for forming a device and a dummy fin 11 to be etched.
Referring to fig. 2, a mask layer 20 is formed on the substrate 10, the mask layer 20 covers the device fin 12 and exposes the dummy fin 11.
Referring to fig. 3, the dummy fin 11 is etched using the mask layer 20 as a mask.
However, as the accommodating feature size decreases, the spacing (space) between adjacent fins also decreases, which correspondingly decreases the process window of the fin cutting process, thereby affecting the effectiveness of the fin cutting process.
For example: on the one hand, the mask layer 20 is easy to cover part of the dummy fin 11 due to the influence of depth of focus (DOF) or offset (overlay shift) in the photolithography process, so that a fence (fe) defect is generated due to the fact that part of the dummy fin 11 is not etched, the fence defect is generated, the isolation structure formed later is easy to cover the rest of the dummy fin 11 completely, the electrical isolation effect of the isolation structure is affected, unwanted devices are formed on the dummy fin 11 exposed to the isolation structure, and in addition, noise in the substrate 10 is increased due to the existence of the fe defect. On the other hand, the mask layer 20 may expose a portion of the device fin 12, so that the device fin 12 may be damaged by etching.
Both of the above conditions may lead to reduced performance of the semiconductor structure.
Moreover, during the etching of the dummy fin 11, damage to the substrate 10 is also easily caused, thereby further deteriorating the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: the substrate comprises a device region and an isolation region adjacent to the device region, wherein the device region is used for forming a device fin part; forming a first mask layer on a device region of the substrate, and forming a second mask layer on an isolation region of the substrate; etching the base with partial thickness by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part protruding out of the initial substrate; removing the second mask layer after the top fin portion is formed, and taking the first mask layer as a fin portion mask layer after the second mask layer is removed; and etching the initial substrate with partial thickness by taking the fin mask layer and the top fin of the isolation region as masks to form a substrate, a pseudo fin protruding out of the substrate of the isolation region and a bottom fin located between the top fin of the device region and the substrate, wherein the bottom fin and the top fin of the device region form the device fin.
In the embodiment of the invention, the first mask layer and the second mask layer are used as masks, the base with partial thickness is etched to form an initial substrate and a top fin part protruding out of the initial substrate, then the second mask layer is removed, after the second mask layer is removed, the first mask layer is used as a fin part mask layer, and correspondingly, when the initial substrate with partial thickness is etched, the fin part mask layer and the top fin part of the isolation region are used as masks; the material of the top fin part is the same as that of the initial substrate, the top fin part of the isolation region is correspondingly etched while the initial substrate exposed by the top fin part is etched, and when the top fin part of the isolation region is completely removed, the initial substrate material below the top fin part of the isolation region is continuously etched, so that after the dummy fin part and the bottom fin part are formed, the top of the dummy fin part is lower than the top of the bottom fin part, the fin cutting process effect is realized, and compared with the scheme of directly adopting a mask for fin cutting, the process window is increased, thereby guaranteeing the fin cutting effect, reducing the damage to the fin part of a device and further improving the performance of a semiconductor structure.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 including a device region 100a and an isolation region 100b adjacent to the device region 100a, the device region 100a being used to form a device fin.
The base 100 is used to prepare for the subsequent formation of a substrate and device fins protruding from the substrate.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.
In this embodiment, the substrate 100 is a unitary structure. In other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used as a substrate, and the second semiconductor layer is used to form a device fin.
Referring to fig. 9, a first mask layer 202 is formed on the device region 100a of the substrate 100, and a second mask layer 201 is formed on the isolation region 100b of the substrate 100.
The subsequent process includes etching a portion of the thickness of the substrate 100, and the first mask layer 202 and the second mask layer 201 are used as masks for the etching process.
In this embodiment, after the first mask layer 202 and the second mask layer 201 are formed, the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202.
After etching the substrate 100 with a partial thickness, the remaining substrate 100 is used as an initial substrate, and after etching the substrate 100 with a partial thickness, the step of removing the second mask layer 201 is further included. By making the top surface of the second mask layer 201 lower than the top surface of the first mask layer 202, the second mask layer 201 can be removed by maskless etching, so as to reduce the complexity of the process. Moreover, when the second mask layer 201 is removed by using a maskless etching method, a part of the first mask layer 202 with a certain height is removed, and the first mask layer 202 still has a residual part of thickness, and the remaining first mask layer 202 can be used as a mask for subsequent etching of the initial substrate.
After the second mask layer 201 is removed later, the remaining first mask layer 202 is used as a fin mask layer, and the fin mask layer is used as a mask for etching the initial substrate later.
Therefore, after forming the first mask layer 202 and the second mask layer 201, the height of the first mask layer 202 should not be too small or too large. If the height of the first mask layer 202 is too small, after the second mask layer 201 is removed later, the remaining height of the first mask layer 202 is easily caused to be too small, that is, the height of the fin mask layer is caused to be too small, so that the fin mask layer is easily caused to be unable to play a role of etching mask; if the height of the first mask layer 202 is too large, the process cost and time will be wasted correspondingly, and the difficulty of the subsequent process for removing the fin mask layer will be increased. For this purpose, in this embodiment, the height of the first mask layer 202 is 20nm to 50nm.
Accordingly, the height of the second mask layer 201 is 20nm to 50nm.
It should be noted that, after the first mask layer 202 and the second mask layer 201 are formed, the ratio of the height of the second mask layer 201 to the height of the first mask layer 202 should not be too small or too large. If the ratio is too large, that is, the difference between the heights of the first mask layer 202 and the second mask layer 201 is too small, the remaining first mask layer 202 is easy to be too small after the second mask layer 201 is removed, that is, the fin mask layer is easy to be too small, so that the fin mask layer cannot play a role in etching mask; if the ratio is too small, that is, the difference between the heights of the first mask layer 202 and the second mask layer 201 is too large, under the condition that the heights of the fin mask layers meet the process requirement, the heights of the second mask layer 201 are correspondingly too small, so that the second mask layer 201 cannot play a role of etching mask in the process of etching the substrate 100 easily. For this reason, in this embodiment, the height of the second mask layer 201 is 1/4 to 1/2 of the height of the first mask layer 202.
In this embodiment, the device fin portion is formed by using a self-aligned multiple patterning process to increase the density of the device fin portion formed on the substrate, and further reduce the pitch (pitch) of the adjacent device fin portion, so that the photolithography process overcomes the limitation of the photolithography resolution.
As an example, the self-aligned multiple patterning process is a self-aligned double patterning (SADP) process. In other embodiments, the self-aligned multiple patterning process may also be a self-aligned quad patterning (self-aligned quadruple patterning, SAQP) process.
The material of any one of the first mask layer 202 and the second mask layer 201 includes one or more of silicon nitride, silicon carbonitride, silicon oxynitride, silicon nitride oxide, boron nitride, and boron carbonitride.
The material density and hardness of the first mask layer 202 and the second mask layer 201 are both higher, and in the subsequent process of etching the substrate 100, the material of the substrate 100 has a higher etching selectivity ratio with the material of the first mask layer 202 and the material of the second mask layer 201, so that the first mask layer 202 and the second mask layer 201 can better perform the function of etching a mask.
In this embodiment, the materials of the first mask layer 202 and the second mask layer 201 are silicon nitride.
The steps of forming the first mask layer 202 and the second mask layer 201 are specifically described below with reference to fig. 4 to 9.
Referring to fig. 4, a core layer 110 is formed on the substrate 100.
The core layer 110 is used to provide a process basis for forming a mask sidewall. The mask side wall is used for preparing for forming a first mask layer and a second mask layer.
After the first mask layer and the second mask layer are formed later, the core layer 110 is also removed, so that the core layer 110 is a material that is easy to be removed, and the process of removing the core layer 110 has less damage to the first mask layer, the second mask layer and the substrate 100.
For this purpose, in the present embodiment, the material of the core layer 110 is amorphous silicon. Amorphous silicon is a common core layer material in SADP processes. In other embodiments, the material of the core layer may also be amorphous carbon.
Referring to fig. 5, mask spacers 200 are formed on sidewalls of the core layer 110.
The mask sidewall 200 in the device region 100a is used as the first mask layer 202, and the mask sidewall 200 in the isolation region 100b is used to provide a process basis for forming a second mask layer.
Specifically, the step of forming the mask sidewall 200 includes: forming a sidewall film conformally covering the core layer 110 and the substrate 100; and removing the sidewall film on the substrate 100 and on the top of the core layer 110, and reserving the sidewall film on the sidewall of the core layer 110 as the mask sidewall 200.
In this embodiment, an atomic layer deposition process is used to form the sidewall film. The atomic layer deposition process is used for forming a film by depositing the film layer by layer in a monoatomic layer mode, is generally used for growing the film with controllable atomic scale, has strong gap filling capability and step covering capability, is beneficial to improving the forming quality and thickness uniformity of the side wall film, reduces the control difficulty of the side wall film thickness, and is beneficial to improving the conformal covering effect of the side wall film.
In other embodiments, the sidewall film may also be formed by a chemical vapor deposition process.
In this embodiment, an anisotropic etching process is used to etch the sidewall film along a direction perpendicular to the surface of the substrate 100, so that the sidewall film on the sidewall of the core layer 110 can be retained while removing the sidewall film on the substrate 100 and on the top of the core layer 110. Specifically, the anisotropic etching process is an anisotropic dry etching process, which is a low-cost anisotropic etching process.
In this embodiment, the mask sidewall 200 is made of silicon nitride.
Referring to fig. 6 to 8 in combination, the mask sidewall 200 (shown in fig. 6) of a portion of the height of the isolation region 100b is removed, and the remaining mask sidewall 200 located in the isolation region 100b is used as the second mask layer 201 (shown in fig. 7).
The mask sidewall 200 is removed from the isolation region 100b to a partial height so that the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202.
Specifically, the step of removing the mask sidewall 200 with a portion of the height in the isolation region 100b includes: forming a shielding layer 210 on the substrate 100, wherein the shielding layer 210 covers the first mask layer 202 and exposes the mask sidewall 200 located in the isolation region 100 b; and etching the mask side wall 200 with a part of the height in the isolation region 100b by taking the shielding layer 210 as a mask.
The shielding layer 210 functions as an etching mask for protecting the first mask layer 202, thereby preventing the height of the first mask layer 202 from being affected.
The shielding layer 210 may have a single-layer structure or a stacked-layer structure, and the material of the shielding layer 210 is a material commonly used as an etching mask in the semiconductor field.
In this embodiment, the material of the shielding layer 210 is photoresist. In other embodiments, the material of the barrier layer may also be a bottom antireflective coating material (BARC).
The shielding layer 210 may expose the mask sidewall 200 in the isolation region 100 b. In this embodiment, in order to increase the process window for forming the shielding layer 210, the shielding layer 210 covers the substrate 100, the first mask layer 202, and the core layer 110 of the device region 100 a.
In this embodiment, an anisotropic etching process is used to remove a portion of the mask sidewall 200 in the isolation region 100b, so that the mask sidewall 200 in the isolation region 100b can be etched along a direction perpendicular to the surface of the substrate 100, and the influence on the width of the mask sidewall 200 in the isolation region 100b is reduced while the height of the mask sidewall 200 in the isolation region 100b is reduced.
Specifically, the anisotropic etching process is an anisotropic dry etching process.
As shown in fig. 8, in this embodiment, after forming the second mask layer 201, the method further includes: the masking layer 210 is removed (as shown in fig. 7).
By removing the masking layer 210, provision is made for subsequent steps of removing the core layer 110 and etching the substrate 100.
In this embodiment, an ashing process is used to remove the shielding layer 210.
Referring to fig. 9, after removing the shielding layer 210 (as shown in fig. 7), the method further includes: the core layer 110 is removed (as shown in fig. 8).
The core layer 110 is removed to expose a portion of the substrate 100, thereby providing for a subsequent step of etching the substrate 100.
In this embodiment, the core layer 110 is etched and removed by a wet etching process. Specifically, the material of the core layer 110 is amorphous silicon, and the etching solution used in the wet etching process is Cl 2 And HBr or TMAH. In other embodiments, a dry etching process, or a combination of dry and wet etching processes may be used to remove the core layer.
Referring to fig. 10, with the first mask layer 202 and the second mask layer 201 as masks, etching a portion of the substrate 100 to form an initial substrate 101 and a top fin 310 protruding from the initial substrate 101.
The top fin 310 of the device region 100a is used as part of the device fin, and the top fin 310 of the isolation region 100b is used as a mask for subsequent etching of the initial substrate 101.
The subsequent process further includes removing the second mask layer 201, so that the remaining first mask layer 202 is used as a fin mask layer, and after removing the second mask layer 201, etching a portion of the initial substrate 101 with a thickness of the initial substrate 101 with the fin mask layer and the top fin 310 of the isolation region 100b as masks, to form a substrate, a dummy fin protruding from the substrate of the isolation region 100b, and a bottom fin located between the top fin 310 and the substrate of the device region 100a, where the bottom fin and the top fin 310 of the device region 100a form a device fin.
The materials of the top fin 310 and the initial substrate 101 are the same, and the top fin 310 of the isolation region 100b is etched while the initial substrate 101 exposed by the top fin 310 is etched, and after the top fin 310 of the isolation region 100b is completely removed, the initial substrate 101 material below the top fin 310 of the isolation region 100b is further etched, so that after the dummy fin and the bottom fin are formed, the top surface of the dummy fin is lower than the top surface of the bottom fin, so as to achieve the fin cutting process effect.
In this embodiment, the first mask layer 202 and the second mask layer 201 are used as masks, and an anisotropic dry etching process is used to etch a portion of the thickness of the substrate 100. The anisotropic dry etching process has good etching profile control, and the anisotropic dry etching process is selected to be beneficial to improving the sidewall flatness of the top fin 310 and to easily control the height of the top fin 310.
It should be noted that, although the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202, the first mask layer 202 and the second mask layer 201 still have the same function due to the higher etching selectivity ratio of the substrate 100 to the second mask layer 201, and accordingly, the etching effect of the embodiment on the substrate 100 of the device region 100a and the isolation region 100b is the same.
In this embodiment, after the top fin 310 is formed, the height of the top fin 310 is greater than or equal to the effective height of the device fin. The effective height of the device fin refers to the height covered by the gate structure in the device fin, that is, the height of the device fin exposed by the isolation structure.
The height of the top fin 310 is greater than or equal to the effective height of the device fin, so that, after the isolation structure is formed on the substrate, the top surface of the isolation structure is flush with the bottom surface of the top fin 310, or the top surface of the isolation structure is higher than the bottom surface of the top fin 310; and after the dummy fin portion and the bottom fin portion are formed subsequently, the top surface of the dummy fin portion is lower than the top surface of the bottom fin portion, that is, the top surface of the dummy fin portion is lower than the bottom surface of the top fin portion 310, so that the isolation structure can completely cover the dummy fin portion, further, the influence of the dummy fin portion on the electrical isolation effect of the isolation structure is avoided, and the unnecessary devices formed by exposing the dummy fin portion to the isolation structure can be avoided.
Moreover, compared with the scheme of forming the device fin portion through one-step etching, the etching time required for forming the top fin portion 310 is shorter, so that less polymer is accumulated in the process of etching to form the top fin portion 310, and the influence of the polymer on etching tracks is smaller, thereby being beneficial to improving the verticality of the side wall of the top fin portion 310, further being beneficial to improving the control capability of a subsequent gate structure on a channel and improving the short channel effect and the barrier lowering (drain induced barrier lowering, DIBL) effect introduced by a drain end.
However, the ratio of the top fin 310 height to the device fin effective height should not be too great. If the ratio is too large, the height of the subsequent pseudo fin portions is easily caused to be too large, so that the possibility that the pseudo fin portions are exposed out of the isolation structure is increased, and the performance of the transistor is adversely affected. For this reason, in this embodiment, the height of the top fin 310 is 1 to 1.5 times the effective height of the device fin.
Wherein, the etching time of the dry etching process is reasonably adjusted, so that the height of the top fin portion 310 can meet the process requirement.
Referring to fig. 11, after forming the top fin 310, the second mask layer 201 (as shown in fig. 10) is removed, and after removing the second mask layer 201, the first mask layer 202 (as shown in fig. 10) serves as a fin mask layer 205.
After the second mask layer 201 is removed, the top fin 310 of the isolation region 100b is exposed, and the top fin 310 of the isolation region 100b and the fin mask layer 205 are used as a mask for etching the initial substrate 101.
As can be seen from the foregoing description, by removing the second mask layer 201, the process window is increased, so that the fin cutting effect is ensured, and the damage to the fin portion of the device is reduced, thereby improving the performance of the semiconductor structure.
In this embodiment, before the second mask layer 201 is removed, the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202, so a maskless etching process is used to remove the second mask layer 201, thereby simplifying the process complexity and reducing the process cost.
In addition, compared with the scheme of forming a pattern layer (e.g., photoresist layer) covering the first mask layer and removing the second mask layer by using the pattern layer as a mask, the embodiment can avoid the influence of the forming process and the removing process of the pattern layer on the top fin portion 310 by making the top surface of the second mask layer 201 lower than the top surface of the first mask layer 202 and adopting a maskless etching manner, thereby being beneficial to improving the quality of the subsequent fin portions and further improving the performance of the semiconductor structure.
Correspondingly, in the process of removing the second mask layer 201, a part of the first mask layer 202 with a height is also removed, and the remaining first mask layer 202 is used as the fin mask layer 205. Specifically, the height of the first mask layer 202 is reduced by an amount equal to the height of the second mask layer 201.
The height of the first mask layer 202 is 20nm to 50nm, and the height of the second mask layer 201 is 1/4 to 1/2 of the height of the first mask layer 202, so that the thickness of the fin mask layer 205 can still meet the process requirement, and the fin mask layer 205 plays a role of etching mask in the process of etching the initial substrate 101.
In this embodiment, an anisotropic etching process is used to remove the second mask layer 201 and a portion of the first mask layer 202. By using an anisotropic etching process, the second mask layer 201 and a portion of the height of the first mask layer 202 are etched away in a direction perpendicular to the surface of the initial substrate 101, so as to reduce the influence on the width of the fin mask layer 205.
Specifically, when the second mask layer 201 and the first mask layer 202 with a partial height are etched and removed, the anisotropic etching process is an anisotropic dry etching process.
The second mask layer 201 and the first mask layer 202 have a higher etching selectivity ratio to the initial substrate 101, so that the loss of the initial substrate 101 is smaller in the process of etching and removing the second mask layer 201 and a part of the first mask layer 202 with a height.
It should be noted that, in other embodiments, according to actual process conditions, etching may not be performed on the mask sidewall of the isolation region, and correspondingly, after the initial substrate and the fin portion protruding from the top of the initial substrate are formed, the second mask layer in the isolation region is removed by using a mask (mask).
Referring to fig. 12, with the fin mask 205 and the top fin 310 (shown in fig. 11) of the isolation region 100b as masks, etching a portion of the initial substrate 101 (shown in fig. 11) to form a substrate 102, a dummy fin 330 protruding from the substrate 102 of the isolation region 100b, and a bottom fin 320 located between the top fin 310 and the substrate 102 of the device region 100 a.
The bottom fin 320 and the top fin 310 of the device region 100a constitute a device fin 300, the device fin 300 being used to provide a channel of a transistor. Wherein the dashed line in fig. 12 is used to indicate the boundary between bottom fin 320 and top fin 310.
As can be seen from the foregoing description, the initial substrate 101 exposed by the top fin 310 is etched, and the top fin 310 of the isolation region 100b is correspondingly etched, so that after the dummy fin 330 and the bottom fin 320 are formed, the top surface of the dummy fin 330 is lower than the top surface of the bottom fin 320, so as to achieve the fin cutting effect, and compared with the scheme of directly performing fin cutting by using a mask (i.e. the conventional fin cutting process), the process window is increased, thereby ensuring the fin cutting effect, reducing the damage to the device fin 300, and further improving the performance of the semiconductor structure.
In this embodiment, an anisotropic dry etching process is used to etch a portion of the thickness of the initial substrate 101. The anisotropic dry etching process has good etching profile control, and the anisotropic dry etching process is selected to be beneficial to improving the sidewall flatness of the bottom fin portion 320 and to easily control the height of the bottom fin portion 320.
The etching time of the dry etching process is reasonably adjusted, so that the height of the bottom fin 320 can meet the process requirement, and the height of the device fin 300 can meet the process requirement.
Moreover, compared to the scheme of forming the device Fin by one-step etching, the etching time required for forming the bottom Fin 320 is also shorter, which is also advantageous for improving the sidewall verticality of the bottom Fin 320, thereby improving the sidewall verticality of the device Fin 300, and further improving the sidewall verticality of the effective Fin (effective Fin), i.e., for reducing the difference between the top width and the bottom width of the effective Fin, thereby improving the performance of the semiconductor structure. The effective fin refers to a portion of the device fin 300 covered by the gate structure.
Referring to fig. 13 in combination, after forming the device fin 300, the forming method further includes: an isolation structure 103 is formed on the substrate 102 where the device fin 300 is exposed, the isolation structure 103 covers the dummy fin 330, and a top surface of the isolation structure 103 is lower than a top surface of the device fin 300.
The isolation structure 103 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent devices.
In this embodiment, the material of the isolation structure 103 is silicon oxide. In other embodiments, the material of the isolation structure may be silicon nitride or other insulating materials such as silicon oxynitride.
Specifically, the step of forming the isolation structure 103 includes: forming an isolation material layer on the substrate 102, the isolation material layer covering the fin mask layer 205 (as shown in fig. 12); removing the isolation material layer higher than the top of the fin mask layer 205 by adopting a planarization process, and exposing the top of the fin mask layer 205; removing the fin mask layer 205; after removing the fin mask layer 205, performing etching back treatment on the remaining isolation material layer, so as to form the isolation structure 103.
In this embodiment, by the foregoing method, the fin cutting process effect is improved, not only the process window of the fin cutting process is increased, but also the fe defect is improved, and the probability that the dummy fin 330 is exposed to the isolation structure 103 is reduced, so that the performance of the semiconductor structure is ensured.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the forming method. Referring in conjunction to fig. 11, a schematic structural diagram of one embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: an initial substrate 101, wherein the initial substrate 101 includes a device region 100a and an isolation region 100b adjacent to the device region 100a, and the device region 100a is used for forming a device fin; a top fin 310 located on the device region 100a and the isolation region 100b of the initial substrate 101, respectively, wherein the top fin 310 is made of the same material as the initial substrate 101; fin mask layer 205 is located on top of top fin 310 of device region 100 a.
And etching a part of the initial substrate 101 with a thickness by using the fin mask layer 205 and the top fin 310 of the isolation region 100b as masks, so as to form a substrate, a pseudo fin protruding out of the substrate of the isolation region 100b, and a top fin located between the top fin 310 of the device region 100a and the substrate, wherein the top fin 310 and the top fin of the device region 100a form a device fin. Wherein the device fin is to provide a channel of the transistor.
The materials of the top fin portion 310 and the initial substrate 101 are the same, and the top fin portion 310 of the isolation region 100b is etched while the initial substrate 101 exposed by the top fin portion 310 is etched, and after the top fin portion 310 of the isolation region 100b is completely removed, the initial substrate 101 material below the top fin portion 310 of the isolation region 100b is further etched, so that after the dummy fin portion and the bottom fin portion are formed, the top of the dummy fin portion is lower than the top of the bottom fin portion, so as to achieve the fin cutting process effect.
In this embodiment, the material of the initial substrate 101 is silicon. In other embodiments, the material of the initial substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In this embodiment, the initial substrate 101 is a unitary structure. In other embodiments, the initial substrate 101 may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used as a substrate, and the second semiconductor layer is used to form the bottom fin.
The top fin 310 of the device region 100a is used as part of the device fin, and the top fin 310 of the isolation region 100b is used as a mask for etching the initial substrate 101.
In this embodiment, the top fin 310 and the initial substrate 101 are formed by etching the same substrate, so that the top fin 310 and the initial substrate 101 are in an integral structure, and the materials of the top fin 310 and the initial substrate 101 are the same.
In this embodiment, the height of the top fin 310 is greater than or equal to the effective height of the device fin. The effective height of the device fin refers to the height covered by the gate structure in the device fin, that is, the height of the device fin exposed by the isolation structure.
The height of the top fin 310 is greater than or equal to the effective height of the device fin, so that, after the isolation structure is formed on the substrate, the top surface of the isolation structure is flush with the bottom surface of the top fin 310, or the top surface of the isolation structure is higher than the bottom surface of the top fin 310; and after the dummy fin portion and the bottom fin portion are formed subsequently, the top surface of the dummy fin portion is lower than the top surface of the bottom fin portion, that is, the top surface of the dummy fin portion is lower than the bottom surface of the top fin portion 310, so that the isolation structure can completely cover the dummy fin portion, further, the influence of the dummy fin portion on the electrical isolation effect of the isolation structure is avoided, and the unnecessary devices formed by exposing the dummy fin portion to the isolation structure can be avoided.
However, the ratio of the top fin 310 height to the device fin effective height should not be too great. If the ratio is too large, the height of the subsequent dummy fin portions is easily caused to be too large, so that the possibility that the dummy fin portions are exposed out of the isolation structure is increased, and the performance of the semiconductor structure is adversely affected. For this reason, in this embodiment, the height of the top fin 310 is 1 to 1.5 times the effective height of the device fin.
The fin mask layer 205 is used as a mask for etching the initial substrate 101.
The fin mask layer 205 may be made of one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The material density and hardness of the fin mask layer 205 are both higher, and in the subsequent etching process of the initial substrate 101, the material of the initial substrate 101 and the material of the fin mask layer 205 have a higher etching selection ratio, so that the fin mask layer 205 can better perform the function of etching mask.
In this embodiment, the fin mask layer 205 is made of silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a device region and an isolation region adjacent to the device region, and the device region is used for forming a device fin part;
Forming a first mask layer on a device region of the substrate, and forming a second mask layer on an isolation region of the substrate; the step of forming the first mask layer and the second mask layer comprises the following steps: forming a mask side wall, wherein the mask side wall positioned in the device region is used as a first mask layer; removing part of the mask side wall at the height in the isolation region, wherein the remaining mask side wall in the isolation region is used as a second mask layer, and the top surface of the second mask layer is lower than the top surface of the first mask layer;
etching the base with partial thickness by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part protruding out of the initial substrate;
removing the second mask layer after the top fin portion is formed, and taking the first mask layer as a fin portion mask layer after the second mask layer is removed;
and etching the initial substrate with partial thickness by taking the fin mask layer and the top fin of the isolation region as masks to form a substrate, a pseudo fin protruding out of the substrate of the isolation region and a bottom fin located between the top fin of the device region and the substrate, wherein the bottom fin and the top fin of the device region form the device fin.
2. The method of forming a semiconductor structure of claim 1, wherein,
the method for forming the semiconductor structure further comprises the following steps: and in the process of removing the second mask layer, removing part of the first mask layer with the height, and taking the rest of the first mask layer as the fin part mask layer.
3. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first mask layer and the second mask layer comprises: forming a core layer on the substrate;
forming a mask side wall on the side wall of the core layer, wherein the mask side wall located in the device region is used as the first mask layer;
removing part of the mask side wall at the height in the isolation region, wherein the remaining mask side wall in the isolation region is used as the second mask layer;
and removing the core layer after removing the mask side wall of the isolation region with partial height.
4. The method of forming a semiconductor structure of claim 1, wherein removing a portion of the mask sidewall of the isolation region comprises: forming a shielding layer on the substrate, wherein the shielding layer covers the first mask layer and exposes a mask side wall positioned in the isolation region;
Etching the mask side wall with partial height in the isolation region by taking the shielding layer as a mask;
and removing the shielding layer.
5. The method of forming a semiconductor structure of claim 3, wherein forming mask spacers on sidewalls of the core layer comprises: forming a side wall film which conformally covers the core layer and the substrate;
and removing the side wall films on the substrate and the top of the core layer, and reserving the side wall films on the side wall of the core layer as the mask side wall.
6. The method of claim 1, wherein an anisotropic etching process is used to remove a portion of the mask sidewall of the isolation region.
7. The method of forming a semiconductor structure of claim 1 or 2, wherein after forming the first mask layer and the second mask layer, the second mask layer has a height of 1/4 to 1/2 of the height of the first mask layer.
8. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a first mask layer on the substrate of the device region, a height of the first mask layer is 20nm to 50nm.
9. The method of claim 1, wherein in forming the top fin, a height of the top fin is greater than or equal to an effective height of the device fin.
10. The method of claim 9, wherein a height of the top fin is 1 to 1.5 times an effective height of the device fin.
11. The method of forming a semiconductor structure of claim 2, wherein the second mask layer and a portion of the height of the first mask layer are removed using an anisotropic etching process.
12. The method of forming a semiconductor structure of claim 6 or 11, wherein the anisotropic etching process is an anisotropic dry etching process.
13. The method of forming a semiconductor structure of claim 1 or 2, wherein the material of either of the first mask layer and the second mask layer comprises one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
14. The method of claim 3, wherein the material of the core layer is amorphous silicon or amorphous carbon.
15. The method of forming a semiconductor structure of claim 1, further comprising, after forming the device fin: and forming an isolation structure on the substrate exposed by the device fin part, wherein the isolation structure covers the pseudo fin part, and the top surface of the isolation structure is lower than the top surface of the device fin part.
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Citations (2)

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US9337050B1 (en) * 2014-12-05 2016-05-10 Globalfoundries Inc. Methods of forming fins for finFET semiconductor devices and the selective removal of such fins
CN108807534A (en) * 2017-05-03 2018-11-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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US20150206759A1 (en) * 2014-01-21 2015-07-23 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US10361125B2 (en) * 2017-12-19 2019-07-23 International Business Machines Corporation Methods and structures for forming uniform fins when using hardmask patterns

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US9337050B1 (en) * 2014-12-05 2016-05-10 Globalfoundries Inc. Methods of forming fins for finFET semiconductor devices and the selective removal of such fins
CN108807534A (en) * 2017-05-03 2018-11-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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