CN114256159A - Array substrate, manufacturing method and display panel - Google Patents

Array substrate, manufacturing method and display panel Download PDF

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Publication number
CN114256159A
CN114256159A CN202111576526.0A CN202111576526A CN114256159A CN 114256159 A CN114256159 A CN 114256159A CN 202111576526 A CN202111576526 A CN 202111576526A CN 114256159 A CN114256159 A CN 114256159A
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layer
photoresist
electrode
substrate
metal layer
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CN114256159B (en
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张盛东
周晓梁
廖聪维
林清平
杨欢
邹忠飞
钟德镇
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Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
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Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

An array substrate, a manufacturing method and a display panel are provided, wherein the manufacturing method comprises the following steps: forming a scanning line and a grid electrode on a substrate, wherein the scanning line is provided with an overlapping part, the width of the overlapping part is less than or equal to twice the retracting amount of the photoresist, and the width of the grid electrode is greater than twice the retracting amount of the photoresist; forming a first insulating layer on a substrate; forming an active layer over the first insulating layer; coating a photoresist layer on the first insulating layer, carrying out photoetching treatment on the photoresist layer from one side of the substrate far away from the photoresist layer by using a first metal layer mask plate and forming a photoresist pattern, wherein the grid electrode corresponds to the photoresist pattern, and the photoresist pattern is completely staggered with the overlapped part; and forming a second metal layer on the upper surface of the photoresist layer, etching the second metal layer and removing the photoresist pattern, wherein the second metal layer forms a data line, a source electrode and a drain electrode, and the projection of the data line on the substrate is overlapped with the projection of the overlapped part on the substrate. The invention simplifies the manufacturing process, reduces the manufacturing cost and improves the manufacturing efficiency.

Description

Array substrate, manufacturing method and display panel
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method and a display panel.
Background
With the development of display technology, a light and thin display panel is popular with consumers, especially a light and thin display panel (LCD).
When the display device works, a driving voltage is respectively applied to a pixel electrode of the Thin Film Transistor Array Substrate and a common electrode of the Color Film Substrate or applied to a common electrode and a pixel electrode of the Thin Film Transistor Array Substrate, and a rotation direction of liquid crystal molecules between the two substrates is controlled, so that backlight provided by a backlight module of the display device is refracted, and a picture is displayed.
The thin film transistor array substrate is provided with a plurality of Thin Film Transistors (TFTs), the TFTs comprise a grid electrode, a source electrode, a drain electrode and an active layer, the length of the grid electrode cannot be shortened due to the fact that the alignment problem of the grid electrode and the alignment problem of the source electrode and the drain electrode need to be considered, the overlapping amount of the grid electrode and the source electrode and the drain electrode is larger, and the parasitic capacitance of a TFT device is also larger. In order to reduce the overlap area between the gate and the source/drain, the prior art uses a photoresist stripping process and a back exposure process to disconnect the source and the drain, i.e. before covering the metal layer, a layer of photoresist is covered, the gate is used as a shield, the photoresist on the metal layer is exposed by adopting the back exposure process, the photoresist in the area corresponding to the gate is reserved, then a layer of metal layer is covered, when the photoresist is stripped, the source and the drain are disconnected, and the self-alignment of the overlap area between the gate and the source/drain is realized, so that the overlap area between the gate and the source/drain can be reduced, the parasitic capacitance between the gate and the source/drain is reduced, and the reliability of a gate driving circuit is improved.
However, the scan lines are usually made of the same metal layer as the gate electrodes, the data lines are usually made of the same metal layer as the source electrodes and the drain electrodes, and in order to prevent the data lines from being disconnected at the overlapping portions of the scan lines, a one-side front exposure process is also required to remove the photoresist at the overlapping portions of the data lines and the scan lines. Although the source electrode and the drain electrode are disconnected by using the photoresist stripping process and the back exposure process in the prior art, the self-alignment of the overlapping region of the gate electrode and the source electrode/drain electrode can be realized, and the overlapping region of the gate electrode and the source electrode/drain electrode and the parasitic capacitance are reduced, a front exposure process is added to ensure that the data line is not disconnected at the overlapping part of the scanning line any more, and the process is relatively complex.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate, a manufacturing method thereof and a display panel, so as to solve the problem that the self-alignment process in the prior art is complex.
The purpose of the invention is realized by the following technical scheme:
the invention provides a manufacturing method of an array substrate, which comprises the following steps:
providing a substrate;
forming a first metal layer above the substrate, etching the first metal layer, patterning the first metal layer to form a scanning line and a grid, wherein the grid is electrically connected with the scanning line, the scanning line is provided with an overlapped part which is overlapped with a data line up and down, the width of the overlapped part is less than or equal to twice of the photoresist retraction amount, and the width of the grid is greater than twice of the photoresist retraction amount;
forming a first insulating layer covering the scan lines and the gate electrode over the substrate;
forming a semiconductor layer over the first insulating layer, etching the semiconductor layer, the semiconductor layer being patterned to form an active layer;
coating a photoresist layer above the first insulating layer, and performing photoetching treatment on the photoresist layer from one side of the substrate far away from the photoresist layer by using the first metal layer mask plate, wherein the photoresist layer is patterned to form a photoresist pattern, the grid electrode corresponds to the photoresist pattern, and the photoresist pattern is completely staggered with the overlapped part;
forming a second metal layer on the upper surface of the photoresist layer, etching the second metal layer and removing the photoresist pattern, wherein the second metal layer is patterned to form the data line, the source electrode and the drain electrode, the projection of the data line on the substrate is overlapped with the projection of the overlapped part on the substrate, the data line is electrically connected with the source electrode, and the source electrode and the drain electrode are electrically connected through the active layer;
and forming a pixel electrode above the first insulating layer, wherein the pixel electrode is electrically connected with the drain electrode.
Furthermore, the semiconductor layer is made of a material capable of reducing the light diffraction range, and the second metal layer is directly arranged on the upper surface of the semiconductor layer.
Further, a diffraction interference layer is formed above the first insulating layer, the diffraction interference layer can reduce the light diffraction range, the second metal layer is directly arranged on the upper surface of the diffraction interference layer, and the semiconductor layer is directly arranged on the upper surface of the second metal layer.
Further, the width of the scanning line is the same as that of the overlapping part, and the width of the scanning line is less than or equal to twice the photoresist shrinkage; or the width of the scan line is greater than the width of the overlap portion.
Further, the number of the overlapped parts is multiple and the overlapped parts are arranged in parallel and at intervals.
Further, a common electrode is formed over the first insulating layer, the common electrode and the pixel electrode being insulated from each other.
The invention also provides an array substrate, which is manufactured by the manufacturing method, and the array substrate comprises the following components:
a substrate;
the first metal layer is arranged above the substrate and comprises a scanning line and a grid electrode, the grid electrode is electrically connected with the scanning line, the scanning line is provided with an overlapped part which is vertically overlapped with the data line, the width of the overlapped part is less than or equal to twice of the retraction amount of the photoresist, and the width of the grid electrode is more than twice of the retraction amount of the photoresist;
the first insulating layer is arranged above the first metal layer and covers the scanning line and the grid;
a semiconductor layer disposed over the first insulating layer, the semiconductor layer including an active layer;
a second metal layer disposed over the first insulating layer, the second metal layer including the data line, a source electrode, and a drain electrode, a projection of the data line on the substrate overlapping a projection of the overlap portion on the substrate, the data line being conductively connected to the source electrode, and the source electrode and the drain electrode being conductively connected through the active layer;
and the pixel electrode is arranged above the first insulating layer and is in conductive connection with the drain electrode.
Furthermore, the semiconductor layer is made of a material capable of reducing the light diffraction range, and the second metal layer is directly arranged on the upper surface of the semiconductor layer; or the array substrate further comprises a diffraction interference layer arranged above the first insulating layer, the diffraction interference layer can reduce the light diffraction range, the second metal layer is directly arranged on the upper surface of the diffraction interference layer, and the semiconductor layer is directly arranged on the upper surface of the second metal layer.
Further, the number of the overlapped parts is multiple and the overlapped parts are arranged in parallel at intervals; or the array substrate further comprises a common electrode arranged above the first insulating layer, and the common electrode and the pixel electrode are mutually insulated.
The invention also provides a display panel, which comprises the array substrate, an opposite substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the opposite substrate.
The invention has the beneficial effects that: by setting the width of the overlapping part of the scanning line and the data line to be less than or equal to two times of the retraction amount of the photoresist and the width of the grid electrode to be more than two times of the retraction amount of the photoresist, when the photoresist layer is subjected to photoetching treatment from one side of the substrate far away from the photoresist layer, the area of the photoresist layer corresponding to the overlapping part is developed and removed, and the area corresponding to the grid electrode is reserved and forms a photoresist pattern, so that after the second metal layer is etched and the photoresist pattern is removed, the overlapping part of the data line and the scanning line can be continuous, and the source electrode and the drain electrode can be automatically disconnected, thereby simplifying the manufacturing process, reducing the manufacturing cost and improving the manufacturing efficiency; and the photoresist pattern is formed by photoetching from the back of the substrate by taking the first metal layer as a mask plate, and the width of the photoresist pattern reserved in the gate region is the same as the distance between the disconnected positions of the source electrode and the drain electrode, so that the overlapped region of the gate electrode and the source electrode and the drain electrode is smaller, the parasitic capacitance of the gate electrode and the source electrode and the drain electrode is reduced, and the reliability of the gate drive circuit is improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of a conventional exposure and development process for a photoresist;
FIG. 3 is a schematic plan view of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view of the array substrate taken along the line A-A in FIG. 3 according to one embodiment of the present invention;
FIGS. 5a-5k are schematic cross-sectional views taken along A-A in FIG. 3 illustrating a method of fabricating a semiconductor device according to one embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of the array substrate taken along line B-B in FIG. 3 according to one embodiment of the present invention;
FIGS. 7a-7e are schematic cross-sectional views taken along line B-B in FIG. 3 illustrating a method of fabricating a semiconductor device according to one embodiment of the present invention;
FIGS. 8a-8f are schematic plan views illustrating a manufacturing method according to one embodiment of the invention;
FIG. 9 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;
FIG. 10 is a schematic cross-sectional view of the array substrate taken along line B-B in FIG. 3 according to a second embodiment of the present invention;
FIG. 11 is a schematic plan view of a first metal layer according to a second embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of the array substrate along the line B-B in FIG. 3 according to the third embodiment of the present invention;
FIG. 13 is a schematic plan view of a first metal layer according to a third embodiment of the present invention;
fig. 14 is a schematic cross-sectional view of the array substrate along a-a in fig. 3 according to a fourth embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the array substrate and the manufacturing method, and the display panel according to the present invention with reference to the accompanying drawings and the preferred embodiments is as follows:
[ example one ]
Fig. 3 is a schematic plan view of an array substrate according to a first embodiment of the present invention, fig. 4 is a schematic cross-sectional view of the array substrate along a-a in fig. 3 according to the first embodiment of the present invention, fig. 5a-5k are schematic cross-sectional views along a-a in fig. 3 according to a manufacturing method according to the first embodiment of the present invention, fig. 6 is a schematic cross-sectional view of the array substrate along B-B in fig. 3 according to the first embodiment of the present invention, fig. 7a-7e are schematic cross-sectional views along B-B in fig. 3 according to the manufacturing method according to the first embodiment of the present invention, fig. 8a-8f are schematic plan views of the manufacturing method according to the first embodiment of the present invention, and fig. 9 is a schematic cross-sectional structure of a display panel according to the first embodiment of the present invention.
As shown in fig. 3, 4 and 6, an array substrate according to an embodiment of the present invention includes:
the substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, and suitable materials for the flexible substrate include, for example, Polyethersulfone (PES), polyethylene naphthalate (PEN), Polyethylene (PE), Polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or a combination thereof.
The first metal layer 11 is disposed above the substrate 10, the first metal layer 11 includes a scan line 111 and a gate 112, and the gate 112 is electrically connected to the scan line 111. Among them, the first metal layer 11 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or employ a combination of the above metals such as Al/Mo, Cu/Mo, or the like.
In this embodiment, the scan line 111 has an overlapping portion 113 (fig. 6) overlapped with the data line 131, a width a1 (fig. 8a) of the scan line 111 is the same as the width of the overlapping portion 113, the width of the overlapping portion 113 is less than or equal to twice of the photoresist retraction amount, and the width a2 (fig. 8a) of the gate 112 is greater than twice of the photoresist retraction amount. The photoresist indentation amount of the photoresist is that when the photoresist is exposed by using the mask plate, certain diffraction effect can occur when light passes through the mask plate, so that the width of the photoresist left after development is smaller than the width of the corresponding pattern on the mask plate, and the width difference of the photoresist left after development and the corresponding pattern on the mask plate is the photoresist indentation amount S.
As shown in fig. 1-2, taking exposure from the back of the substrate 1 and taking the metal pattern 2 on the substrate 1 as a mask, when exposure is performed from the back of the substrate 1, a certain diffraction effect occurs on the edge of the metal pattern 2 by light passing through the substrate 1, so that after development, the photoresist 3 left on the metal pattern 2 is retracted compared with the metal pattern 2, and the illustrated single-sided photoresist retraction amount is S. For example, if the width of the metal pattern 2 is 10 μm and the width of the photoresist 3 left on the metal pattern 2 after development is 9 μm, the photoresist recession amount is 0.5 μm.
And a first insulating layer 101 disposed over the first metal layer 11, the first insulating layer 101 covering the scan lines 111 and the gate electrodes 112. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
And a semiconductor layer 12 disposed over the first insulating layer 101, the semiconductor layer 12 including an active layer 121, the active layer 121 corresponding to the gate electrode 112. In this embodiment, the semiconductor layer 12 is made of a material capable of reducing the diffraction range of light, and preferably, a material having a certain absorption effect on the ultraviolet light for exposure so as to reduce the amount of photoresist shrinkage. After the light passes through the semiconductor layer 12, since the semiconductor layer 12 absorbs the ultraviolet light to a certain extent, the diffraction phenomenon is reduced, so that the light passes through the semiconductor layer 12 for exposure, and the photoresist retraction amount is reduced. The semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor layer, for example, indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like. So that when the photoresist layer 100 is subjected to a photolithography process from the side of the substrate 10 (fig. 5d) away from the photoresist layer 100 (the back side of the substrate 10), the width of the remaining photoresist pattern 110 is closer to the width of the gate electrode 112. The overlapping area of the gate 112 and the source 132 and the drain 133 is made smaller to reduce the parasitic capacitance of the gate 112 and the source 132/drain 133, thereby improving the reliability of the gate driving circuit.
And a second metal layer 13 disposed on the upper surface of the semiconductor layer 12, wherein the second metal layer 13 includes a data line 131, a source electrode 132, and a drain electrode 133. The projection of the data line 131 on the substrate 10 overlaps the projection of the overlapping portion 113 on the substrate 10, i.e., the area where the scan line 111 and the data line 131 overlap is the overlapping portion 113. The data line 131 is electrically connected to the source electrode 132, and the source electrode 132 and the drain electrode 133 are electrically connected through the active layer 121. Among them, the second metal layer 13 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, Cu/Mo, or the like.
A second insulating layer 102 disposed on the upper surface of the second metal layer 13, and a transparent conductive layer 14 disposed on the upper surface of the second insulating layer 102. The second insulating layer 102 covers the second metal layer 13 and is provided with a contact hole 103 (fig. 5j) in a region corresponding to the drain electrode 133, the transparent conductive layer 14 includes a pixel electrode 141, and the pixel electrode 141 is electrically connected to the drain electrode 133 through the contact hole 103. The material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. The material of the transparent conductive layer 14 is Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Cadmium Tin Oxide (CTO), Aluminum Zinc Oxide (AZO), Indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).
As shown in fig. 5a to 5k, fig. 7a to 7e, and fig. 8a to 8f, the present embodiment further provides a manufacturing method of an array substrate, the manufacturing method is used for manufacturing the array substrate, and the manufacturing method includes:
as shown in fig. 5a, 7a and 8a, a substrate 10 is provided. The substrate 10 may be made of glass, quartz, silicon, acrylic, polycarbonate, or the like, and the substrate 10 may also be a flexible substrate, and suitable materials for the flexible substrate include, for example, Polyethersulfone (PES), polyethylene naphthalate (PEN), Polyethylene (PE), Polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or a combination thereof.
Forming a first metal layer 11 on the substrate 10, etching the first metal layer 11 to pattern the first metal layer 11 to form a scan line 111 and a gate 112, wherein the gate 112 is electrically connected to the scan line 111. Among them, the first metal layer 11 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or employ a combination of the above metals such as Al/Mo, Cu/Mo, or the like.
In the present embodiment, the scan line 111 has an overlapping portion 113 (fig. 6 and 8a) overlapping the data line 131, i.e., the overlapping portion 113 is a region where the scan line 111 overlaps the data line 131. The width a1 (fig. 8a) of the scan line 111 is the same as the width of the overlap 113, the width of the overlap 113 is less than or equal to twice the photoresist retraction S, and the width a2 (fig. 8a) of the gate 112 is greater than twice the photoresist retraction S. The photoresist retraction amount is that when the mask plate is used for exposing the photoresist, light rays penetrate through the mask plate to generate a certain diffraction effect, so that the width of the photoresist left after development is smaller than that of a corresponding pattern on the mask plate, and the width difference between the photoresist left after development and the corresponding pattern on the mask plate is the photoresist retraction amount S.
As shown in fig. 1-2, taking exposure from the back of the substrate 1 and taking the metal pattern 2 on the substrate 1 as a mask, when exposure is performed from the back of the substrate 1, a certain diffraction effect occurs on the edge of the metal pattern 2 by light passing through the substrate 1, so that after development, the photoresist 3 left on the metal pattern 2 is retracted compared with the metal pattern 2, and the illustrated single-sided photoresist retraction amount is S. For example, if the width of the metal pattern 2 is 10 μm and the width of the photoresist 3 left on the metal pattern 2 after development is 9 μm, the photoresist recession amount is 0.5 μm.
A first insulating layer 101 covering the scan line 111 and the gate electrode 112 is formed over the substrate 10. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 5b and 8b, the semiconductor layer 12 is formed over the first insulating layer 101, the semiconductor layer 12 is etched, the semiconductor layer 12 is patterned to form an active layer 121, and the active layer 121 corresponds to the gate electrode 112. The semiconductor layer 12 is made of a material which has a certain absorption effect on the ultraviolet light for exposure and can reduce the photoresist retraction amount, and after the light passes through the semiconductor layer 12, the diffraction phenomenon can be reduced because the semiconductor layer 12 has a certain absorption effect on the ultraviolet light, so that the light passes through the semiconductor layer 12 for exposure, and the photoresist retraction amount can be reduced. The semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor layer, for example, indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like.
As shown in fig. 5c to 5d, fig. 7b to 7c, and fig. 8c, a photoresist layer 100 is coated over the first insulating layer 101, and the photoresist layer 100 employs a positive photoresist. The photoresist layer 100 is exposed from the substrate 10 away from the photoresist layer 100 (i.e. the back of the substrate 10) by using the first metal layer 11 as a mask, and the photoresist layer 100 is left to form a photoresist pattern 110 after being developed. When the substrate 10 is exposed from the back side, the light passing through the substrate 10 is diffracted at the edge of the overlapping portion 113, so that after the development, the photoresist (if the photoresist is left) left on the overlapping portion 113 is retracted compared to the overlapping portion 113, assuming that the first photoresist retraction amount above the overlapping portion 113 and the scan line 111 is S1. In this embodiment, since the width a1 of the overlapped portion 113 is less than or equal to twice the first photoresist shrinkage amount S1 (i.e. a1<2 × S1), after the development, all the photoresist layers 100 directly above the overlapped portion 113 are developed and removed (fig. 7b-7 c); while the width a2 of the gate 112 is greater than twice the first photoresist recession amount S1 (i.e., a2>2 × S1), after development, the photoresist layer 100 directly above the gate 112 is retained and forms the photoresist pattern 110, i.e., after exposure and development from the back side of the substrate 10, the photoresist pattern 110 is retained only directly above the gate 112 (fig. 8 c); and because the gate 112 is covered with the semiconductor layer 12, the semiconductor layer 12 has the effect of reducing the photoresist shrinkage, so that the light passing through the substrate 10 is diffracted to a lower degree at the edge of the gate 112, and assuming that the photoresist pattern 110 left on the gate 112 after the development is S2 compared with the second photoresist shrinkage of the gate 112, there is S2< S1 (fig. 5c-5d), so that the width of the photoresist pattern 110 left right above the gate 112 is closer to the width of the gate 112, so that the overlapping area between the gate 112 and the source 132 or the drain 133 is smaller, thereby reducing the parasitic capacitance between the gate 112 and the source 132 or the drain 133 and improving the driving reliability. The first photoresist recession S1 is equal to the photoresist recession S and greater than the second photoresist recession by S2, i.e., S1 is S > S2.
As shown in fig. 5e to 5h, fig. 7d and fig. 8d, a second metal layer 13 is formed on the upper surface of the photoresist layer 100 (fig. 5e), and the second metal layer 13 is etched (fig. 5f to 5h), so that the second metal layer 13 is patterned to form a data line 131, a source electrode 132 and a drain electrode 133 (fig. 5h and fig. 8 d). The extending direction of the data line 131 intersects with the extending direction of the scan line 111, and the overlapping region where the scan line 111 and the data line 131 intersect with each other is an overlapping portion 113. Among them, the second metal layer 13 may employ a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, Cu/Mo, or the like.
The specific steps of etching the second metal layer 13 include:
as shown in fig. 5f, a photoresist 200 is coated on the upper surface of the second metal layer 13;
as shown in fig. 5g, the photoresist 200 is subjected to photolithography (exposure, development) using a mask plate, so that the photoresist 200 forms an etching stopper layer 210;
as shown in fig. 5h, fig. 7d and fig. 8d, the second metal layer 13 is wet-etched using the etching stop layer 210 as a barrier, and the exposed region of the second metal layer 13 (i.e., the region not covered by the etching stop layer 210) is removed, so that the second metal layer 13 is patterned to form the data line 131, the source electrode 132 and the drain electrode 133.
As shown in fig. 5i and 8e, the etch stopper layer 210 is removed and the photoresist pattern 110 is also removed, and since the photoresist pattern 110 is raised higher relative to other regions, the second metal layer 13 is broken at the edge of the photoresist pattern 110, when the photoresist pattern 110 is removed, the second metal layer 13 directly above the photoresist pattern 110 is also removed, so that after the photoresist pattern 110 is removed, the source electrode 132 and the drain electrode 133 are automatically disconnected, the channel 134 is formed between the source electrode 132 and the drain electrode 133, the data line 131 is electrically connected to the source electrode 132, and the source electrode 132 and the drain electrode 133 are electrically connected through the active layer 121. The width of the channel 134 is close to that of the gate 112, so that the overlapping area between the gate 112 and the source 132 or the drain 133 is small, the parasitic capacitance between the gate 112 and the source 132 or the drain 133 is reduced, the self-alignment of the overlapping area between the gate 112 and the source 132 or the drain 133 is realized, and the driving reliability is improved.
As shown in fig. 5j and 7e, a second insulating layer 102 is formed on the upper surface of the etched second metal layer 13, and the second insulating layer 102 covers the data line 131, the source electrode 132 and the drain electrode 133. The second insulating layer 102 is etched such that the second insulating layer 102 forms a contact hole 103 in a region corresponding to the drain electrode 133, and the upper surface of the drain electrode 133 is exposed through the contact hole 103. The material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 5k and 8f, a transparent conductive layer 14 is formed on the upper surface of the second insulating layer 102, the transparent conductive layer 14 is etched to form a pixel electrode 141, and the pixel electrode 141 fills the contact hole 103 and is electrically connected to the drain electrode 133. The transparent conductive layer 14 is made of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like.
In this embodiment, by setting the width of the overlapping portion 113 where the scan line 111 overlaps the data line 131 to be less than or equal to twice the photoresist shrinkage amount, and setting the width of the gate 112 to be greater than twice the photoresist shrinkage amount, when the photoresist layer 100 is subjected to the photolithography process from the side of the substrate 10 away from the photoresist layer 100, the region of the photoresist layer 100 corresponding to the overlapping portion 113 is developed and removed, and the region corresponding to the gate 112 remains and forms a photoresist pattern, so that after the second metal layer 13 is etched and the photoresist pattern 110 is removed, the data line 131 can be continuous at the overlapping portion with the scan line 111, and the source 132 and the drain 133 can be disconnected by itself, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the manufacturing efficiency; and the photoresist pattern 110 is formed by photolithography from the back side of the substrate 10 by using the first metal layer 11 as a mask plate, the width of the photoresist pattern 110 reserved in the gate 112 region is the same as the distance between the source 132 and the drain 133, so that the overlapping region of the gate 112 and the source 132 and the drain 133 is smaller, the parasitic capacitance of the gate 112 and the source 132 and the drain 133 is reduced, and the reliability of the gate driving circuit is improved.
As shown in fig. 9, the present embodiment further provides a display panel, which includes the array substrate, a counter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the counter substrate 20. The opposite substrate 20 is provided with an upper polarizer 41, the array substrate is provided with a lower polarizer 42, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and an alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is perpendicular to an alignment direction of the positive liquid crystal molecules 131 close to the array substrate, so that a TN display mode is formed. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
In this embodiment, the opposite substrate 20 is a color film substrate, a black matrix 21 and a color resistance layer 22 are disposed on the opposite substrate 20, the black matrix 21 corresponds to the scan line 111, the data line 141, the thin film transistor and the peripheral non-display region, and the black matrix 21 separates the color resistance layers 22. The color resist layer 22 includes color resist materials of three colors of red (R), green (G), and blue (B), and sub-pixels of the three colors of red (R), green (G), and blue (B) are correspondingly formed. The opposite substrate 20 is further provided with a common electrode 23 cooperating with the pixel electrode 141, and the pixel electrode 141 and the common electrode 23 are used to form a driving electric field to drive the positive liquid crystal molecules in the liquid crystal layer 30 to deflect, thereby controlling gray-scale brightness.
[ example two ]
Fig. 10 is a schematic cross-sectional view of the array substrate along the line B-B in fig. 3 according to the second embodiment of the present invention, and fig. 11 is a schematic plan view of the first metal layer according to the second embodiment of the present invention. As shown in fig. 10 and 11, the array substrate and the manufacturing method thereof, and the display panel provided in the second embodiment of the present invention are substantially the same as the array substrate and the manufacturing method thereof, and the display panel in the first embodiment (fig. 3 to 9), except that in this embodiment, the number of the overlapping portions 113 is multiple and the overlapping portions are arranged in parallel and at intervals, that is, the scanning lines 111 are provided with the openings 104 in the areas overlapped with the data lines 131, so as to form the overlapping portions 113 on the upper and lower sides of the openings 104, respectively. The width a3 of each overlap 113 is less than or equal to twice the first photoresist retraction amount S1, so that when the photoresist layer 100 is subjected to photolithography, the photoresist layer 100 is not retained in the region where the scan line 111 overlaps the data line 131, so that the data line 131 can be continuous in the corresponding overlap 113 region. Meanwhile, the plurality of overlapping portions 113 may also reduce the resistance of the scan line 111 to increase the conductive performance of the scan line 111.
In the present embodiment, the width a3 of each overlapping portion 113 is smaller than the width a1 of the scan line 111, i.e., the width a1 of the scan line 111 is greater than twice the first photoresist retraction amount S1, so as to reduce the resistance of the scan line 111.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ third example ]
Fig. 12 is a schematic cross-sectional view of the array substrate along the line B-B in fig. 3 according to the third embodiment of the present invention, and fig. 13 is a schematic plan view of the first metal layer according to the third embodiment of the present invention. As shown in fig. 12 and 13, the array substrate, the manufacturing method thereof, and the display panel according to the third embodiment of the present invention are substantially the same as the array substrate, the manufacturing method thereof, and the display panel according to the first embodiment (fig. 3 to 9), except that in this embodiment, the width a1 of the scan line 111 is greater than the width a3 of the overlapping portion 113, that is, the width a1 of the scan line 111 is greater than twice the first photoresist retraction amount S1, and the scan line 111 forms the notches 105 on both sides of the overlapping portion 113, so as to ensure that the data line 131 is continuous in the corresponding overlapping portion 113 region, and at the same time, the resistance of the scan line 111 can be reduced, and the conductivity of the scan line 111 can be increased.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ example four ]
Fig. 14 is a schematic cross-sectional view of the array substrate along a-a in fig. 3 according to a fourth embodiment of the invention. As shown in fig. 14, an array substrate according to a fourth embodiment of the present invention is substantially the same as the array substrate according to the first embodiment (fig. 3 to 9), except that in the present embodiment, the array substrate further includes a diffraction interference layer 151 disposed above the first insulating layer 101, the diffraction interference layer 151 can reduce a diffraction range of light, and after the light passes through the diffraction interference layer 151, the diffraction range is reduced, that is, the light passes through the diffraction interference layer 151 for photolithography, so that a retraction amount of a photoresist is reduced. The diffraction interference layer 151 is made of a light-transmitting material capable of reducing the diffraction range of light, and preferably made of a material having a certain absorption effect on ultraviolet light for exposure so as to reduce the amount of photoresist shrinkage.
The second metal layer 13 is directly disposed on the upper surface of the diffraction interference layer 151, and the second metal layer 13 includes a data line 131, a source electrode 132, and a drain electrode 133. The semiconductor layer 12 is directly disposed on the upper surface of the second metal layer 13, the semiconductor layer 12 includes an active layer 121, and the semiconductor layer 12 may be made of single crystal silicon or doped single crystal silicon.
Further, the array substrate further includes a common electrode 23 disposed above the first insulating layer 101, and the common electrode 23 is insulated and spaced apart from the pixel electrode 141 by a third insulating layer 106. The common electrode 23 has a slit structure and is located above the pixel electrode 141, and of course, the common electrode 23 may also be located below the pixel electrode 141, and the pixel electrode 141 has a slit structure, so as to form a Fringe Field Switching (FFS). Alternatively, the common electrode 23 and the pixel electrode 141 may be located at the same layer to form an In-Plane Switching (IPS) mode.
The present embodiment further provides a manufacturing method of an array substrate, which is substantially the same as the manufacturing method in the first embodiment (fig. 3 to 9), except that, in the present embodiment, referring to fig. 5a to 5k, fig. 7a to 7e, and fig. 8a to 8f, after forming the first insulating layer 101;
forming a diffraction interference layer 151 above a first insulating layer 101, coating a photoresist layer 100 on the upper surface of the diffraction interference layer 151, and performing a photolithography process on the photoresist layer 100 from a side of a substrate 10 away from the photoresist layer 100 (a back side of the substrate 10) by using a first metal layer 11 as a mask, wherein the photoresist layer 100 is patterned to form a photoresist pattern 110, a gate 112 corresponds to the photoresist pattern 110, and the photoresist pattern 110 is completely staggered from an overlapping portion 113;
forming a second metal layer 13 on the upper surface of the photoresist layer 100, wherein the second metal layer 13 covers the photoresist pattern 110 and the diffraction interference layer 151, etching the second metal layer 13 and removing the photoresist pattern 110, and the second metal layer 13 is patterned to form the data line 131, the source electrode 132 and the drain electrode 133.
A semiconductor layer 12 is formed on the upper surface of the second metal layer 13, the semiconductor layer 12 is etched, and the semiconductor layer 12 is patterned to form an active layer 121, wherein the active layer 121 corresponds to the gate electrode 112. In this embodiment, the semiconductor layer 12 does not need to be made of a material capable of reducing the diffraction range of light, and the semiconductor layer 12 may be made of a common semiconductor material, such as single crystal silicon or doped single crystal silicon.
A second insulating layer 102 is formed on the upper surface of the semiconductor layer 12, and the second insulating layer 102 covers the data line 131, the source electrode 132, the drain electrode 133, and the active layer 121. The second insulating layer 102 is etched such that the second insulating layer 102 has the contact hole 103 in a region corresponding to the drain electrode 133, and the upper surface of the drain electrode 133 is exposed through the contact hole 103.
A transparent conductive layer 14 is formed on the upper surface of the second insulating layer 102, the transparent conductive layer 14 is etched to form a pixel electrode 141, and the pixel electrode 141 covers the contact hole 103 and is electrically connected to the drain electrode 133.
A third insulating layer 106 is formed on the upper surface of the transparent conductive layer 14, and a common electrode 23 is formed on the upper surface of the third insulating layer 106, and the common electrode 23 is insulated and spaced apart from the pixel electrode 141 by the third insulating layer 106.
This embodiment also provides a display panel which is substantially the same as the display panel in the first embodiment (fig. 9), except that, in this embodiment, the counter substrate 20 is not provided with the common electrode 23.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate (10);
forming a first metal layer (11) above the substrate (10), etching the first metal layer (11), patterning the first metal layer (11) to form a scanning line (111) and a gate electrode (112), wherein the gate electrode (112) is electrically connected with the scanning line (111), the scanning line (111) has an overlapping part (113) which is overlapped with the data line (131) up and down, the width of the overlapping part (113) is less than or equal to twice of the photoresist shrinkage, and the width of the gate electrode (112) is greater than twice of the photoresist shrinkage;
forming a first insulating layer (101) covering the scan line (111) and the gate electrode (112) over the substrate (10);
forming a semiconductor layer (12) over the first insulating layer (101), etching the semiconductor layer (12), the semiconductor layer (12) being patterned to form an active layer (121);
coating a photoresist layer (100) above the first insulating layer (101), carrying out photoetching treatment on the photoresist layer (100) from the side, away from the photoresist layer (100), of the substrate (10) by using a mask of the first metal layer (11), wherein the photoresist layer (100) is patterned to form a photoresist pattern (110), the grid electrode (112) corresponds to the photoresist pattern (110), and the photoresist pattern (110) is completely staggered from the overlapped part (113);
forming a second metal layer (13) on the upper surface of the photoresist layer (100), etching the second metal layer (13) and removing the photoresist pattern (110), wherein the second metal layer (13) is patterned to form the data line (131), a source electrode (132) and a drain electrode (133), a projection of the data line (131) on the substrate (10) is overlapped with a projection of the overlapped part (113) on the substrate (10), the data line (131) is electrically connected with the source electrode (132), and the source electrode (132) and the drain electrode (133) are electrically connected through the active layer (121);
forming a pixel electrode (141) above the first insulating layer (101), the pixel electrode (141) being conductively connected to the drain electrode (133).
2. The method for manufacturing the array substrate according to claim 1, wherein the semiconductor layer (12) is made of a material capable of reducing a diffraction range of light, and the second metal layer (13) is directly disposed on an upper surface of the semiconductor layer (12).
3. The method of claim 1, wherein a diffraction interference layer (151) is formed above the first insulating layer (101), the diffraction interference layer (151) is capable of reducing a diffraction range of light, the second metal layer (13) is directly disposed on an upper surface of the diffraction interference layer (151), and the semiconductor layer (12) is directly disposed on an upper surface of the second metal layer (13).
4. The method for manufacturing the array substrate according to any one of claims 1 to 3, wherein the width of the scan line (111) is the same as the width of the overlapping portion (113), and the width of the scan line (111) is less than or equal to twice the photoresist recession amount; or the width of the scanning line (111) is larger than the width of the overlapping part (113).
5. The method for manufacturing the array substrate according to any one of claims 1 to 3, wherein the number of the overlapping portions (113) is plural and the overlapping portions are arranged in parallel and spaced from each other.
6. The method for manufacturing the array substrate according to any one of claims 1 to 3, wherein a common electrode (23) is formed above the first insulating layer (101), and the common electrode (23) and the pixel electrode (141) are insulated from each other.
7. An array substrate manufactured by the method according to any one of claims 1 to 6, the array substrate comprising:
a substrate (10);
the first metal layer (11) is arranged above the substrate (10), the first metal layer (11) comprises a scanning line (111) and a grid electrode (112), the grid electrode (112) is electrically connected with the scanning line (111), the scanning line (111) is provided with an overlapping part (113) which is overlapped with the data line (131) up and down, the width of the overlapping part (113) is less than or equal to twice of photoresist shrinkage, and the width of the grid electrode (112) is greater than twice of photoresist shrinkage;
a first insulating layer (101) disposed over the first metal layer (11), the first insulating layer (101) covering the scan lines (111) and the gate electrodes (112);
a semiconductor layer (12) disposed over the first insulating layer (101), the semiconductor layer (12) comprising an active layer (121);
a second metal layer (13) disposed over the first insulating layer (101), the second metal layer (13) including the data line (131), a source electrode (132), and a drain electrode (133), a projection of the data line (131) on the substrate (10) overlapping a projection of the overlap portion (113) on the substrate (10), the data line (131) being electrically connected to the source electrode (132), the source electrode (132) and the drain electrode (133) being electrically connected through the active layer (121);
a pixel electrode (141) disposed over the first insulating layer (101), the pixel electrode (141) being conductively connected to the drain electrode (133).
8. The array substrate according to claim 7, wherein the semiconductor layer (12) is made of a material capable of reducing the diffraction range of light, and the second metal layer (13) is directly disposed on the upper surface of the semiconductor layer (12); or the array substrate further comprises a diffraction interference layer (151) arranged above the first insulating layer (101), the diffraction interference layer (151) can reduce the diffraction range of light, the second metal layer (13) is directly arranged on the upper surface of the diffraction interference layer (151), and the semiconductor layer (12) is directly arranged on the upper surface of the second metal layer (13).
9. The array substrate according to claim 7, wherein the number of the overlapping portions (113) is plural and the overlapping portions are arranged in parallel and spaced from each other; or the array substrate further comprises a common electrode (23) arranged above the first insulating layer (101), and the common electrode (23) and the pixel electrode (141) are mutually insulated.
10. A display panel comprising an array substrate according to any one of claims 7 to 9 and a counter substrate (20) disposed opposite to the array substrate, and a liquid crystal layer (30) disposed between the array substrate and the counter substrate (20).
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