CN114242804A - HJT battery and preparation method thereof - Google Patents

HJT battery and preparation method thereof Download PDF

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Publication number
CN114242804A
CN114242804A CN202111399527.2A CN202111399527A CN114242804A CN 114242804 A CN114242804 A CN 114242804A CN 202111399527 A CN202111399527 A CN 202111399527A CN 114242804 A CN114242804 A CN 114242804A
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layer
amorphous silicon
thin film
film layer
type amorphous
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孟祥浩
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Suzhou Sierwei Nanotechnology Co ltd
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Suzhou Sierwei Nanotechnology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Abstract

The invention provides an HJT battery and a preparation method thereof, comprising the following steps: the solar cell comprises an N-type crystal silicon wafer, an intrinsic amorphous silicon layer, a P-type amorphous silicon thin film layer, an N-type amorphous silicon thin film layer, a TCO conducting layer, a silver nanowire layer and a gate electrode. Compared with the traditional HJT battery, the silver nanowire layer is additionally arranged between the TCO conducting layer and the grid electrode, the conductivity of the TCO conducting layer can be greatly improved by arranging the silver nanowire layer on the TCO conducting layer, so that the electron collection rate is improved, and further the low-temperature welding of the silver nanowire layer and the TCO conducting layer and the low-temperature welding of the silver nanowire layer and the grid electrode greatly improve the conductivity of the whole channel; meanwhile, the sheet resistance of the TCO conductive layer can be reduced to 30ohm by adding the silver nanowire layer, and light rays are not influenced (TT is more than 98%), namely, the generation efficiency of photoelectrons is hardly influenced.

Description

HJT battery and preparation method thereof
Technical Field
The invention relates to the technical field of solar cells, in particular to an HJT cell and a preparation method thereof.
Background
At present, the solar cell panel is widely applied to PERC and TOPCON technologies, the maximum photovoltaic conversion efficiency is only 24%, and the mass production efficiency is 21-22%; the theoretical efficiency of a new generation of HJT (heterojunction, HIT) process solar cell panel can reach 28-30%, and as a bright technical direction of the application prospect in the photovoltaic industry, the current mass production efficiency is only 24%, and the theoretical efficiency has a great difference. The main reason is that the generated electrons have low collection efficiency and large loss in the collection and transmission process. Compared with a PERC solar cell, the HJT solar cell has the greatest structural difference from a PERC layer (transparent conductive electrode, mainly ITO), but when the optical transmittance and the electrical conductivity of the conventional TCO layer are selected, a material with relatively poor electrical conductivity, mainly ITO, is selected for better optical transmittance, resulting in a relatively low electrical energy collection rate.
There is a need to improve this based on the shortcomings of current HJT solar cells.
Disclosure of Invention
In view of the above, the present invention provides an HJT battery and a method for manufacturing the same, so as to solve or at least partially solve the technical problems in the prior art.
In a first aspect, the present invention provides an HJT battery comprising:
an N-type crystal silicon wafer;
the intrinsic amorphous silicon layers are respectively positioned on the front side and the back side of the N-type crystal silicon wafer;
the P-type amorphous silicon thin film layer is positioned on the surface of the intrinsic amorphous silicon layer on the front side of the N-type crystalline silicon wafer;
the N-type amorphous silicon thin film layer is positioned on the surface of the intrinsic amorphous silicon layer on the back surface of the N-type crystalline silicon wafer;
the TCO conducting layer is respectively arranged on the surfaces of the P-type amorphous silicon thin film layer and the n-type amorphous silicon thin film layer;
the silver nanowire layer is respectively arranged on the TCO conductive layer corresponding to the P-type amorphous silicon thin film layer and the TCO conductive layer corresponding to the n-type amorphous silicon thin film layer;
and the gate electrode is arranged on the surface of the silver nanowire layer.
Preferably, in the HJT battery, the diameter of the silver nanowire in the silver nanowire layer is 10-50 nm.
Preferably, in the HJT cell, the gate electrode is made of any one of silver, copper, and silver-copper alloy.
In a second aspect, the present invention further provides a method for preparing the HJT cell, including the following steps:
providing an N-type crystal silicon wafer;
preparing intrinsic amorphous silicon layers on the front side and the back side of the N-type crystal silicon wafer respectively;
preparing a P-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the front side of the N-type crystalline silicon wafer;
preparing an N-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the back of the N-type crystalline silicon wafer;
preparing TCO conducting layers on the surfaces of the P-type amorphous silicon thin film layer and the n-type amorphous silicon thin film layer respectively;
preparing silver nanowire layers on the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer respectively;
and preparing a gate electrode on the surface of the silver nanowire layer.
Preferably, in the method for preparing an HJT cell, the method for preparing a silver nanowire layer specifically includes the following steps:
preparing silver nanowire silver paste;
and preparing the silver nano silver paste on the surfaces of the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer to obtain a silver nano wire layer.
The silver nanowire silver paste comprises the following raw materials in parts by weight: 25-75 parts of silver nanowires, 0.5-10 parts of resin, 1.5-22 parts of an auxiliary agent and 5-40 parts of a solvent.
Preferably, in the method for preparing the HJT cell, the resin includes a thermosetting resin or a UV-curable resin.
Preferably, in the preparation method of the HJT battery, the auxiliary agent includes at least one of a surface tension regulator, a rheology regulator, a coupling agent, and a dispersant.
Preferably, in the method for preparing an HJT cell, the solvent comprises water and/or an alcohol solvent; the alcohol solvent comprises at least one of n-butanol, terpineol and isopropanol.
Preferably, in the method for preparing an HJT battery, the surface tension modifier comprises at least one of a fluorocarbon surfactant and a fluorosilicone surfactant;
the rheology modifier comprises at least one of cellulose and PVP;
at least one of the coupling agents of vinyltrimethoxysilane and vinyltriethoxysilane;
the dispersant comprises at least one of polyacrylamide and fatty acid polyglycol ester.
Preferably, in the preparation method of the HJT battery, the silver nano silver paste is prepared on the surface of the TCO conductive layer corresponding to the P-type amorphous silicon thin film layer and the surface of the TCO conductive layer corresponding to the n-type amorphous silicon thin film layer by using a screen printing or pad printing method.
Compared with the prior art, the HJT battery and the preparation method thereof have the following beneficial effects:
(1) compared with the traditional HJT battery, the silver nanowire layer is additionally arranged between the TCO conducting layer and the grid electrode, the conductivity of the TCO conducting layer can be greatly improved by arranging the silver nanowire layer on the TCO conducting layer, so that the electron collection rate is improved, and further the low-temperature welding of the silver nanowire layer and the TCO conducting layer and the low-temperature welding of the silver nanowire layer and the grid electrode greatly improve the conductivity of the whole channel; meanwhile, the sheet resistance of the TCO conductive layer can be reduced to 30ohm by adding the silver nanowire layer, and light rays are not influenced (TT is more than 98%), namely, the generation efficiency of photoelectrons is hardly influenced.
Drawings
Fig. 1 is a schematic structural view of an HJT cell of the present application;
fig. 2 is a schematic structural view of a conventional HJT cell.
Detailed Description
In the following, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
An embodiment of the present application provides an HJT battery, as shown in fig. 1, including:
an N-type crystal silicon wafer 1;
intrinsic amorphous silicon layers 2 respectively positioned on the front and back sides of the N-type crystalline silicon wafer 1;
the P-type amorphous silicon thin film layer 3 is positioned on the surface of the intrinsic amorphous silicon layer 2 on the front surface of the N-type crystalline silicon wafer 1;
the N-type amorphous silicon thin film layer 4 is positioned on the surface of the intrinsic amorphous silicon layer 2 on the back surface of the N-type crystalline silicon wafer 1;
the TCO conducting layer 5 is respectively arranged on the surfaces of the P-type amorphous silicon thin film layer 3 and the n-type amorphous silicon thin film layer 4;
the silver nanowire layer 6 is respectively arranged on the surfaces of the TCO conducting layer 5 corresponding to the P-type amorphous silicon thin film layer 3 and the TCO conducting layer 5 corresponding to the n-type amorphous silicon thin film layer 4;
and a gate electrode 7 provided on the surface of the silver nanowire layer 6.
The HJT cell includes an N-type crystalline silicon wafer 1, an intrinsic amorphous silicon layer 2, a P-type amorphous silicon thin film layer 3, an N-type amorphous silicon thin film layer 4, a TCO conductive layer 5, a silver nanowire layer 6, and a gate electrode 7, where the TCO conductive layer is usually ITO; and its structure of traditional HJT battery is shown in fig. 2, the HJT battery of this application compares traditional HJT battery and has increased silver nanowire layer 6 between TCO conducting layer 5 and gate electrode 7, through set up silver nanowire layer 6 on the TCO conducting layer, can improve the electric conductivity of TCO conducting layer greatly, and then improve the electron collection rate, further silver nanowire layer 6 and 5 low temperature welding of TCO conducting layer, silver nanowire layer 6 and gate electrode 7 low temperature welding have improved the electric conductivity of whole route greatly.
In some embodiments, the diameter of the silver nanowires in the silver nanowire layer is 10-50 nm, and experiments show that when silver nanowires with a diameter of 10-50 nm are used, the sheet resistance of the TCO conductive layer 5 can be reduced to 30ohm, but light rays are not influenced (TT > 98%), i.e., the generation efficiency of photoelectrons is hardly influenced.
In some embodiments, the material of the gate electrode 7 is any of silver, copper, silver-copper alloy.
In some embodiments, the thickness of the intrinsic amorphous silicon layer 2 is 5-10 nm, the thickness of the P-type amorphous silicon thin film layer 3 and the thickness of the n-type amorphous silicon thin film layer 4 are both 7-10 nm, the thickness of the TCO conductive layer 5 is 70-80 nm, and the thickness of the silver nanowire layer 6 is 70-80 nm.
Based on the same inventive concept, the embodiment of the present application further provides a method for preparing the HJT battery, which includes the following steps:
s1, providing an N-type crystal silicon wafer;
s2, preparing intrinsic amorphous silicon layers on the front side and the back side of the N-type crystal silicon wafer respectively;
s3, preparing a P-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the front side of the N-type crystalline silicon wafer;
s4, preparing an N-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the back of the N-type crystalline silicon wafer;
s5, preparing TCO conducting layers on the surfaces of the P-type amorphous silicon thin film layer and the n-type amorphous silicon thin film layer respectively;
s6, preparing silver nanowire layers on the surfaces of the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer respectively;
and S7, preparing a gate electrode on the surface of the silver nanowire layer.
It should be noted that, in the above embodiments, the intrinsic amorphous silicon layer, the P-type amorphous silicon thin film layer, the n-type amorphous silicon thin film layer, the TCO conductive layer, and the gate electrode are all prepared by a conventional method. Specifically, an N-type crystal silicon wafer is subjected to texturing and cleaning treatment, and then an intrinsic amorphous silicon layer is prepared by utilizing a plasma enhanced chemical vapor deposition method; preparing a P-type amorphous silicon thin film layer and an n-type amorphous silicon thin film layer by using a plasma enhanced chemical vapor deposition method; depositing the TCO conducting layer by using a reactive ion deposition or sputtering method; the gate electrode was prepared by a screen printing method.
In some embodiments, the method of preparing a layer of silver nanowires specifically comprises the steps of:
preparing silver nanowire silver paste;
and preparing silver nano silver paste on the surfaces of the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer to obtain a silver nano wire layer.
The silver nanowire silver paste comprises the following raw materials in parts by weight: 25-75 parts of silver nanowires, 0.5-10 parts of resin, 1.5-22 parts of an auxiliary agent and 5-40 parts of a solvent.
In some embodiments, the resin comprises a thermosetting resin or a UV curable resin.
Specifically, the thermosetting resin includes epoxy resin, polyester resin, vinyl ester, bismaleimide, thermosetting polyimide, cyanate ester, melamine formaldehyde resin, furan resin, polybutadiene resin, silicone resin, and the like; UV curable resins include epoxy acrylates, urethane acrylates, polyester acrylates, polyether acrylates, amino acrylates, acrylates and other acrylates and the like.
In some embodiments, the adjuvant comprises at least one of a surface tension modifier, a rheology modifier, a coupling agent, a dispersing agent.
In some embodiments, the solvent comprises water and/or an alcohol solvent; the alcohol solvent comprises at least one of n-butanol, terpineol and isopropanol.
In some embodiments, the surface tension modifier comprises at least one of a fluorocarbon surfactant, a fluorosilicone surfactant;
the rheology modifier comprises at least one of cellulose and PVP;
at least one of coupling agent vinyl trimethoxy silane and vinyl triethoxy silane;
the dispersant comprises at least one of polyacrylamide and fatty acid polyglycol ester.
Specifically, the fluorocarbon surfactant can adopt Zonyl series products of Dupont and perfluorohexyl polyethenoxy ether sulfonate; the fluorine silicon surfactant adopts N-dimethylamino propyl-N-triethoxy silane and the like; as the cellulose, methyl cellulose, ethyl cellulose and the like can be used.
In some embodiments, silver nano silver paste is prepared on the surface of the TCO conductive layer corresponding to the P-type amorphous silicon thin film layer and the surface of the TCO conductive layer corresponding to the n-type amorphous silicon thin film layer by using a screen printing or pad printing method.
Specifically, the preparation of the silver nano silver paste on the surfaces of the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer by adopting a pad printing method specifically comprises the following steps: and coating the silver nanowire silver paste on the surface of the EVA or POE substrate, and then hot-melting and pasting the silver nanowire silver paste on the surface of the TCO conducting layer to obtain the silver nanowire layer.
It should be noted that, if the silver nanowire layer is prepared by a screen printing method, the silver nanowire layer is in a grid line shape, and the silver nanowire layer is a grid line silver nanowire.
The HJT cell and the method for making the same of the present application are further illustrated by the following specific examples.
Example 1
An embodiment of the present application provides an HJT battery, including:
an N-type crystal silicon wafer 1;
intrinsic amorphous silicon layers 2 respectively positioned on the front and back sides of the N-type crystalline silicon wafer 1;
the P-type amorphous silicon thin film layer 3 is positioned on the surface of the intrinsic amorphous silicon layer 2 on the front surface of the N-type crystalline silicon wafer 1;
the N-type amorphous silicon thin film layer 4 is positioned on the surface of the intrinsic amorphous silicon layer 2 on the back surface of the N-type crystalline silicon wafer 1;
the TCO conducting layer 5 is respectively arranged on the surfaces of the P-type amorphous silicon thin film layer 3 and the n-type amorphous silicon thin film layer 4;
the silver nanowire layer 6 is respectively arranged on the surfaces of the TCO conducting layer 5 corresponding to the P-type amorphous silicon thin film layer 3 and the TCO conducting layer 5 corresponding to the n-type amorphous silicon thin film layer 4;
a gate electrode 7 provided on the surface of the silver nanowire layer 6;
the gate electrode 7 is made of silver, the TCO conductive layer 5 is made of ITO, the thickness of the intrinsic amorphous silicon layer 2 is 10nm, the thicknesses of the P-type amorphous silicon thin film layer 3 and the n-type amorphous silicon thin film layer 4 are both 10nm, the thickness of the TCO conductive layer 5 is 80nm, and the thickness of the silver nanowire layer 6 is 75 nm.
The preparation method of the HJT battery comprises the following steps: performing texturing and cleaning treatment on the N-type crystal silicon wafer, and preparing an intrinsic amorphous silicon layer by using a plasma enhanced chemical vapor deposition method; preparing a P-type amorphous silicon thin film layer and an n-type amorphous silicon thin film layer by using a plasma enhanced chemical vapor deposition method; depositing a TCO conductive layer by using a sputtering method;
preparing silver nanowire silver paste, wherein the silver nanowire silver paste comprises the following raw materials in parts by weight: 50 parts of silver nanowires with the diameter of 35nm, 2 parts of resin, 10 parts of auxiliary agent and 35 parts of solvent, wherein the resin adopts acrylic ester, the auxiliary agent comprises a mixture of a surface tension regulator, a rheology regulator and a dispersing agent, the surface tension regulator adopts fluorocarbon surfactant, the rheology regulator adopts methyl cellulose, the dispersing agent adopts fatty acid polyglycol ester, and the mass ratio of the surface tension regulator to the rheology regulator to the dispersing agent is 1:2: 1;
preparing the silver nanowire silver paste on a TCO conductive layer by adopting a screen printing method to form a silver nanowire layer;
and preparing a silver gate electrode on the surface of the silver nanowire layer by using a screen printing method.
Comparative example 1
This comparative example provides an HJT cell having the same structure as example 1 except that the silver nanowire layer 6 is not included.
The TCO conductive layer in comparative example 1 was tested to have a sheet resistance of 102ohm, and the conductive layer in example 1 where the TCO conductive layer and the silver nanowire layer were integrally formed was tested to have a sheet resistance of 30 ohm. Meanwhile, the light transmittance of the HJT cell in example 1 is almost unchanged from that of the HJT cell in comparative example 1, and the transmittance is greater than 98%.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. An HJT cell, comprising:
an N-type crystal silicon wafer;
the intrinsic amorphous silicon layers are respectively positioned on the front side and the back side of the N-type crystal silicon wafer;
the P-type amorphous silicon thin film layer is positioned on the surface of the intrinsic amorphous silicon layer on the front side of the N-type crystalline silicon wafer;
the N-type amorphous silicon thin film layer is positioned on the surface of the intrinsic amorphous silicon layer on the back surface of the N-type crystalline silicon wafer;
the TCO conducting layer is respectively arranged on the surfaces of the P-type amorphous silicon thin film layer and the n-type amorphous silicon thin film layer;
the silver nanowire layer is respectively arranged on the TCO conductive layer corresponding to the P-type amorphous silicon thin film layer and the TCO conductive layer corresponding to the n-type amorphous silicon thin film layer;
and the gate electrode is arranged on the surface of the silver nanowire layer.
2. The HJT cell according to claim 1, wherein the diameter of the silver nanowires in the silver nanowire layer is between 10nm and 50 nm.
3. The HJT cell of claim 1, wherein the gate electrode is made of any of silver, copper, and silver-copper alloy.
4. A method for preparing HJT cell according to any of claims 1 to 3, comprising the steps of:
providing an N-type crystal silicon wafer;
preparing intrinsic amorphous silicon layers on the front side and the back side of the N-type crystal silicon wafer respectively;
preparing a P-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the front side of the N-type crystalline silicon wafer;
preparing an N-type amorphous silicon film layer on the surface of the intrinsic amorphous silicon layer on the back of the N-type crystalline silicon wafer;
preparing TCO conducting layers on the surfaces of the P-type amorphous silicon thin film layer and the n-type amorphous silicon thin film layer respectively;
preparing silver nanowire layers on the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer respectively;
and preparing a gate electrode on the surface of the silver nanowire layer.
5. The method of claim 4, wherein the method of forming the silver nanowire layer comprises the steps of:
preparing silver nanowire silver paste;
and preparing the silver nano silver paste on the surfaces of the TCO conducting layer corresponding to the P-type amorphous silicon thin film layer and the TCO conducting layer corresponding to the n-type amorphous silicon thin film layer to obtain a silver nano wire layer.
The silver nanowire silver paste comprises the following raw materials in parts by weight: 25-75 parts of silver nanowires, 0.5-10 parts of resin, 1.5-22 parts of an auxiliary agent and 5-40 parts of a solvent.
6. The method of claim 5, wherein the resin comprises a thermosetting resin or a UV curable resin.
7. The method of claim 5, wherein the additive comprises at least one of a surface tension modifier, a rheology modifier, a coupling agent, and a dispersant.
8. The method of claim 5, wherein the solvent comprises water and/or an alcohol solvent; the alcohol solvent comprises at least one of n-butanol, terpineol and isopropanol.
9. The method of claim 7, wherein the surface tension modifier comprises at least one of a fluorocarbon surfactant and a fluorosilicone surfactant;
the rheology modifier comprises at least one of cellulose and PVP;
at least one of the coupling agents of vinyltrimethoxysilane and vinyltriethoxysilane;
the dispersant comprises at least one of polyacrylamide and fatty acid polyglycol ester.
10. The method for preparing an HJT cell as claimed in claim 4, wherein the silver nano silver paste is prepared on the TCO conductive layer corresponding to the P-type amorphous silicon thin film layer and the TCO conductive layer corresponding to the n-type amorphous silicon thin film layer by a screen printing or pad printing method.
CN202111399527.2A 2021-11-23 2021-11-23 HJT battery and preparation method thereof Pending CN114242804A (en)

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CN108091719A (en) * 2017-11-15 2018-05-29 君泰创新（北京）科技有限公司 Heterojunction solar battery and preparation method thereof
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CN113013294A (en) * 2021-02-26 2021-06-22 江苏润阳悦达光伏科技有限公司 HJT heterojunction battery based on repeated printing and preparation method thereof

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