CN114242011B - Driving system and driving method for display device - Google Patents
Driving system and driving method for display device Download PDFInfo
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- CN114242011B CN114242011B CN202111537695.3A CN202111537695A CN114242011B CN 114242011 B CN114242011 B CN 114242011B CN 202111537695 A CN202111537695 A CN 202111537695A CN 114242011 B CN114242011 B CN 114242011B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The driving system of the display device and the driving method of the display device provided by the embodiment of the application comprise a display panel, a driving control board and a programmable logic controller, wherein the driving control board is provided with a field programmable gate array chip, a master time sequence control chip and a slave time sequence control chip. Firstly, the display of partial areas is respectively controlled by different time sequence control chips, so that the display with high resolution and high refresh rate can be realized; secondly, a field programmable gate array chip is added in the embodiment of the application, so that the synchronous signals generated by the master timing control chip can be copied into a plurality of copies and transmitted to the slave timing control chip, and thus, when the master timing control chip and the slave timing control chip drive the display panel to display, synchronous driving can be realized, the phenomenon of abnormal pictures is avoided, and the display quality of the display panel is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a driving system and a driving method for a display device.
Background
Currently, liquid Crystal Display (LCD) devices have been widely used in various fields, such as televisions, tablet computers, or notebook computers. Then, due to the inherent characteristics of the liquid crystal cell, the LCD panel generally has a low response speed and a low resolution, and there is substantially no LCD display panel above 8k120hz on the market.
Among them, in order to improve the response speed and resolution of the LCD display panel, the related art generally employs an overdrive method to drive the LCD panel. However, when the display panel is driven by the overdrive method, the driving signal synchronization performance between different timing control chips is poor, so that the phenomenon of drawing difference occurs.
Therefore, how to avoid the phenomenon of drawing different images on the basis of improving the resolution of the LCD panel is a difficult problem for the existing panel manufacturers to try to overcome.
Disclosure of Invention
An object of the embodiments of the present application is to provide a driving system and a driving method for a display device, which can solve the technical problem in the prior art that a picture difference phenomenon is easily generated when an overdrive method is used to improve the resolution of an LCD panel.
An embodiment of the present application provides a driving system of a display device, including:
the display device comprises a display panel, a drive control panel and a programmable logic controller, wherein the drive control panel is provided with a field programmable gate array chip and a time sequence control chip, and the time sequence control chip comprises a master time sequence control chip and a plurality of slave time sequence control chips; wherein the content of the first and second substances,
the programmable logic controller is used for processing initial image data so as to divide the initial image data into a plurality of subarea image data and transmitting the plurality of subarea image data to the master timing control chip and the plurality of slave timing control chips; the main time sequence control chip is used for receiving the subarea image data, generating a synchronous signal according to the subarea image data and transmitting the synchronous signal to the field programmable gate array chip; the field programmable gate array chip is used for receiving the synchronous signal and transmitting the synchronous signal to the slave timing control chip; the slave time sequence control chip is used for receiving the synchronous signal and the subarea image data; the master time sequence control chip and the slave time sequence control chip are both used for transmitting the subarea image data to the display panel according to the synchronous signals so as to synchronously drive the display panel to display.
In the driving system of the display device according to the embodiment of the present application, the timing control chips controlling the sub display regions that are adjacently disposed may receive edge video data between the sub display regions that are adjacently disposed.
In the driving system of the display device according to the embodiment of the present application, the programmable logic controller includes a processing module and a first transmission module; the processing module is used for processing the initial image data to divide the initial image data into a plurality of subarea image data; the first transmission module is used for transmitting the plurality of subarea image data to the master timing control chip and the plurality of slave timing control chips.
In the driving system of the display device according to the embodiment of the present application, the main timing control chip includes a first receiving module, a generating module, a second transmitting module, and a first driving module; the first receiving module is used for receiving the partitioned image data; the generating module generates a synchronous signal according to the subarea image data; the second transmission module is used for transmitting the synchronous signal to a field programmable gate array chip; the first driving module is used for transmitting the subarea image data to the display panel by the synchronous signal so as to synchronously drive the display panel to display.
In the driving system of the display device according to the embodiment of the present application, the field programmable gate array chip includes a second receiving module and a third transmitting module; the second receiving module is used for receiving the synchronous signal; the third transmission module is used for transmitting the synchronous signal to the slave timing control chip.
In the driving system of the display device according to the embodiment of the present application, the slave timing control chip includes a third receiving module and a second driving module; the third receiving module is used for receiving the synchronous signal and the subarea image data; the second driving module is used for transmitting the subarea image data to the display panel according to the synchronous signal so as to synchronously drive the display panel to display.
In the driving system of a display device according to an embodiment of the present application, the slave timing control chip is further configured to transmit status information and synchronization information of the slave timing control chip to the field programmable gate array chip, the programmable gate array chip is further configured to summarize the status information and synchronization information of the slave timing control chip, and transmit the status information and synchronization information of the slave timing control chip to the master timing control chip, the master timing control chip is configured to compare and calculate the status information and synchronization information of the slave timing control chip and the status information and synchronization information of the master timing control chip, so as to determine whether the slave timing control chip is defective, and if a certain slave timing control chip is defective, the slave timing control chip is controlled to reset correspondingly.
In the driving system of the display device according to the embodiment of the present application, the slave timing control chip further includes a fourth transmission module, and the fourth transmission module is configured to transmit the state information and the synchronization information of the slave timing control chip to the field programmable gate array chip; the programmable gate array chip further comprises a summarizing module and a fifth transmission module, the summarizing module is used for summarizing the state information and the synchronous information of the slave timing control chip, and the fifth transmission module is used for transmitting the state information and the synchronous information of the slave timing control chip to the master timing control chip; the master timing control chip further comprises a comparison module and a reset module, the comparison module is used for comparing and calculating the state information and the synchronous information of the slave timing control chip and the state information and the synchronous information of the master timing control chip so as to judge whether the slave timing control chip is bad, and the reset module is used for controlling the corresponding slave timing control chip to reset if the slave timing control chip is bad.
An embodiment of the present application further provides a driving method of a display device, where the driving method includes:
providing initial image data to a programmable logic controller;
the programmable logic controller processing initial image data to segment the initial image data into a plurality of partitioned image data;
the programmable logic controller transmits the plurality of subarea image data to a master timing control chip and a plurality of slave timing control chips;
the master time sequence control chip generates a synchronous signal according to the partitioned image data and transmits the synchronous signal to a field programmable gate array chip;
the field programmable gate array chip transmits the synchronous signal to the slave timing control chip;
and the master time sequence control chip and the slave time sequence control chip transmit the subarea image data to a display panel according to the synchronous signals so as to synchronously drive the display panel to display.
In the driving system of the display device and the driving method of the display device provided in the embodiment of the present application, the driving system includes a display panel, a driving control board and a programmable logic controller, and the driving control board is provided with a field programmable gate array chip, a master timing control chip and a slave timing control chip. The master timing control chip can generate a synchronous signal after receiving the partitioned image data, and the synchronous signal is copied to multiple copies through the field programmable gate array chip and transmitted to the slave timing control chip. Then, the master timing control chip and the slave timing control chip can synchronously drive the display panel to display according to the synchronous signals and the subarea image data. Firstly, the display of partial areas is respectively controlled by different time sequence control chips, so that the display with high resolution and high refresh rate can be realized; secondly, a field programmable gate array chip is added in the embodiment of the application, so that the synchronous signals generated by the master timing control chip can be copied into a plurality of copies and transmitted to the slave timing control chip, and thus, when the master timing control chip and the slave timing control chip drive the display panel to display, synchronous driving can be realized, the phenomenon of abnormal pictures is avoided, and the display quality of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first structural schematic diagram of a driving system of a display device according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a programmable logic controller according to an embodiment of the present application.
Fig. 3 is a first structural schematic diagram of a main timing control chip according to an embodiment of the present disclosure.
Fig. 4 is a first structural schematic diagram of a field programmable gate array chip according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a first structure of a slave timing control chip according to an embodiment of the present disclosure.
Fig. 6 is a second structural schematic diagram of a slave timing control chip according to an embodiment of the present disclosure.
Fig. 7 is a second schematic structural diagram of a field programmable gate array chip according to an embodiment of the present application.
Fig. 8 is a second structural diagram of a main timing control chip according to an embodiment of the present application.
Fig. 9 is a flowchart illustrating a driving method of a display device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "length," "width," "thickness," "upper," "lower," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and simplicity in description, but do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second", etc. may explicitly or implicitly include one or more of the described features and are therefore not to be construed as limiting the application.
The embodiment of the application provides a driving system of a display device and a driving method of the display device. The following are detailed descriptions. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a driving system of a display device according to an embodiment of the present disclosure. As shown in fig. 1, a driving system 10 of a display device provided in an embodiment of the present application includes a display panel 101, a driving control board 102, and a programmable logic controller 103. The driving control board 102 is provided with a field programmable gate array chip 1021 and a timing control chip 1022, and the timing control chip 1022 includes a master timing control chip 1023 and a plurality of slave timing control chips 1024.
The programmable logic controller 103 is configured to process the initial image data to divide the initial image data into a plurality of partition image data, and transmit the plurality of partition image data to the master timing control chip 1023 and the plurality of slave timing control chips 1024.
It should be noted that the programmable logic controller 103 is mainly configured to convert the initial image data with low resolution and low refresh rate into the image data with high resolution and high refresh rate, and divide the image data into a plurality of sets of partitioned image data, each set of partitioned image data corresponds to a different display area, where the number of sets of partitioned image data matches the number of the timing control chips 1022. For example, if the initial image data received by the programmable logic controller 103 is 10bit data of 4k × 2k, the programmable logic controller 103 converts the 10bit data of 4k × 2k into 10bit data of 8k × 4k, divides the 10bit data of 8k × 4k into four pieces of partitioned image data, and transmits the four pieces of partitioned image data to the corresponding timing control chip 1022. When the plc 103 transmits the tile image data to the timing controller 1022, the master timing controller 1023 also serves as a timing controller and receives a piece of tile image data.
The display area of the display panel 101 includes a plurality of sub-display areas arranged adjacently, and the timing control chip 1022 controls one corresponding sub-display area respectively and generates a timing signal for driving the display panel 101 to display to the sub-display area controlled by the timing control chip 1022.
It should be noted that, by using different timing control chips 1022 to respectively control the display of different sub-display regions, the display with high resolution and high refresh rate can be realized.
The timing control chips 1022 controlling the sub-display regions arranged adjacently receive the edge video data between the sub-display regions arranged adjacently. It should be noted that, by enabling the timing control chips 1022 controlling the adjacently disposed sub-display areas to receive the edge video data between the adjacently disposed sub-display areas, the display area of the display panel can be smoother, and the split screen phenomenon can be avoided. In addition, in the embodiment of the present application, the programmable logic controller 103 directly transmits the edge video data to the corresponding sequential control chip 1022, so that data transmission between adjacent sequential control chips 1022 is not required.
The master timing control chip 1023 is configured to receive the tile image data, generate a synchronization signal according to the tile image data, and transmit the synchronization signal to the fpga chip 1021. The field programmable gate array chip 1021 is used for receiving the synchronization signal and transmitting the synchronization signal to the slave timing control chip 1024. The slave timing control chip 1024 is used for receiving a synchronization signal and partition image data. The master timing control chip 1023 and the slave timing control chip 1024 are also used for transmitting the partitioned image data to the display panel according to the synchronization signal, so as to synchronously drive the display panel to display.
It should be noted that, in the embodiment of the present application, the field programmable gate array chip 1021 copies the synchronization signal generated by the master timing control chip 1023 into multiple copies, and transmits the copies to the slave timing control chip 1024, so that when the master timing control chip 1023 and the slave timing control chip 1024 drive the display panel to display, synchronous driving can be implemented, thereby avoiding the occurrence of a drawing exception phenomenon, and improving the display quality of the display panel.
Referring to fig. 2, fig. 3, fig. 4, and fig. 5, fig. 2 is a schematic structural diagram of a programmable logic controller according to an embodiment of the present application, fig. 3 is a schematic structural diagram of a master timing control chip according to the embodiment of the present application, fig. 4 is a schematic structural diagram of a field programmable gate array chip according to the embodiment of the present application, and fig. 5 is a schematic structural diagram of a slave timing control chip according to the embodiment of the present application. As shown in fig. 2, 3, 4, and 5, the programmable logic controller 103 includes a processing module 103a and a first transmission module 103b. The master timing control chip 1023 includes a first receiving module 1023a, a generating module 1023b, a second transmitting module 1023c and a first driving module 1023d. The fpga chip 1021 includes a second receiving module 1021a and a third transmitting module 1021b. The slave timing control chip 1024 includes a third receiving module 1024a and a second driving module 1024b.
The processing module 103a is configured to process the initial image data to divide the initial image data into a plurality of divisional image data. The first transmission module 103b is used for transmitting the plurality of partition image data to the master timing control chip 1023 and the plurality of slave timing control chips 1024.
The first receiving module 1023a is used for receiving the partition image data. The generating module 1024b generates a synchronization signal according to the partitioned image data. The second transmission module 1024c is used to transmit the synchronization signal to the field programmable gate array chip 1021. The first driving module 1024d is configured to transmit the divisional image data to the display panel 101 according to the synchronization signal, so as to synchronously drive the display panel 101 to display.
The second receiving module 1021a is configured to receive a synchronization signal. The third transmitting module 1021b is used for transmitting the synchronization signal to the slave timing control chip 1024.
The third receiving module 1024a is configured to receive the synchronization signal and the partition image data. The second driving module 1024b is configured to transmit the divisional image data to the display panel 101 according to the synchronization signal, so as to synchronously drive the display panel 101 for displaying.
Referring to fig. 6, fig. 7 and fig. 8, fig. 6 is a second structural schematic diagram of a slave timing control chip according to an embodiment of the present application, fig. 7 is a second structural schematic diagram of a programmable gate array chip according to the embodiment of the present application, and fig. 8 is a second structural schematic diagram of a master timing control chip according to the embodiment of the present application. As shown in fig. 6, 7 and 8, the slave timing control chip 1024 further includes a fourth transmission module 1024c. The programmable gate array chip 1021 further includes a summary module 1021c and a fifth transmission module 1021d. The master timing control chip 1023 further comprises a comparison module 1023e and a reset module 1023f.
The fourth transmission module 1024c is configured to transmit the state information and the synchronization information of the slave timing control chip 1024 to the fpga 1021.
The state information of the slave timing control chip 1024 includes information such as current and voltage flowing through the slave timing control chip 1024, and the synchronization information of the slave timing control chip 1024 includes information such as clock information and length information. The status information and the synchronization information of the slave timing controller 1024 are obtained mainly for detecting whether the slave timing controller 1024 fails to output the driving signal normally and receives no correct synchronization signal.
The summarizing module 1021c is configured to summarize the status information and the synchronization information of the slave timing control chip 1024. The fifth transmitting module 1021d is used for transmitting the status information and the synchronization information of the slave timing control chip 1024 to the master timing control chip 1023.
The comparing module 1023e is used for comparing and calculating the state information and the synchronization information of the slave timing control chip 1024 and the state information and the synchronization information of the master timing control chip 1023 to judge whether the slave timing control chip 1024 is bad. The reset module 1023f is used for controlling the corresponding slave timing control chip 1024 to reset if a certain slave timing control chip 1024 is defective.
It should be noted that the reason for controlling the corresponding slave timing control chip 1024 to reset is to provide new information to the slave timing control chip 1024, so as to avoid the slave timing control chip 1024 from generating a bad phenomenon.
In the driving system of the display device provided in the embodiment of the application, the driving system includes a display panel, a driving control board and a programmable logic controller, and the driving control board is provided with a field programmable gate array chip, a master timing control chip and a slave timing control chip. The master timing control chip can generate a synchronous signal after receiving the partitioned image data, and the synchronous signal is copied to multiple copies through the field programmable gate array chip and transmitted to the slave timing control chip. Then, the master time sequence control chip and the slave time sequence control chip can synchronously drive the display panel to display according to the synchronous signals and the partitioned image data. Firstly, the display of partial areas is respectively controlled by different time sequence control chips, so that the display with high resolution and high refresh rate can be realized; secondly, a field programmable gate array chip is added in the embodiment of the application, so that the synchronous signals generated by the master timing control chip can be copied into a plurality of copies and transmitted to the slave timing control chip, and thus, when the master timing control chip and the slave timing control chip drive the display panel to display, synchronous driving can be realized, the phenomenon of abnormal pictures is avoided, and the display quality of the display panel is improved.
Referring to fig. 9, fig. 9 is a schematic flowchart illustrating a driving method of a display device according to an embodiment of the present disclosure, and as shown in fig. 9, the driving method of the display device according to the embodiment of the present disclosure includes the following steps:
At step 202, the programmable logic controller processes the initial image data to segment the initial image data into a plurality of segmented image data.
And step 203, the programmable logic controller transmits the plurality of subarea image data to the master timing control chip and the plurality of slave timing control chips.
And step 204, the main time sequence control chip generates a synchronous signal according to the partitioned image data and transmits the synchronous signal to the field programmable gate array chip.
And step 205, the field programmable gate array chip transmits the synchronous signal to the slave timing control chip.
The driving system of the display device can refer to the description of the driving system of the display device, which is not described herein again.
In the driving method of the display device provided in the embodiment of the present application, first, the display of a partial region is respectively controlled by different time sequence control chips, so that the display with high resolution and high refresh rate can be realized; secondly, a field programmable gate array chip is added in the embodiment of the application, so that the synchronous signals generated by the master timing control chip can be copied into a plurality of copies and transmitted to the slave timing control chip, and thus, when the master timing control chip and the slave timing control chip drive the display panel to display, synchronous driving can be realized, the phenomenon of abnormal pictures is avoided, and the display quality of the display panel is improved.
The foregoing describes in detail a driving system of a display device and a driving method of a display device provided in an embodiment of the present application, and a specific example is applied to illustrate the principle and the implementation of the present application, and the above description of the embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (8)
1. A driving system of a display device, comprising: the display device comprises a display panel, a drive control panel and a programmable logic controller;
the drive control board is provided with a field programmable gate array chip and a time sequence control chip, and the time sequence control chip comprises a master time sequence control chip and a plurality of slave time sequence control chips; wherein the content of the first and second substances,
the programmable logic controller is used for processing initial image data so as to divide the initial image data into a plurality of subarea image data and transmitting the plurality of subarea image data to the master timing control chip and the plurality of slave timing control chips;
the main time sequence control chip is used for receiving the subarea image data, generating a synchronous signal according to the subarea image data and transmitting the synchronous signal to the field programmable gate array chip; the master time sequence control chip comprises a first receiving module, a generating module and a second transmitting module; the first receiving module is used for receiving the subarea image data, the generating module generates the synchronous signal according to the subarea image data, and the second transmitting module is used for transmitting the synchronous signal to the field programmable gate array chip;
the field programmable gate array chip is used for receiving the synchronous signal and transmitting the synchronous signal to the slave timing control chip; the field programmable gate array chip comprises a second receiving module and a third transmitting module, wherein the second receiving module is used for receiving the synchronous signal, and the third transmitting module is used for transmitting the synchronous signal to the slave timing control chip;
the slave timing control chip is used for receiving the synchronous signal and the subarea image data; the slave timing control chip comprises a third receiving module, wherein the third receiving module is used for receiving the synchronous signal; the slave timing control chip is also used for transmitting the state information and the synchronization information of the slave timing control chip to the field programmable gate array chip;
the field programmable gate array chip is also used for summarizing the state information and the synchronous information of the slave timing control chip and transmitting the state information and the synchronous information of the slave timing control chip to the master timing control chip;
the master timing control chip is also used for comparing and calculating the state information and the synchronous information of the slave timing control chips with the state information and the synchronous information of the master timing control chip so as to judge whether the slave timing control chips are poor or not, and if a certain slave timing control chip is poor, the corresponding slave timing control chip is controlled to reset;
the master time sequence control chip and the slave time sequence control chip are both used for transmitting the subarea image data to the display panel according to the synchronous signals so as to synchronously drive the display panel to display.
2. The driving system of the display device according to claim 1, wherein the display area of the display panel comprises a plurality of sub-display areas arranged adjacently, and the timing control chip controls one of the sub-display areas respectively and generates the timing signal for driving the display panel to display on the sub-display area controlled by the timing control chip.
3. The driving system of a display device according to claim 2, wherein the timing control chips controlling the adjacently disposed sub-display regions each receive edge video data between the adjacently disposed sub-display regions.
4. The driving system of a display device according to claim 1, wherein the programmable logic controller includes a processing module and a first transmission module; the processing module is used for processing the initial image data to divide the initial image data into a plurality of subarea image data; the first transmission module is used for transmitting the plurality of subarea image data to the master timing control chip and the plurality of slave timing control chips.
5. The driving system of the display device according to claim 1, wherein the main timing control chip further comprises a first driving module, and the first driving module is configured to transmit the divisional image data to the display panel according to the synchronization signal so as to synchronously drive the display panel to display.
6. The driving system of a display device according to claim 1, wherein the slave timing control chip further comprises a second driving module; the third receiving module is also used for the subarea image data; the second driving module is used for transmitting the partitioned image data to the display panel according to the synchronous signal so as to synchronously drive the display panel to display.
7. The driving system of the display device according to claim 1, wherein the slave timing control chip further comprises a fourth transmission module for transmitting the status information and the synchronization information of the slave timing control chip to the field programmable gate array chip; the field programmable gate array chip further comprises a summarizing module and a fifth transmission module, wherein the summarizing module is used for summarizing the state information and the synchronous information of the slave timing control chip, and the fifth transmission module is used for transmitting the state information and the synchronous information of the slave timing control chip to the master timing control chip; the master timing control chip further comprises a comparison module and a reset module, the comparison module is used for comparing and calculating the state information and the synchronous information of the slave timing control chip and the state information and the synchronous information of the master timing control chip so as to judge whether the slave timing control chip is bad, and the reset module is used for controlling the corresponding slave timing control chip to reset if the slave timing control chip is bad.
8. A driving method of a driving system of a display device according to any one of claims 1 to 7, wherein the driving method comprises:
providing initial image data to a programmable logic controller;
the programmable logic controller processing initial image data to segment the initial image data into a plurality of partitioned image data;
the programmable logic controller transmits the plurality of subarea image data to a master time sequence control chip and a plurality of slave time sequence control chips;
the main time sequence control chip generates a synchronous signal according to the partitioned image data and transmits the synchronous signal to a field programmable gate array chip;
the field programmable gate array chip transmits the synchronous signal to the slave timing control chip;
the slave timing control chip transmits the state information and the synchronous information of the slave timing control chip to the field programmable array chip; the field programmable array chip collects the state information of the slave timing control chip and the synchronous information of the slave timing control chip and transmits the collected state information and the synchronous information to the master timing control chip;
the master timing control chip compares the state information and the synchronous information of the slave timing control chip with the state information and the synchronous information of the master timing control chip to judge whether the slave timing control chip is poor, and if some slave timing control chip is poor, the corresponding slave timing control chip is controlled to reset;
and the master time sequence control chip and the slave time sequence control chip transmit the subarea image data to a display panel according to the synchronous signals so as to synchronously drive the display panel to display.
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