CN114217752A - Control method and device for multi-screen synchronous display, electronic equipment and storage medium - Google Patents
Control method and device for multi-screen synchronous display, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN114217752A CN114217752A CN202111231668.3A CN202111231668A CN114217752A CN 114217752 A CN114217752 A CN 114217752A CN 202111231668 A CN202111231668 A CN 202111231668A CN 114217752 A CN114217752 A CN 114217752A
- Authority
- CN
- China
- Prior art keywords
- display
- delay
- target screen
- parameter
- screen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004590 computer program Methods 0.000 claims description 6
- 230000001172 regenerating effect Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 23
- 230000003111 delayed effect Effects 0.000 description 13
- 238000012545 processing Methods 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The embodiment of the invention discloses a control method and device for multi-screen synchronous display, electronic equipment and a storage medium. The control method for multi-screen synchronous display comprises the following steps: determining a delay parameter of a target screen according to the set position of the target screen; resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board; and determining the time for resetting the counter display sending module according to the delay parameters so as to synchronously display all screens. The embodiment of the invention realizes the reset synchronization of the display sending modules of all the screen counters through the display sending frame synchronization signals sent by the main control board, and simultaneously determines the delay parameters through the screen positions to solve the problem of asynchronous display of different lines of display screens during multi-screen display, thereby realizing the picture synchronization effect of a television wall and having strong applicability.
Description
Technical Field
The embodiment of the invention relates to the technical field of screen display, in particular to a control method and device for multi-screen synchronous display, electronic equipment and a storage medium.
Background
Along with the popularization vigorously of smart cities, because reasons such as the big, with high costs of single big screen production degree of difficulty, generally use the mode of many screens concatenation to realize the big screen display and show for control type is pieced together accuse equipment and is more and more popularized. For example, a splicing control device is used in a monitoring field to splice the display pictures of a plurality of display screens together, so that a television wall formed by the plurality of display screens jointly displays the same picture.
To piecing together accuse equipment, often be provided with a plurality of output integrated circuit boards, and a plurality of picture output interfaces can be established to a plurality of output integrated circuit boards, and every picture output interface is connected with a display screen, realizes piecing together the simultaneous control of accuse equipment to a plurality of display screens. Under the condition that a plurality of display screens are spliced into a television wall with multiple rows and multiple columns, one image input source is dragged into the whole television wall, the image refreshing starting time of each display screen is the same, but for the whole television wall, the scanning of the whole image is sequentially performed from top to bottom, so that the display screens in different rows can generate the phenomenon of picture asynchronism when displaying the image, and the phenomenon of asynchronism is more serious the larger the number of rows is, thereby influencing the whole display effect of the television wall.
Disclosure of Invention
The embodiment of the invention provides a multi-screen synchronous display control method, a multi-screen synchronous display control device, electronic equipment and a storage medium, solves the problem of asynchronous display of pictures of different display screens during multi-screen display, realizes the picture synchronization effect of a television wall, and has strong applicability.
In a first aspect, an embodiment of the present invention provides a method for controlling multi-screen synchronous display, where all screens are controlled and displayed by a same main control board, and the method includes:
determining a delay parameter of a target screen according to the set position of the target screen;
resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and determining the time for resetting the counter display sending module according to the delay parameters so as to synchronously display all screens.
In a second aspect, an embodiment of the present invention further provides a control device for multi-screen synchronous display, where all screens are controlled and displayed by a same main control board, and the control device includes:
the delay parameter determining module is used for determining the delay parameter of the target screen according to the set position of the target screen;
the display sending reset module is used for resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and the display sending and decoding resetting module is used for determining the time for decoding and resetting the counter display sending module according to the delay parameter so as to synchronously display all screens.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement the control method for multi-screen synchronous display according to any embodiment of the invention.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a method for controlling multi-screen synchronous display according to any embodiment of the present invention.
The method comprises the steps of determining a delay parameter of a target screen according to a set position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronization signal sent by a main control board; and determining the time for resetting the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of the display sending modules of all the screen counters is realized through the display sending frame synchronization signals sent by the main control board, and meanwhile, the problem of asynchronous display of different lines of display screens during multi-screen display is solved through determining delay parameters by screen positions, so that the picture synchronization effect of a television wall is realized, and the applicability is strong.
Drawings
FIG. 1 is a flowchart illustrating a method for controlling multi-screen simultaneous display according to a first embodiment of the present invention;
FIG. 2 is a schematic view of a video wall constructed with 3 rows and 3 columns of display screens;
FIG. 3 is a flowchart illustrating a control method for multi-screen simultaneous display according to a second embodiment of the present invention;
FIG. 4 is a flowchart of a control method of a multi-screen simultaneous display in a synchronous mode;
fig. 5 is a flowchart of a control method for multi-screen synchronous display when a clock of a main control board and a clock of an output service board associated with each screen in a synchronous delay mode are homologous clocks;
fig. 6 is a flowchart of a control method for multi-screen synchronous display when a clock of a main control board and a clock of an output service board associated with each screen in a synchronous delay mode are non-homologous clocks;
FIG. 7 is a schematic structural diagram of a control device for multi-screen simultaneous display according to a third embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a multi-screen synchronous display control method according to a first embodiment of the present invention, where this embodiment is applicable to a case where synchronous display control is performed on multiple display screens controlled by a mosaic device, and all the screens are controlled and displayed by a same main control board. The method can be executed by a control device for multi-screen synchronous display, which can be implemented in software and/or hardware and can be configured in an electronic device, for example, the electronic device can be a device with communication and computing capabilities, such as a backend server. As shown in fig. 1, the method specifically includes:
The target screen is any one of a plurality of screens forming a television wall, and the setting position of the target screen refers to the position of the target screen on the television wall, for example, because the number of lines of the screen affects the display synchronization effect, the setting position of the target screen refers to the number of lines of the target screen.
The synchronous display effect of the target screen is influenced due to the number of lines of the target screen. As shown in fig. 2, which is a schematic view of a tv wall composed of 3 rows and 3 columns of display screens, the refresh rates of the first row of display screens 1 and the second row of display screens 4 are the same, and the image refresh start time of each screen is the same. But for the entire video wall, the starting point for scanning the entire image is a1, scanning from top to bottom in sequence. For 60 frames, the time for scanning the display screen 1 from a1 to a2 image needs 16.66ms, and at the same time, the display screen 4 of the second row has been scanned from a2 to the position of A3, and at this time, the screen of the first row of display screens and the screen of the second row of display screens will have 16.66ms delay, that is, the screen is out of sync. In order to solve the problem, firstly, a delay parameter of the display screen, namely delay time, needs to be determined, and picture display on the display screen is controlled according to the delay time.
Specifically, the setting position of the target screen comprises the number of lines of the target screen, and the time of the display picture of the target screen, which is delayed from the display picture of the first line screen, is determined according to the number of lines of the target screen, and is used as the delay parameter. Illustratively, the delay parameter of the first line of screens is 0, the second line of screens is based on the first line of screens, the delay parameter is the display time of one frame of image, the display time is determined by calculation according to the resolution of the image, for example, the delay parameter can be set to 16.66ms, and so on, the asynchronous phenomenon is more serious when the number of lines is larger, and the corresponding delay parameter is doubled.
And 102, resetting a counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board.
And the counter display module associated with the target screen is used for controlling the time of the target screen for displaying the picture. Because the number of lines of the target screen is different and the parameters to be delayed are different, and the delay parameters of all screens in the television wall are based on the display screen in the first line as the reference standard, the reset operation needs to be performed on the display module of the counter of all screens in the television wall. The reset operation is to send the display counter to perform zero clearing operation so as to perform recounting after zero clearing.
Specifically, the main control board sends a display frame sending synchronization signal to the controlled counter display sending modules associated with all screens, and when the counter display sending module associated with the target screen receives the display frame sending synchronization signal sent by the adjacent main control board, the reset zero clearing operation is performed on the counter display sending module. Illustratively, the FPGA of the main control board sends frame pulses to the FPGA counter display sending modules of all the output service boards, and the FPGA of the output service board associated with the target screen receives the frame pulses sent by the adjacent main control board after determining the delay parameters, so that the FPGA counter display sending module executes the reset operation. Because the FPGA counter display sending module needs to wait for the time delay parameter synchronization and then carries out the reset operation, the reset time of the FPGA counter display sending modules of all the output service board cards is the same, namely the counting zero clearing operation is carried out simultaneously, and the foundation is laid for the subsequent time delay synchronous display.
And 103, determining the time for resetting the counter display sending module according to the delay parameter so as to synchronously display all screens.
The reset operation refers to a reset operation for performing recounting on the counter display sending module. The start of the recounting indicates that the screen is displayed according to the counted time.
If the target screen is located in a non-first line of the television wall, the picture display start time of the target screen needs to be delayed according to the delay parameter on the basis of the picture display start time of the first line screen, so that the picture of the target screen and the picture of the first line screen are ensured to be synchronous.
Specifically, after delaying the picture output interface corresponding to the target screen according to the delay parameter, the counter is sent to the display module for resetting. And simultaneously, after delaying the picture output interface corresponding to any screen according to the delay parameter of the screen, performing reset operation on the counter display sending modules associated with all screens, so that the counter display sending modules associated with all screens start to count again at the same time, and outputting pictures to the corresponding picture output interfaces according to the corresponding delay, so that all screens synchronously display the pictures.
In one possible embodiment, the delay parameter is determined based on a blanking delay time; wherein, the blanking delay time is the delay time difference between adjacent lines of screens;
accordingly, step 103 comprises:
determining a comparison result of the delay parameter and the preset single-frame acquisition time; the preset single-frame image acquisition time is determined according to the resolution of the display image;
if the delay parameter is smaller than the preset single-frame acquisition time, delaying the image display of the target screen according to the delay parameter, and executing the reset-releasing operation of the counter display sending module;
and if the delay parameter is greater than or equal to the preset single-frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and executing the reset-releasing operation of the counter display sending module.
The delay parameter refers to a delay time required by display of effective pixels in an image when the image is displayed, and since a frame of image includes the effective pixels and blanking pixels when displayed, only the effective pixels are displayed when the image is displayed on a screen, the image display of a target screen needs to be delayed according to the delay time after the blanking pixels are removed, so as to ensure the accuracy of the image delay. The delay parameter of the target screen is compared with that of the first line screen, the blanking delay time is the delay time difference between adjacent line screens, and the delay parameter of the target screen is determined according to the product of the line number difference and the blanking delay time between the target screen and the first line screen. For example, the delay time difference between adjacent line screens is approximately the display duration of one frame of image, and the specific accurate time may be determined by calculation according to the resolution of the image, for example, the delay time difference may be set to 16ms (approximately 16ms, and the accurate time needs to be obtained by calculation), then the line number difference between the third line target screen and the first line screen is 2, then the delay parameter of the second line target screen is 32ms, and this value may be determined according to the delay time difference between adjacent line screens, and so on.
Since the delay parameter of the target screen indicates the degree of delay required for the initial time of the image display of the target screen, if the delay time of the target screen exceeds the acquisition time of one frame of image, in this case, if the image display of the target screen is delayed according to the delay time, the image display is inaccurate. Therefore, in the embodiment of the present invention, if the delay parameter to be delayed determined by the target screen is greater than or equal to the preset single-frame acquisition time, the frame skipping delay processing is directly performed to delay the image display of the target screen.
Specifically, the preset single-frame acquisition time represents the acquisition time of a single frame of a picture to be displayed by the target screen, and the acquisition time includes the acquisition time of both the effective pixels and the blanking pixels. Determining a comparison result of the delay parameter and the preset single-frame acquisition time, and if the delay parameter is smaller than the preset single-frame acquisition time, indicating that the time required by the target screen is smaller than the acquisition time of one frame of image, directly delaying the image display of the target screen according to the delay parameter; if the delay parameter is greater than or equal to the preset single-frame acquisition time, the time required by the target screen to be delayed is greater than the acquisition time of one frame of image, and the target screen needs to process the delay time according to frame skipping. For example, the frame skipping parameter of the target screen is equal to the rounded value of the blanking delay time divided by the frame skipping reference time, and the delay margin parameter is the remainder of the blanking delay time divided by the total preamble delay time.
Illustratively, the preset single-frame acquisition time is determined to be 16.66ms according to the resolution of the image to be displayed, if the target screen is located on the second line of the television wall, the determined delay parameter is approximately 16ms, the specific value can be calculated according to the actual situation, the specific value is not strictly limited, and since the 16ms is less than 16.66ms, the screen of the second line directly displays the image according to the delay parameter, so that the image display delay is realized. If the target screen is located on the third row of the television wall, the determined delay parameter is approximately 32ms, and similarly, the specific value may be calculated according to an actual situation, which is not strictly limited herein, because 32ms is greater than 16.66ms, that is, the time required for delaying the screen on the third row is greater than the acquisition time of one frame of image, the image display of the target screen on the third row needs to be delayed according to the frame skipping parameter and the delay margin parameter. The frame skipping reference time represents the multiple of frame skipping required by the target screen, so that the total preamble delay time is 32ms, the frame skipping parameter is 32ms/32ms which is 1 frame, and the delay margin parameter is 0, that is, one frame skipping processing is required when the third row target screen is delayed. And after correspondingly delaying all the screens according to the delay parameters, executing the reset operation of the FPGA counter display sending module in the associated output service board card, so that the FPGA counter display sending module restarts counting from zero clearing, and performing display sending operation on the screens.
In one possible embodiment, the blanking delay time is determined according to the following equation:
blanking delay time is equal to horizontal total pixels (vertical total pixels-front edge parameter-synchronous width parameter-back edge parameter)/clock parameter;
wherein, the horizontal total pixel is a horizontal effective pixel + a horizontal blanking pixel, and the vertical total pixel is a vertical effective pixel + a vertical blanking pixel; the horizontal effective pixel, the horizontal blanking pixel, the vertical effective pixel and the vertical blanking pixel are determined according to the resolution of the image to be displayed; the leading edge parameter, the synchronization width parameter, the trailing edge parameter and the clock parameter are determined according to the time sequence characteristics of the image to be displayed.
The blanking delay time needs to eliminate the influence of blanking data which is not displayed in an image, so the blanking delay time is determined according to the blanking data of a display image, but the blanking delay time of a target screen needs to keep the blanking data in the horizontal direction and eliminate the influence of the blanking data in the vertical direction because the screen display is delayed in the vertical direction and the horizontal direction needs to scan according to a normal picture. The sum of the leading edge parameter, the synchronization width parameter and the trailing edge parameter represents a blanking pixel, and the leading edge parameter, the synchronization width parameter and the trailing edge parameter are determined according to the time sequence characteristics of the display image, namely according to the output resolution of the display image. The horizontal total pixels and the vertical total pixels represent total pixel points on the image in the horizontal direction and the vertical direction.
In one possible embodiment, before step 103, the method further comprises:
determining whether the clock of the main control board and the clock of the output service board card associated with the target screen are homologous clocks;
if not, correcting the clock of the output service board card according to the clock of the main control board, and then determining the time for performing reset operation on the counter display sending module according to the delay parameter;
if the clock is the same source clock, the time for performing the reset operation on the counter display sending module is determined according to the delay parameter.
Whether the clock of the main control board and the clock of the output service board card associated with the target screen are the homologous clocks means whether the clock of the output service board card generates a local clock signal of the output service board card, and if the output service board card generates the local clock signal of the output service board card and the local clock signal is taken as a reference to carry out display counting, the clock of the main control board and the clock of the output service board card associated with the target screen are the nonhomologous clocks; and if the output service board card does not generate the local clock signal of the output service board card, the clock signal of the main control board is taken as a reference to carry out display counting, and the clock of the main control board and the clock of the output service board card related to the target screen are the same source clock. For example, the clock of the service board is the clock generated by the master CPLD, which is the homologous clock, otherwise, the clock is the non-homologous clock.
If the clock of the main control board and the clock of the output service board card associated with the target screen are the same source clock, the counter display sending module is cleared, and after delaying according to the delay parameter, the counter display sending module is subjected to reset operation, for example, the delay and frame skipping number are configured to the associated FPGA by delaying the display sending time of different lines of screens, and the FPGA controls the internal counter display sending module to achieve the purpose of delay synchronization, so that the phenomenon of visual synchronization of the whole picture is achieved.
If the clock of the main control board and the clock of the output service board card associated with the target screen are non-homologous clocks, the frame pulse generated by the main control CPLD is used as a calibration clock, and the frame pulse generated by the main control CPLD is replaced by the reference clock generated by the output service board card FPGA, so that the effect of synchronizing the clocks of all the output service board cards is realized. After the clock synchronization of all the output service board cards is realized, the delay is carried out according to the delay parameters, and then the reset operation is carried out on the counter display sending module.
In a possible embodiment, correcting the clock of the output service board according to the clock of the main control board includes:
outputting a local clock generated by a service board card;
resetting a counter module associated with a target screen according to a clock frame synchronization signal sent by a main control board;
and regenerating the reference clock according to the counter module after the reset operation.
The clock of the main control board and the clock of the output service board card associated with the target screen are non-homologous clocks, the clock generated by the main control board and the clock of the output service board card are non-homologous clocks, for example, under the condition that the clock pulse of the main control CPLD is faster than the clock of the output service board card, each frame is faster, and after accumulation, a second line screen of a certain frame is faster than a first line screen, so that the phenomenon of asynchronization is caused. At this time, the effect that the synchronization cannot be achieved by simply carrying out the time delay according to the time delay parameters is achieved, and in the embodiment of the invention, the FPGA on each output service board card is adopted to generate the pulse signals by itself, so that the pulse signals replace the pulse signals generated by the main control board. Illustratively, a clock generated by the master control CPLD is used as a calibration clock, when the configuration parameters of the video wall are completed, the parameters are issued to be synchronized, and then the counters of all output service board FPGAs generating local pulses are cleared after the clock frame synchronization signals transmitted by the master control board CPLD and the like arrive, so that the effect of synchronizing the local pulses of all the output service board FPGAs is achieved.
In a possible embodiment, before step 101, the method further comprises:
determining a synchronous display mode of a target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
if the synchronous display mode is the synchronous mode, performing reset operation on a counter display sending module associated with the target screen according to a display sending frame synchronous signal of the main control board;
and if the synchronous display mode is the synchronous delay mode, continuously determining the delay parameter of the target screen according to the setting position of the target screen.
The screen attribute characteristics of the target screen are determined according to the screen material and other characteristics, illustratively, the association relationship between the screen attribute characteristics of the target screen and the synchronous display mode is established in advance, and after the screen attribute characteristics of the target screen are determined, the synchronous display mode for operating the target screen can be determined. Illustratively, when the target screen is an LCD screen, the synchronous display mode may be a synchronous delay mode; and when the target screen is the small-distance LED screen, the synchronous display mode is the synchronous mode, and the synchronous display mode is determined according to the screen display principle determined by the screen attribute characteristics.
If the synchronous display mode of the target screen is the synchronous delay mode, the delay parameter of the target screen is determined according to the set position of the target screen, namely the delay parameter is issued according to the number of lines of the target screen, and synchronization of all the output service board cards and all the FPGAs is ensured.
Because the power-on time of each output service board card is different, the display sending time of each output service board card is also different, and the problem of desynchrony caused by screen display is solved. In the embodiment of the invention, if the synchronous display mode of the target screen is the synchronous mode, FPGA synchronization is realized, firstly, all FPGA clocks of the output service board cards are ensured to be homologous clocks and are generated by the FPGA of the main control board; and secondly, the main control board FPGA can generate a frame synchronization signal, such as a frame synchronization pulse, and all output service boards related to the screen perform de-resetting on the counter display sending module of each FPGA according to the frame synchronization pulse.
In a possible embodiment, the performing a reset operation on the counter display sending module associated with the target screen according to the display sending frame synchronization signal of the main control board includes:
locking image display parameters of a target screen;
the counter associated with the target screen is sent to the display module for resetting operation;
and if receiving a display frame sending synchronization signal sent by the main control board, performing resetting operation on a counter display sending module associated with the target screen.
When a television wall is created, the television walls with different resolutions can send VESA standard video display time sequence signals with corresponding resolutions to an FPGA of an output service board card, namely image display parameters of a target screen; after the signal is stable, the FPGA locks the phase-locked loop, namely the FPGA related to the target screen locks the image display parameters of the target screen; meanwhile, the counter display module in the FPGA can be reset, so that the counter is reset. And then after all the output service board FPGA modules wait until the main control board FPGA generates adjacent frame synchronization pulses, the FPGA sends the internal counter to the display module for reset operation, so that the counter is sent to the display module for uniform counting operation, thereby realizing the effect that the FPGAs of all the output service boards synchronously send the display.
The method comprises the steps of determining a delay parameter of a target screen according to a set position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronization signal sent by a main control board; and determining the time for resetting the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of the display sending modules of all the screen counters is realized through the display sending frame synchronization signals sent by the main control board, and meanwhile, the problem of asynchronous display of different lines of display screens during multi-screen display is solved through determining delay parameters by screen positions, so that the picture synchronization effect of a television wall is realized, and the applicability is strong.
Example two
Fig. 3 is a flowchart of a control method for multi-screen synchronous display according to a second embodiment of the present invention, and as shown in fig. 3, the method includes:
configuring a control mode of multi-screen synchronous display on a web interface, for example, issuing a command to configure the control mode into a synchronous mode or a synchronous delay mode; the client sends a synchronization command after receiving the configuration of the web interface, the control software of the multi-screen display sends the synchronization command to the driver after receiving the command, and the driver sets relevant parameters according to the command after receiving the command, wherein the parameters comprise the delay parameters of each screen and the like. And the FPGA associated with each screen processes according to the related parameters stored in the register, so that the synchronous display of the multiple screens is realized.
FIG. 4 is a flowchart illustrating a control method for multi-screen simultaneous display in the synchronous mode. As shown in fig. 4, in the synchronous mode, firstly, the resolution of the television wall needs to be reconfigured according to the output resolution of the image to be displayed, and the horizontal blanking parameter and the vertical blanking parameter of the television wall need to be configured, that is, the television walls with different resolutions will send the VESA standard video display timing signals with corresponding resolutions to the FPGA of the output service board card; and after the signals are stable, the FPGA locks the phase-locked loop, namely the FPGA related to each screen locks the related display parameters of the target screen. After parameters are locked, resetting operation is carried out on the FPGA counter display sending module associated with each screen, namely counting zero clearing operation is carried out, then after all the FPGA modules of the output service board cards wait until the adjacent frame synchronization pulse generated by the FPGA of the main control board arrives, the FPGA sends the internal counter display sending module to carry out resetting operation, so that the counters of the internal counter display sending modules carry out unified counting operation, and therefore the FPGA of all the output service board cards achieves the effect of synchronous display sending. And after simultaneous unified counting operation is carried out, generating display-sending line field blanking parameters, and sending and displaying the display-sending images according to the parameters to realize the synchronous display effect of the multi-screen images. In a synchronous mode, firstly, ensuring that all output service board FPGA clocks are homologous clocks and are generated by a main control board FPGA uniformly; and secondly, the FPGA of the main control board can generate a frame synchronization pulse, and all the output board cards send the display module of each FPGA to perform resetting according to the frame synchronization pulse. The problem of asynchronous transmission and display time difference of each output service board card caused by different power-on time of each output service board card is solved.
Fig. 5 is a flowchart illustrating a control method for multi-screen synchronous display when a clock of the main control board and a clock of an output service board associated with each screen in the synchronous delay mode are the same source clock. As shown in fig. 5, in the synchronous delay mode, when the clock of the main control board and the clock of the output service board associated with each screen are the same source clock, first, software issues delay levels of VOs (picture output interfaces) in different rows, where different delay levels correspond to different delay parameters, and each VO is associated with one display screen. Fig. 5 only illustrates the delay parameters of four lines of screens, and so on, which are not described herein again, and 16ms is the blanking delay time, and is determined according to the output resolution of the display image.
Each screen corresponds to a register for configuring and storing the delay parameters and the enabling bits of the screen, and then the delay parameters of each screen are configured to the FPGA of the associated different output service board cards, so that all FPGA parameters are synchronized, and the operation of the enabling bit bits is synchronized. And after the FPGA of each output service board card receives the adjacent FPGA frame pulse of the main control board, resetting the FPGA counter display module to clear the counter. And finally, determining the time for performing reset operation on the corresponding counter display sending module according to the delay parameters of each screen so as to synchronously display all the screens.
Illustratively, software issues a corresponding configuration command, that is, a display sending delay parameter of each line of VOs, according to the difference of the line number where the VOs are located. All delay parameters are configured by taking the first line VO as a reference, the first line VO is not delayed, the second line delay is 16ms, and the 16ms is that the video display time sequence standard of the image display contains blanking data, and after blanking is removed, the effective data display time of one frame of image is 16 ms. Line 3 is delayed by 32ms, but since 60 frames are acquired, the time for one frame is 16.6ms, and the delay time must be within 16.6ms to be effective, the delay parameter cannot be directly configured to be 32ms from the third line. Because 4 frames of image data are buffered in the FPGA, reading is one frame later than writing, FPGA acquisition is carried out according to 60 frames, but 60 frames are extracted into 30 frames for processing inside, and finally, the frame is sent for display and is doubled into 60 frames for display. Therefore, the VO in the 3 rd row directly jumps by one frame, the display is sent from the next frame, 0ms is delayed, and the like; and in the VO in the 4 th row, frame skipping processing is required, one frame is skipped first, and then the delay is carried out for 16 ms. At the moment, all LCD screens are synchronous in visual display effect, and practically, each VO is subjected to corresponding time delay processing, so that the synchronous display effect of multiple screens is realized. The values of the delay time, the display time and the like can be accurately calculated according to the resolution of the actually displayed image, and the value in the example is only one example and is an approximate value.
Fig. 6 is a flowchart illustrating a control method for multi-screen synchronous display when a clock of the main control board and a clock of an output service board associated with each screen in the synchronous delay mode are non-homologous clocks. As shown in fig. 6, in the synchronous delay mode, when the clock of the main control board and the clock of the output service board associated with each screen are non-homologous clocks, and the CPLD pulse of the main control board is faster than VO0, each frame is faster, and after accumulation, there is a frame of VO1 faster than VO0, which results in that different rows of VOs display unsynchronized. Because the clock is a non-homologous clock, the synchronization effect cannot be achieved simply according to the delay parameter, under the condition, after the software issues the delay grades of VOs in different rows, the frame pulse generated by the CPLD of the main control board is used as a calibration clock while the delay parameter is configured and the display module of the FPGA counter is reset, and the frame pulse generated by the CPLD of the main control board is replaced by the reference clock generated by the FPGA of the output service board, so that the clock synchronization effect of all the output boards is realized. Illustratively, each output board card comprises an FPGA (field programmable gate array) on the expansion cabinet to generate a pulse signal by itself, so that the pulse signal replaces the pulse signal generated by the CPLD (complex programmable logic device) to perform frame skipping operation. The clock generated by the master control CPLD is used as a calibration clock, when the configuration parameters of the television wall are completed, the issued parameters are synchronized, and then after the adjacent frame pulse transmitted by the master control board CPLD arrives, the counters for generating the local pulse for all the output board FPGAs are cleared, so that the effect of synchronizing all the FPGA local pulses is achieved, and the effect of synchronous delay can be achieved. On the basis, the time for performing reset operation on each counter display sending module is determined according to the delay parameters so as to perform synchronous display of all screens.
The embodiment of the invention can realize the picture synchronization effect under the homologous clock or the non-homologous clock, and has strong applicability and good synchronization effect. The FPGA is used for controlling the time delay of different line screens of the television wall, and the FPGA controls the reset and reset opportunity of the display sending module of the counter inside the FPGA, so that the purpose of carrying out time delay display sending on different related screens by different FPGAs is realized, and the synchronization effect is safe and reliable and has high efficiency.
EXAMPLE III
Fig. 7 is a schematic structural diagram of a control apparatus for multi-screen synchronous display according to a third embodiment of the present invention, which is applicable to a case where synchronous display control is performed on multiple display screens controlled by a mosaic device, where all the screens are controlled and displayed by a same main control board. As shown in fig. 7, the apparatus includes:
a delay parameter determining module 710, configured to determine a delay parameter of a target screen according to a set position of the target screen;
the display sending resetting module 720 is used for resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and the display sending and display resetting module 730 is used for determining the time for resetting the counter display sending module according to the delay parameter so as to synchronously display all screens.
The method comprises the steps of determining a delay parameter of a target screen according to a set position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronization signal sent by a main control board; and determining the time for resetting the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of the display sending modules of all the screen counters is realized through the display sending frame synchronization signals sent by the main control board, and meanwhile, the problem of asynchronous display of different lines of display screens during multi-screen display is solved through determining delay parameters by screen positions, so that the picture synchronization effect of a television wall is realized, and the applicability is strong.
Optionally, the delay parameter is determined according to a blanking delay time; wherein, the blanking delay time is the delay time difference between adjacent lines of screens;
correspondingly, send apparent reset module that explains specifically to be used for:
determining a comparison result of the delay parameter and the preset single-frame acquisition time; the preset single-frame image acquisition time is determined according to the resolution of the image to be displayed;
if the delay parameter is smaller than the preset single-frame acquisition time, delaying the image display of the target screen according to the delay parameter, and then executing the reset-releasing operation of the counter display sending module;
and if the delay parameter is greater than or equal to the preset single-frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and executing the reset-releasing operation of the counter display-sending module.
Optionally, the blanking delay time is determined according to the following formula:
blanking delay time is equal to horizontal total pixels (vertical total pixels-front edge parameter-synchronous width parameter-back edge parameter)/clock parameter;
wherein, the horizontal total pixel is a horizontal effective pixel + a horizontal blanking pixel, and the vertical total pixel is a vertical effective pixel + a vertical blanking pixel; the horizontal effective pixel, the horizontal blanking pixel, the vertical effective pixel and the vertical blanking pixel are determined according to the resolution of the image to be displayed; and the leading edge parameter, the synchronous width parameter, the trailing edge parameter and the clock parameter are determined according to the time sequence characteristics of the display image.
Optionally, the apparatus further includes a source clock determining module, configured to determine, according to the delay parameter, a time for performing a reset operation on the counter display module, where the time includes:
a judging unit, configured to determine whether the clock of the main control board and the clock of the output service board associated with the target screen are homologous clocks;
the clock correction unit is used for correcting the clock of the output service board card according to the clock of the main control board if the clock is not the same source clock, and then determining the time for performing the reset operation on the counter display sending module according to the delay parameter;
and the display sending and decoding resetting unit is used for determining the time for decoding and resetting the display sending module of the counter according to the delay parameter if the clock is the same source clock.
Optionally, the clock correction unit is specifically configured to:
the output service board card generates a local clock;
resetting the counter module associated with the target screen according to a clock frame synchronization signal sent by the main control board;
and regenerating the reference clock according to the counter module after the reset operation.
Optionally, the method further includes a mode selection module, configured to, before determining the delay parameter of the target screen according to the set position of the target screen, include:
a mode determination unit for determining a synchronous display mode of the target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
the synchronous mode unit is used for performing reset operation on a counter display sending module associated with a target screen according to a display sending frame synchronous signal of the main control board if the synchronous display mode is the synchronous mode;
and the synchronous delay mode unit is used for continuously determining the delay parameter of the target screen according to the setting position of the target screen if the synchronous display mode is the synchronous delay mode.
Optionally, the synchronization mode unit includes:
locking image display parameters of a target screen;
resetting a counter display module associated with the target screen;
and if receiving a display frame sending synchronization signal sent by the main control board, performing reset operation on the counter display sending module associated with the target screen.
The multi-screen synchronous display control device provided by the embodiment of the invention can execute the multi-screen synchronous display control method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the multi-screen synchronous display control method.
Example four
Fig. 8 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention. FIG. 8 illustrates a block diagram of an exemplary electronic device 12 suitable for use in implementing embodiments of the present invention. The electronic device 12 shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiment of the present invention.
As shown in FIG. 8, electronic device 12 is embodied in the form of a general purpose computing device. The components of electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory device 28, and a bus 18 that couples various system components including the system memory device 28 and the processing unit 16.
The system storage 28 may include computer system readable media in the form of volatile storage, such as Random Access Memory (RAM)30 and/or cache storage 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 8, and commonly referred to as a "hard drive"). Although not shown in FIG. 8, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Storage 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in storage 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
The processing unit 16 executes various functional applications and data processing by running a program stored in the system storage device 28, for example, implementing a control method for multi-screen synchronous display provided in an embodiment of the present invention, where all screens are controlled and displayed by the same main control board, and the method includes:
determining a delay parameter of a target screen according to the set position of the target screen;
resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and determining the time for resetting the counter display sending module according to the delay parameters so as to synchronously display all screens.
EXAMPLE five
The fifth embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method for controlling multi-screen synchronous display provided in the fifth embodiment of the present invention is implemented, where all screens are controlled and displayed by a same main control panel, and the method includes:
determining a delay parameter of a target screen according to the set position of the target screen;
resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and determining the time for resetting the counter display sending module according to the delay parameters so as to synchronously display all screens.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, or the like, as well as conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A control method for multi-screen synchronous display is characterized in that all screens are controlled and displayed by the same main control panel, and comprises the following steps:
determining a delay parameter of a target screen according to the set position of the target screen;
resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and determining the time for resetting the counter display sending module according to the delay parameters so as to synchronously display all screens.
2. The method of claim 1, wherein the delay parameter is determined based on a blanking delay time; wherein, the blanking delay time is the delay time difference between adjacent lines of screens;
correspondingly, the determining the time for performing the reset operation on the counter display sending module according to the delay parameter includes:
determining a comparison result of the delay parameter and the preset single-frame acquisition time; the preset single-frame image acquisition time is determined according to the resolution of the image to be displayed;
if the delay parameter is smaller than the preset single-frame acquisition time, delaying the image display of the target screen according to the delay parameter, and then executing the reset-releasing operation of the counter display sending module;
and if the delay parameter is greater than or equal to the preset single-frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and executing the reset-releasing operation of the counter display-sending module.
3. The method of claim 2, wherein the blanking delay time is determined according to the following equation:
blanking delay time is equal to horizontal total pixels (vertical total pixels-front edge parameter-synchronous width parameter-back edge parameter)/clock parameter;
wherein, the horizontal total pixel is a horizontal effective pixel + a horizontal blanking pixel, and the vertical total pixel is a vertical effective pixel + a vertical blanking pixel; the horizontal effective pixel, the horizontal blanking pixel, the vertical effective pixel and the vertical blanking pixel are determined according to the resolution of the image to be displayed; and the leading edge parameter, the synchronous width parameter, the trailing edge parameter and the clock parameter are determined according to the time sequence characteristics of the display image.
4. The method of claim 1, wherein prior to determining the timing for performing a reset operation on the counter presentation module based on the delay parameter, the method further comprises:
determining whether the clock of the main control board and the clock of the output service board card associated with the target screen are homologous clocks;
if not, correcting the clock of the output service board card according to the clock of the main control board, and then determining the time for performing reset operation on the counter display sending module according to the delay parameter;
and if the clock is the same source clock, determining the time for resetting the counter display sending module according to the delay parameter.
5. The method of claim 4, wherein correcting the clock of the output service board according to the clock of the master control board comprises:
the output service board card generates a local clock;
resetting the counter module associated with the target screen according to a clock frame synchronization signal sent by the main control board;
and regenerating the reference clock according to the counter module after the reset operation.
6. The method of claim 1, wherein before determining the delay parameter of the target screen according to the set position of the target screen, the method further comprises:
determining a synchronous display mode of the target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
if the synchronous display mode is the synchronous mode, performing reset operation on a counter display sending module associated with the target screen according to a display sending frame synchronous signal of the main control board;
and if the synchronous display mode is the synchronous delay mode, continuously determining the delay parameter of the target screen according to the set position of the target screen.
7. The method of claim 6, wherein performing a reset operation on the counter display sending module associated with the target screen according to the display sending frame synchronization signal of the main control board comprises:
locking image display parameters of a target screen;
resetting a counter display module associated with the target screen;
and if receiving a display frame sending synchronization signal sent by the main control board, performing reset operation on the counter display sending module associated with the target screen.
8. The utility model provides a controlling means that many screens synchronization show which characterized in that, all screens are controlled by same main control panel and are shown, include:
the delay parameter determining module is used for determining the delay parameter of the target screen according to the set position of the target screen;
the display sending reset module is used for resetting the counter display sending module associated with the target screen according to the display sending frame synchronization signal sent by the main control board;
and the display sending and decoding resetting module is used for determining the time for decoding and resetting the counter display sending module according to the delay parameter so as to synchronously display all screens.
9. An electronic device, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the control method for multi-screen simultaneous display according to any one of claims 1-7.
10. A computer-readable storage medium on which a computer program is stored, the program, when executed by a processor, implementing a method for controlling a multi-screen simultaneous display according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111231668.3A CN114217752B (en) | 2021-10-22 | 2021-10-22 | Control method and device for multi-screen synchronous display, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111231668.3A CN114217752B (en) | 2021-10-22 | 2021-10-22 | Control method and device for multi-screen synchronous display, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114217752A true CN114217752A (en) | 2022-03-22 |
| CN114217752B CN114217752B (en) | 2024-02-06 |
Family
ID=80696105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111231668.3A Active CN114217752B (en) | 2021-10-22 | 2021-10-22 | Control method and device for multi-screen synchronous display, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114217752B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726400A (en) * | 2022-03-31 | 2022-07-08 | 成都信息工程大学 | Blind frequency hopping pattern FHSS signal frequency hopping removing method |
| CN115484136A (en) * | 2022-09-23 | 2022-12-16 | 瑞斯康达科技发展股份有限公司 | Method for determining frame synchronization signal, service card and communication equipment |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645261A (en) * | 2009-08-10 | 2010-02-10 | 广东威创视讯科技股份有限公司 | Line-field synchronous time sequence control method for separated screens in multi-screen display technique and system thereof |
| CN103065610A (en) * | 2013-01-08 | 2013-04-24 | 北京淳中视讯科技有限公司 | Split joint screen synchronous disposal method and split joint screen synchronous disposal device |
| CN103268209A (en) * | 2013-04-11 | 2013-08-28 | 威盛电子股份有限公司 | Television wall |
| CN103873828A (en) * | 2014-03-11 | 2014-06-18 | 浙江宇视科技有限公司 | Live flow sending display control method and device |
| CN106374946A (en) * | 2016-08-17 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | Radio frequency panoramic scanning circuit of receiver |
| CN106454010A (en) * | 2016-10-21 | 2017-02-22 | 青岛海信电器股份有限公司 | Synchronous display calibration method for multi-screen spliced display system, displays and multi-screen spliced display system |
| US20180077348A1 (en) * | 2015-06-02 | 2018-03-15 | Olympus Corporation | Display control device and imaging device |
| US20180322823A1 (en) * | 2017-05-03 | 2018-11-08 | Apple Inc. | Display scan time compensation systems and methods |
| CN110399110A (en) * | 2019-07-24 | 2019-11-01 | 浙江大华技术股份有限公司 | Multi-screen synchronous display methods and system, display equipment and storage medium |
| CN112702634A (en) * | 2019-10-23 | 2021-04-23 | 西安诺瓦星云科技股份有限公司 | Image display method, device and system and display screen controller |
| CN112995531A (en) * | 2019-12-13 | 2021-06-18 | 浙江宇视科技有限公司 | Synchronous splicing display method and device, decoding splicing controller and medium |
-
2021
- 2021-10-22 CN CN202111231668.3A patent/CN114217752B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645261A (en) * | 2009-08-10 | 2010-02-10 | 广东威创视讯科技股份有限公司 | Line-field synchronous time sequence control method for separated screens in multi-screen display technique and system thereof |
| CN103065610A (en) * | 2013-01-08 | 2013-04-24 | 北京淳中视讯科技有限公司 | Split joint screen synchronous disposal method and split joint screen synchronous disposal device |
| CN103268209A (en) * | 2013-04-11 | 2013-08-28 | 威盛电子股份有限公司 | Television wall |
| CN103873828A (en) * | 2014-03-11 | 2014-06-18 | 浙江宇视科技有限公司 | Live flow sending display control method and device |
| US20180077348A1 (en) * | 2015-06-02 | 2018-03-15 | Olympus Corporation | Display control device and imaging device |
| CN106374946A (en) * | 2016-08-17 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | Radio frequency panoramic scanning circuit of receiver |
| CN106454010A (en) * | 2016-10-21 | 2017-02-22 | 青岛海信电器股份有限公司 | Synchronous display calibration method for multi-screen spliced display system, displays and multi-screen spliced display system |
| US20180322823A1 (en) * | 2017-05-03 | 2018-11-08 | Apple Inc. | Display scan time compensation systems and methods |
| CN110399110A (en) * | 2019-07-24 | 2019-11-01 | 浙江大华技术股份有限公司 | Multi-screen synchronous display methods and system, display equipment and storage medium |
| CN112702634A (en) * | 2019-10-23 | 2021-04-23 | 西安诺瓦星云科技股份有限公司 | Image display method, device and system and display screen controller |
| CN112995531A (en) * | 2019-12-13 | 2021-06-18 | 浙江宇视科技有限公司 | Synchronous splicing display method and device, decoding splicing controller and medium |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726400A (en) * | 2022-03-31 | 2022-07-08 | 成都信息工程大学 | Blind frequency hopping pattern FHSS signal frequency hopping removing method |
| CN114726400B (en) * | 2022-03-31 | 2023-08-04 | 成都信息工程大学 | Frequency hopping method for FHSS signal of blind frequency hopping pattern |
| CN115484136A (en) * | 2022-09-23 | 2022-12-16 | 瑞斯康达科技发展股份有限公司 | Method for determining frame synchronization signal, service card and communication equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114217752B (en) | 2024-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10613812B2 (en) | System, control apparatus and control method for distributed video display | |
| TWI534795B (en) | Techniques for aligning frame data | |
| KR101260426B1 (en) | Techniques for aligning frame data | |
| CN114217752B (en) | Control method and device for multi-screen synchronous display, electronic equipment and storage medium | |
| KR101467714B1 (en) | Image synchronization for multiple displays | |
| US20160180812A1 (en) | Display device, display system including the same and display method thereof | |
| KR102362054B1 (en) | Display apparatus consisting a multi display system and control method thereof | |
| EP1998315B1 (en) | Resolution detecting circuit and method thereof | |
| US4720708A (en) | Display control device | |
| CN103021378A (en) | Method and device for multi-screen mosaic display | |
| CN113205779B (en) | Multi-screen synchronous control method, device and system suitable for electronic ink screen | |
| TWI424430B (en) | Device and method for controlling input/output frame | |
| US9087473B1 (en) | System, method, and computer program product for changing a display refresh rate in an active period | |
| EP3855719A1 (en) | Image display method and apparatus, and smart television and readable storage medium | |
| CN103024430A (en) | Control display method and system for simulating red, green and blue (RGB) signal | |
| CN115119532B (en) | Signal processing method and device and display device | |
| CN114982250B (en) | Signal processing method and device and display device | |
| KR100750452B1 (en) | Method and apparatus of testing control signals for display device and display apparatus having test function | |
| JP2001083927A (en) | Display device and its driving method | |
| CN112486438A (en) | OSD (on-screen display) cross-screen scrolling display method and device and display output equipment | |
| CN112565738A (en) | Video source state detection method and device | |
| EP4276813A1 (en) | Display device and display control method | |
| CN114035758B (en) | Image mosaic display system and image mosaic display method | |
| CN114302090A (en) | Control method and control system for multi-screen display quality under same resolution | |
| CN114500767A (en) | Input video source adjusting method and device, video input card and video processing equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |