CN114217752B - Control method and device for multi-screen synchronous display, electronic equipment and storage medium - Google Patents
Control method and device for multi-screen synchronous display, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
Abstract
The embodiment of the invention discloses a control method and device for multi-screen synchronous display, electronic equipment and a storage medium. The control method for the multi-screen synchronous display comprises the following steps: determining delay parameters of a target screen according to the setting position of the target screen; resetting a counter display sending module associated with the target screen according to a display sending frame synchronous signal sent by a main control board; and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens. According to the embodiment of the invention, the reset synchronization of all the screen counter display modules is realized through the display frame transmission synchronization signals sent by the main control board, meanwhile, the problem that the picture display of different lines of display screens is not synchronous when the multi-screen display is performed is solved through the determination of the delay parameters by the screen positions, the picture synchronization effect of the television wall is realized, and the applicability is strong.
Description
Technical Field
The embodiment of the invention relates to the technical field of screen display, in particular to a control method and device for multi-screen synchronous display, electronic equipment and a storage medium.
Background
Along with the vigorous popularization of smart cities, large-screen display is generally realized by using a multi-screen splicing mode due to the large production difficulty, high cost and other reasons of a single large screen, so that monitoring type splicing control equipment is more and more popular. For example, the display pictures of a plurality of display screens are spliced together by using the splicing control equipment on a monitoring site, so that the television wall formed by the plurality of display screens jointly displays the same picture.
For the spelling control equipment, a plurality of output boards are often arranged, and a plurality of picture output interfaces can be established by the plurality of output boards, and each picture output interface is connected with one display screen, so that the spelling control equipment can simultaneously control a plurality of display screens. Under the condition that the television wall formed by splicing a plurality of display screens is multi-row and multi-column, an image input source is dragged into the whole television wall, and as the image refreshing initial time of each display screen is the same, the whole television wall is scanned by the whole image from top to bottom in sequence, so that the phenomenon that images are not synchronous when the display screens positioned in different rows display the images can occur, and the larger the number of lines is, the more serious the phenomenon is, and the whole display effect of the television wall is affected.
Disclosure of Invention
The embodiment of the invention provides a control method, a device, electronic equipment and a storage medium for multi-screen synchronous display, solves the problem that different rows of display screens are not synchronous in picture display during multi-screen display, realizes the picture synchronization effect of a television wall, and has strong applicability.
In a first aspect, an embodiment of the present invention provides a method for controlling multi-screen synchronous display, where all screens are controlled and displayed by a same main control board, including:
determining delay parameters of a target screen according to the setting position of the target screen;
resetting a counter display sending module associated with the target screen according to a display sending frame synchronous signal sent by a main control board;
and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens.
In a second aspect, an embodiment of the present invention further provides a control device for multi-screen synchronous display, where all screens are controlled and displayed by a same main control board, including:
the delay parameter determining module is used for determining delay parameters of the target screen according to the setting position of the target screen;
the display sending and resetting module is used for resetting the counter display sending module associated with the target screen according to the display sending frame synchronizing signal sent by the main control board;
And the display sending and resetting module is used for determining the time for performing the resetting operation on the counter display sending module according to the delay parameter so as to synchronously display all screens.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
one or more processors;
storage means for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement a method for controlling multi-screen synchronous display according to any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, where the program when executed by a processor implements a method for controlling multi-screen synchronous display according to any embodiment of the present invention.
According to the embodiment of the invention, the delay parameter of the target screen is determined according to the setting position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronous signal sent by a main control board; and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of all the screen counter display modules is realized through the display frame transmission synchronization signals sent by the main control board, and meanwhile, the problem that the picture display of different lines of display screens is asynchronous when the multi-screen display is performed is solved through the determination of the delay parameters by the screen positions, so that the picture synchronization effect of the television wall is realized, and the applicability is strong.
Drawings
FIG. 1 is a flow chart of a method for controlling multi-screen synchronous display in accordance with a first embodiment of the present invention;
FIG. 2 is a schematic view of a video wall made up of 3 rows and 3 columns of display screens;
FIG. 3 is a flowchart of a method for controlling multi-screen synchronous display in a second embodiment of the present invention;
FIG. 4 is a flow chart of a control method of a multi-screen synchronous display in synchronous mode;
FIG. 5 is a flowchart of a control method for multi-screen synchronous display when the clock of the master control board and the clock of the output service board card associated with each screen are homologous clocks in the synchronous delay mode;
FIG. 6 is a flowchart of a control method for multi-screen synchronous display when the clock of the master control board and the clock of the output service board card associated with each screen are non-homologous clocks in the synchronous delay mode;
fig. 7 is a schematic structural diagram of a control device for multi-screen synchronous display in the third embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device in a fourth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a method for controlling multi-screen synchronous display in the first embodiment of the present invention, where the present embodiment may be applied to a case of implementing display synchronous control on a plurality of display screens controlled by a jigsaw device, where all the screens are controlled and displayed by the same main control board. The method can be performed by a control device for multi-screen synchronous display, the device can be implemented in a software and/or hardware mode and can be configured in an electronic device, for example, the electronic device can be a device with communication and computing capabilities, such as a background server. As shown in fig. 1, the method specifically includes:
and step 101, determining a delay parameter of the target screen according to the setting position of the target screen.
The target screen is any one of a plurality of screens forming a television wall, and the setting position of the target screen refers to the position of the target screen on the television wall, for example, the display synchronization effect is affected by the number of lines of the screen, so the setting position of the target screen refers to the number of lines of the target screen.
The synchronous display effect of the target screen is affected due to the number of lines of the target screen. As shown in fig. 2, which is a schematic view of a video wall composed of 3 rows and 3 columns of display screens, the refresh rates of the first row of display screen 1 and the second row of display screen 4 are the same, and the image refresh start time of each screen is the same. But for the whole television wall, the scanning starting point of the whole image is A1, and the scanning is sequentially performed from top to bottom. For 60 frames, 16.66ms is required for the display screen 1 to scan from the A1 to the A2 image, and at the same time, the second row of display screens 4 has scanned from the A2 to the A3 position, and the screen of the first row of display screens and the screen of the second row of display screens will have 16.66ms delay, namely, a picture dyssynchrony phenomenon occurs. To solve this problem, it is first necessary to determine a delay parameter of the display screen, i.e., a delay time, and control the picture display of the display screen according to the delay time.
Specifically, the setting position of the target screen includes the number of lines of the target screen, and the time delay of the display screen of the target screen compared with the display screen of the first line of screen is determined according to the number of lines of the target screen, and is used as the delay parameter. For example, the delay parameter of the first line of screen is 0, the second line of screen is based on the first line of screen, the delay parameter is the display time of one frame of image, the display time is calculated and determined according to the resolution of the image, for example, the delay parameter can be set to 16.66ms, and the like, the larger the number of lines is, the more serious the asynchronous phenomenon is, and the corresponding delay parameter is doubled.
And 102, resetting the counter display sending module associated with the target screen according to the display sending frame synchronizing signal sent by the main control board.
The counter sending and displaying module associated with the target screen is used for controlling the time of displaying the picture on the target screen. Because the number of lines of the target screen is different, and the delay parameters of all the screens in the television wall are based on the display screen in the first line as a reference standard, the counter display module of all the screens in the television wall needs to be reset. The reset operation is to zero the send counter to re-count after zero.
Specifically, the main control board sends a frame sending and displaying synchronizing signal to all the controlled counter sending and displaying modules associated with the screen, and when the counter sending and displaying module associated with the target screen receives the frame sending and displaying synchronizing signal sent by the adjacent main control board, the counter sending and displaying module is reset and cleared. The method includes that an FPGA of a main control board sends frame pulses to FPGA counter display sending modules of all output service boards, after delay parameters are determined, the FPGA of the output service board associated with a target screen receives the frame pulses sent by an adjacent main control board, and the FPGA counter display sending modules execute reset operation. Because the FPGA counter display sending module needs to wait for the delay parameter synchronization and then reset, the reset time of the FPGA counter display sending modules of all output service boards is the same, namely the counting zero clearing operation is performed simultaneously, and a foundation is laid for the subsequent delay synchronous display.
And step 103, determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all the screens.
The reset operation refers to a recovery operation of re-counting the counter display module. Starting the recounting means displaying the picture of the screen according to the counting time.
If the target screen is located in a non-first line of the television wall, the picture transmission start time of the target screen needs to be delayed according to the delay parameter on the basis of the picture transmission start time of the first line of the screen, so that the picture of the target screen and the picture of the first line of the screen are kept synchronous.
Specifically, after delaying the picture output interface corresponding to the target screen according to the delay parameter, the counter send-display module is subjected to a reset operation. And simultaneously delaying the picture output interface corresponding to any screen according to the delay parameter of the screen, and then performing a reset operation on the counter display sending modules associated with all the screens, so that the counter display sending modules associated with all the screens start to count again at the same time, and outputting pictures according to the corresponding delay, so that all the screens synchronously display the pictures.
In one possible embodiment, the delay parameter is determined from a blanking delay time; the blanking delay time is the delay time difference between adjacent line screens;
accordingly, step 103 includes:
determining a comparison result of the delay parameter and a preset single frame acquisition time; the preset single frame acquisition time is determined according to the resolution of the display image;
If the delay parameter is smaller than the preset single frame acquisition time, delaying the image display of the target screen according to the delay parameter, and then executing the reset operation of the counter display module;
if the delay parameter is greater than or equal to the preset single frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and executing the reset operation of the counter display sending module.
The delay parameter is delay time required by displaying effective pixels in an image when the image is displayed, and because the effective pixels and the blanking pixels are included when one frame of the image is displayed, only the effective pixels are displayed when the image is displayed on a screen, the image display of a target screen is required to be delayed according to the delay time after the blanking pixels are removed, so that the accuracy of the image delay is ensured. Since the delay parameter of the target screen is a delay parameter compared with that of the first line screen, the blanking delay time is a delay time difference between adjacent line screens, and the delay parameter of the target screen is determined according to the product of the line number difference between the target screen and the first line screen and the blanking delay time. For example, the delay time difference between adjacent line screens is approximately the display duration of one frame of image, the specific accurate time may be determined by calculation according to the resolution of the image, for example, the delay time difference may be set to 16ms (approximately 16ms, the accurate time needs to be obtained by calculation), the line number difference between the third line target screen and the first line screen is 2, the delay parameter of the second line target screen is 32ms, the value may be determined according to the delay time difference between the adjacent line screens, and so on.
The delay parameter of the target screen indicates the extent of delay required for the initial time of the picture display of the target screen, but if the delay time of the target screen exceeds the acquisition time of one frame of image, in this case, if the picture display of the target screen is still delayed according to the delay time, the problem of inaccurate picture display can be caused. Therefore, in the embodiment of the invention, if the delay parameter which is determined by the target screen and needs to be delayed is greater than or equal to the preset single frame acquisition time, the frame skip delay processing is directly performed to delay the picture display of the target screen.
Specifically, since the preset single frame acquisition time indicates the time of single frame acquisition of the picture to be displayed on the target screen, the acquisition time includes the acquisition time of the effective pixel and the acquisition time of the blanking pixel. Determining a comparison result of the delay parameter and the preset single frame acquisition time, and if the delay parameter is smaller than the preset single frame acquisition time to indicate that the time required for delaying the target screen is smaller than the acquisition time of one frame of image, delaying the image display of the target screen directly according to the delay parameter; if the delay parameter is greater than or equal to the preset single frame acquisition time, which means that the time of the target screen required to delay is greater than the acquisition time of one frame of image, the target screen needs to process the delay time according to the frame skipping. For example, the frame skip parameter of the target screen is equal to the integral value of the division of the blanking delay time and the frame skip reference time, and the delay margin parameter is the remainder of the division of the blanking delay time and the preamble delay total time.
For example, the preset single frame acquisition time is determined to be 16.66ms according to the resolution of the display image, if the target screen is located on the second row of the television wall, the determined delay parameter is about 16ms, the specific value can be calculated according to the actual situation, the specific value is not strictly limited here, and because 16ms is less than 16.66ms, the screen on the second row directly delays the display of the image according to the delay parameter. If the target screen is located in the third row of the tv wall, the determined delay parameter is approximately 32ms, and similarly, the specific value can be calculated according to the actual situation, which is not strictly limited herein, and since 32ms is greater than 16.66ms, that is, the time of the delay required by the third row of the screen is greater than the acquisition time of one frame of image, the image display of the target screen in the third row needs to be delayed according to the frame skipping parameter and the delay allowance parameter. The frame-skipping reference time represents a multiple of the frame-skipping required by the target screen, so that the total preamble delay time is 32ms, the frame-skipping parameter is 32ms/32 ms=1 frame, and the delay margin parameter is 0, namely the third line of target screen is delayed and needs to skip one frame. After corresponding delay is carried out on all the screens according to the delay parameters, the reset operation of the FPGA counter display module in the associated output service board card is carried out, so that the FPGA counter display module starts counting again from zero clearing, and the display operation is carried out on the screens.
In one possible embodiment, the blanking delay time is determined according to the following formula:
blanking delay time = horizontal total pixel (vertical total pixel-leading edge parameter-sync width parameter-trailing edge parameter)/clock parameter;
wherein, horizontal total pixel=horizontal effective pixel+horizontal blanking pixel, vertical total pixel=vertical effective pixel+vertical blanking pixel; the horizontal effective pixels, the horizontal blanking pixels, the vertical effective pixels and the vertical blanking pixels are determined according to the resolution of the display image; the front edge parameter, the synchronous width parameter, the back edge parameter and the clock parameter are determined according to the time sequence characteristics of the display image.
The blanking delay time needs to eliminate the influence of blanking data which is not displayed in the image, so that the blanking delay time is determined according to the blanking data of the transmitted and displayed image, but the blanking delay time of the target screen needs to keep the blanking data in the horizontal direction and remove the influence of the blanking data in the vertical direction because the delay time is caused in the vertical direction when the screen is displayed and the scanning is required to be performed according to the normal image in the horizontal direction. The sum of the front edge parameter, the synchronous width parameter and the back edge parameter represents blanking pixels, and the front edge parameter, the synchronous width parameter and the back edge parameter are determined according to the time sequence characteristics of the display image, namely, the output resolution of the display image. The horizontal total pixels and the vertical total pixels represent total pixel points on the image in the horizontal direction and the vertical direction.
In one possible embodiment, before step 103, the method further comprises:
determining whether the clock of the master control board and the clock of the output service board card associated with the target screen are homologous clocks;
if the clock is not the homologous clock, correcting the clock of the output service board card according to the clock of the main control board, and then executing the time for performing the reset operation on the counter display module according to the delay parameter;
if the clock is the same source clock, the time for performing the reset operation on the counter display module is determined according to the delay parameter.
Whether the clock of the master control board and the clock of the output service board card associated with the target screen are homologous clocks refers to whether the clock of the output service board card generates own local clock signals or not, if the output service board card generates own local clock signals, the display count is carried out by taking the local clock signals as the reference, and the clock of the master control board and the clock of the output service board card associated with the target screen are non-homologous clocks; if the output service board card does not generate a local clock signal, the clock signal of the main control board is taken as a reference to carry out display counting, and the clock of the main control board and the clock of the output service board card associated with the target screen are homologous clocks. The clock of the service board card is a clock generated by the master control CPLD, and is a homologous clock, or is a non-homologous clock.
If the clock of the main control board and the clock of the output service board card associated with the target screen are homologous clocks, the counter display module is subjected to zero clearing operation, and after delay is carried out according to delay parameters, the counter display module is subjected to reset releasing operation, for example, the display time of different lines of screens is delayed and the frame skip number is configured to an associated FPGA, and the FPGA controls the internal counter display module to realize the aim of delay synchronization, so that the phenomenon of visual synchronization of the whole picture is achieved.
If the clock of the master control board and the clock of the output service board card associated with the target screen are non-homologous clocks, the frame pulse generated by the master control CPLD is used as a calibration clock, and the frame pulse generated by the master control CPLD is replaced by the reference clock generated by the FPGA of the output service board card, so that the effect of clock synchronization of all the output service board cards is realized. After the clock synchronization of all the output service boards is realized, the counter display sending module is subjected to reset operation after delay according to the delay parameters.
In one possible embodiment, correcting the clock of the output service board card according to the clock of the main control board includes:
the output service board card generates a local clock;
Resetting a counter module associated with a target screen according to a clock frame synchronizing signal sent by a main control board;
and regenerating the reference clock according to the counter module after the reset operation.
The clock of the master control board and the clock of the output service board card related to the target screen are non-homologous clocks, the clock generated by the master control board and the clock of the output service board card are non-homologous clocks, for example, under the condition that the clock pulse of the master control CPLD is faster than that of the output service board card, each frame can be fast, and after accumulation, a certain frame of second line screen is faster than the first line screen, so that the phenomenon of asynchronism is caused. In the embodiment of the invention, the FPGA on each output service board card is adopted to automatically generate pulse signals, so that the pulse signals replace the pulse signals generated by the main control board. The clock generated by the main control CPLD is used as a calibration clock, after the configuration parameters of the television wall are completed, parameter synchronization is issued, then the output service board cards wait until the clock frame synchronization signals sent by the main control board CPLD arrive, and the counters of all output service board card FPGAs for generating local pulses are cleared, so that the effect of local pulse synchronization of all output service board card FPGAs is achieved.
In a possible embodiment, before step 101, the method further comprises:
determining a synchronous display mode of a target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
if the synchronous display mode is the synchronous mode, performing a reset operation on a counter display module associated with the target screen according to a display frame synchronous signal of the main control board;
if the synchronous display mode is the synchronous delay mode, continuing to determine the delay parameter of the target screen according to the setting position of the target screen.
The screen attribute features of the target screen are determined according to screen materials and other features, and an association relationship between the screen attribute features of the target screen and the synchronous display mode is pre-established, and after the screen attribute features of the target screen are determined, the synchronous display mode for operating the target screen can be determined. For example, when the target screen is an LCD screen, the synchronous display mode may be a synchronous delay mode; when the target screen is a small-spacing LED screen, the synchronous display mode is a synchronous mode, and the synchronous display mode is determined according to a screen display principle determined by screen attribute characteristics.
If the synchronous display mode of the target screen is the synchronous delay mode, the delay parameter of the target screen is determined according to the setting position of the target screen, namely, the delay parameter is issued according to the line number of the target screen, so that the synchronization of all output service boards and all FPGAs is ensured.
Because the power-on time of each output service board card is different, the transmission and display time of each output service board card is also different, and therefore, the problem of out-of-sync caused by screen display can be solved. In the embodiment of the invention, if the synchronous display mode of the target screen is the synchronous mode, the synchronization of the FPGA is realized, firstly, all the output service board FPGA clocks are guaranteed to be homologous clocks, and are uniformly generated by the master control board FPGA; and secondly, the main control board FPGA generates a frame transmission synchronous signal, such as a frame synchronous pulse, and the output service boards associated with all screens perform de-reset on the counter transmission module of each FPGA according to the frame synchronous pulse.
In a possible embodiment, the resetting operation of the counter display module associated with the target screen according to the display frame synchronization signal of the main control board includes:
locking an image display parameter of a target screen;
resetting a counter display sending module associated with a target screen;
and if the frame synchronous signal sent by the main control board is received, performing resetting operation on the counter frame synchronous signal associated with the target screen.
When a television wall is created, the television walls with different resolutions can issue VESA standard video display time sequence signals with corresponding resolutions to an FPGA of an output service board card, namely image display parameters of a target screen; when the signals are stable, the FPGA locks the phase-locked loop, namely the FPGA associated with the target screen locks the image display parameters of the target screen; and at the same time, resetting the counter display module in the FPGA to zero the counter. And then after the FPGA modules of all the output service boards wait until the frame synchronization pulse adjacent to the FPGA of the main control board is generated, the FPGA performs a reset operation on the internal counter display sending module, so that the counter display sending module performs a uniform counting operation, and the effect of synchronous display sending of the FPGA modules of all the output service boards is realized.
According to the embodiment of the invention, the delay parameter of the target screen is determined according to the setting position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronous signal sent by a main control board; and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of all the screen counter display modules is realized through the display frame transmission synchronization signals sent by the main control board, and meanwhile, the problem that the picture display of different lines of display screens is asynchronous when the multi-screen display is performed is solved through the determination of the delay parameters by the screen positions, so that the picture synchronization effect of the television wall is realized, and the applicability is strong.
Example two
Fig. 3 is a flowchart of a control method for multi-screen synchronous display in the second embodiment of the present invention, as shown in fig. 3, the method includes:
configuring a control mode of multi-screen synchronous display on a web interface, for example, configuring a down-command into a synchronous mode or a synchronous delay mode; the client side sends a synchronous command after receiving the configuration of the web interface, the control software of the multi-screen display sends the synchronous command to the driver after receiving the command, and the driver sets relevant parameters according to the command after receiving the command, wherein the parameters comprise delay parameters of each screen and the like. And the FPGA associated with each screen processes according to the related parameters stored in the register, so that synchronous display of multiple screens is realized.
Fig. 4 is a flowchart of a control method of multi-screen synchronous display in synchronous mode. As shown in fig. 4, in the synchronous mode, firstly, the resolution of the television wall needs to be reconfigured according to the output resolution of the display image, and the line and field blanking parameters of the television wall are configured, namely, the television walls with different resolutions can issue VESA standard video display time sequence signals with corresponding resolutions to the FPGA of the output service board card; and after the signals are stable, the FPGA locks the phase-locked loop, namely, the FPGA associated with each screen locks the related display parameters of the target screen. After the parameters are locked, resetting the FPGA counter display module associated with each screen, namely executing counting zero clearing operation, and then after all the output service board FPGA modules wait until the frame synchronization pulse generated by the main control board FPGA arrives, the FPGA carries out resetting operation on the internal counter display module to enable the counter display module to carry out unified counting operation, so that the effect of synchronous display of the FPGAs of all the output service boards is achieved. And after the simultaneous unified counting operation is carried out, generating a transmission line and field blanking parameter, and transmitting and displaying the transmission image according to the parameter, so as to realize the synchronous display effect of the multi-screen picture. Under the synchronous mode, firstly, ensuring that all output service board FPGA clocks are homologous clocks and are uniformly generated by a master control board FPGA; and secondly, the main control board FPGA generates a frame synchronization pulse, and all output boards perform de-reset on the counter display sending module of each FPGA according to the frame synchronization pulse. The problem of asynchronous generation of different sending and displaying time of each output service board card due to different power-on time of each output service board card is solved.
Fig. 5 is a flowchart of a control method for multi-screen synchronous display when the clock of the master control board and the clock of the output service board card associated with each screen are homologous clocks in the synchronous delay mode. As shown in fig. 5, in the synchronous delay mode, when the clock of the main control board and the clock of the output service board associated with each screen are homologous clocks, firstly, software issues delay levels of different lines of VOs (picture output interfaces), and the different delay levels correspond to different delay parameters, wherein each VO is associated with one display screen. In fig. 5, only delay parameters of four lines of screens are illustrated, and so on, which are not described herein again, 16ms is a blanking delay time, and is determined according to the output resolution of the display image.
Each screen corresponds to a register for configuring and storing the delay parameters of the screen and the enabling bits thereof, and then the delay parameters of each screen are configured into the FPGA of the associated different output service boards, and all FPGA parameters are synchronized, so that the operation of the delay enabling position bits is synchronized. After receiving the frame pulse of the adjacent main control board FPGA, the FPGA of each output service board card executes the reset operation of the FPGA counter display module, so that the counter is cleared. And finally, determining the time for performing the reset operation on the corresponding counter display module according to the delay parameters of each screen so as to synchronously display all the screens.
The software issues corresponding configuration commands, namely the sending and displaying delay parameters of each line of VO, according to different lines of VOs. All delay parameters are configured by taking the first line VO as a reference, the first line VO does not delay, and the second line delay is 16ms, and 16ms is because blanking data is contained in a video display time sequence standard of image transmission and display, and after blanking is removed, the effective data display time of one frame of image is 16ms. Line 3 delays 32ms, but since 60 frames are acquired, the time taken for one frame is 16.6ms, and the delay time must be within 16.6ms to be effective, the delay parameter cannot be directly configured to be 32ms from the third line. Because the FPGA can buffer 4 frames of image data, read and write the data one frame later, the FPGA acquires the data according to 60 frames, but the 60 frames are extracted into 30 frames to be processed, and finally the data is sent and displayed again, and the frame is 60 frames. So the 3 rd line VO directly jumps one frame, starts to display from the next frame, delays for 0ms, and so on; line 4 VO, need to skip frame, skip one frame first, then delay 16ms. At this time, all LCD screens are synchronous in visual display effect, and each VO is correspondingly delayed in practice, so that the synchronous display effect of multiple screens is realized. The values of the delay time, the display time and the like can be accurately calculated according to the resolution of the actual display image, and the value in the example is only one example and is a rough value.
Fig. 6 is a flowchart of a control method for multi-screen synchronous display when the clock of the master control board and the clock of the output service board card associated with each screen are non-homologous clocks in the synchronous delay mode. As shown in fig. 6, in the synchronous delay mode, when the clock of the main control board and the clock of the output service board associated with each screen are non-homologous clocks, the CPLD pulse of the main control board is faster than VO0, and after accumulation, a certain frame VO1 is faster than VO0, resulting in the asynchronous phenomenon of VO display of different lines. Because the clock is a non-homologous clock, the synchronous effect cannot be achieved simply according to the delay parameters, under the condition, after the software issues delay grades of VOs of different rows, the configuration of the delay parameters and the reset operation of the FPGA counter display module are carried out, and at the same time, the frame pulse generated by the CPLD of the main control board is used as a calibration clock, and the FPGA of the output service board automatically generates a reference clock to replace the frame pulse generated by the CPLD of the main control board, so that the clock synchronous effect of all the output boards is achieved. Illustratively, each output board comprises an FPGA on the expansion cabinet that generates a pulse signal by itself, so that the pulse signal replaces the pulse signal generated by the CPLD to perform the frame skipping operation. When the configuration parameters of the television wall are completed, parameter synchronization is issued, then the counter of local pulses generated by all output board FPGAs is cleared after the adjacent frame pulses transmitted by the CPLD of the main control board arrive, so that the counter achieves the effect of local pulse synchronization of all FPGAs, and the effect of synchronous delay can be achieved. On the basis, the time for performing the reset operation on each counter display module is determined according to the delay parameter so as to synchronously display all screens.
The embodiment of the invention can realize the picture synchronization effect under the homologous clock or the non-homologous clock, and has strong applicability and good synchronization effect. Corresponding display delay parameters and frame skip numbers are configured for the FPGA corresponding to the different lines of screens, so that the picture synchronization effect among the different lines of screens of the whole television wall is achieved, the delay of the different lines of screens of the television wall is controlled by the FPGA, the reset and reset time of the display module of the internal counter is controlled by the FPGA, the purpose of carrying out delay display on the associated different screens by the different FPGA is achieved, and the synchronization effect is safe and reliable and the efficiency is high.
Example III
Fig. 7 is a schematic structural diagram of a control device for multi-screen synchronous display in the third embodiment of the present invention, where the present embodiment is applicable to a case of implementing display synchronous control on a plurality of display screens controlled by a jigsaw device, where all the screens are controlled and displayed by the same main control board. As shown in fig. 7, the apparatus includes:
a delay parameter determining module 710, configured to determine a delay parameter of a target screen according to a setting position of the target screen;
the send display reset module 720 is configured to reset the counter send display module associated with the target screen according to the send display frame synchronization signal sent by the main control board;
And the send display and reset module 730 is configured to determine, according to the delay parameter, a time for performing a reset operation on the counter send display module, so as to perform synchronous display of all the screens.
According to the embodiment of the invention, the delay parameter of the target screen is determined according to the setting position of the target screen; resetting a counter display sending module associated with a target screen according to a display sending frame synchronous signal sent by a main control board; and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens. The reset synchronization of all the screen counter display modules is realized through the display frame transmission synchronization signals sent by the main control board, and meanwhile, the problem that the picture display of different lines of display screens is asynchronous when the multi-screen display is performed is solved through the determination of the delay parameters by the screen positions, so that the picture synchronization effect of the television wall is realized, and the applicability is strong.
Optionally, the delay parameter is determined according to a blanking delay time; the blanking delay time is the delay time difference between adjacent line screens;
correspondingly, the sending display and decoding reset module is specifically used for:
determining a comparison result of the delay parameter and a preset single frame acquisition time; the preset single-frame acquisition time is determined according to the resolution of the display image;
If the delay parameter is smaller than the preset single frame acquisition time, delaying the image display of the target screen according to the delay parameter, and then executing a reset operation of the counter display sending module;
if the delay parameter is greater than or equal to the preset single frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and then executing the reset operation of the counter display sending module.
Optionally, the blanking delay time is determined according to the following formula:
blanking delay time = horizontal total pixel (vertical total pixel-leading edge parameter-sync width parameter-trailing edge parameter)/clock parameter;
wherein, the horizontal total pixel=horizontal effective pixel+horizontal blanking pixel, and the vertical total pixel=vertical effective pixel+vertical blanking pixel; the horizontal effective pixels, the horizontal blanking pixels, the vertical effective pixels and the vertical blanking pixels are determined according to the resolution of the display image; and the front edge parameter, the synchronous width parameter, the back edge parameter and the clock parameter are determined according to the time sequence characteristics of the display image.
Optionally, the device further includes a homologous clock judging module, configured to, before determining, according to the delay parameter, an opportunity to perform a reset operation on the counter sending and displaying module, include:
the judging unit is used for determining whether the clock of the main control board and the clock of the output service board card associated with the target screen are homologous clocks or not;
the clock correction unit is used for correcting the clock of the output service board card according to the clock of the main control board if the clock is not the homologous clock, and then determining the time for resetting the counter display module according to the delay parameter;
and the display and reset sending unit is used for executing the moment of performing the reset operation on the counter display module according to the delay parameter if the counter display module is the same source clock.
Optionally, the clock correction unit is specifically configured to:
the output service board card generates a local clock;
resetting a counter module associated with the target screen according to a clock frame synchronizing signal sent by a main control board;
and regenerating the reference clock according to the counter module after the reset operation.
Optionally, the method further includes a mode selection module, configured to, before determining the delay parameter of the target screen according to the setting position of the target screen, include:
A mode determining unit configured to determine a synchronous display mode of the target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
the synchronous mode unit is used for performing a reset operation on the counter display module associated with the target screen according to the display frame synchronous signal of the main control board if the synchronous display mode is the synchronous mode;
and the synchronous delay mode unit is used for continuously executing the delay parameter determination of the target screen according to the setting position of the target screen if the synchronous display mode is the synchronous delay mode.
Optionally, the synchronization mode unit includes:
locking an image display parameter of a target screen;
resetting the counter display module associated with the target screen;
and if the frame sending and displaying synchronous signal sent by the main control board is received, performing resetting operation on the counter sending and displaying module associated with the target screen.
The control device for multi-screen synchronous display provided by the embodiment of the invention can execute the control method for multi-screen synchronous display provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the control method for multi-screen synchronous display.
Example IV
Fig. 8 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention. Fig. 8 illustrates a block diagram of an exemplary electronic device 12 suitable for use in implementing embodiments of the present invention. The electronic device 12 shown in fig. 8 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.
As shown in fig. 8, the electronic device 12 is in the form of a general purpose computing device. Components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory device 28, a bus 18 that connects the various system components, including the system memory device 28 and the processing unit 16.
Bus 18 represents one or more of several types of bus structures, including a memory device bus or memory device controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Electronic device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by electronic device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
The system storage 28 may include computer system readable media in the form of volatile memory such as Random Access Memory (RAM) 30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 8, commonly referred to as a "hard disk drive"). Although not shown in fig. 8, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. The storage device 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in storage 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods of the embodiments described herein.
The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the device 12, and/or any devices (e.g., network card, modem, etc.) that enable the device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Also, the electronic device 12 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through a network adapter 20. As shown in fig. 8, the network adapter 20 communicates with other modules of the electronic device 12 over the bus 18. It should be appreciated that although not shown in fig. 8, other hardware and/or software modules may be used in connection with electronic device 12, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The processing unit 16 executes various functional applications and data processing by running a program stored in the system storage device 28, for example, to implement a control method for multi-screen synchronous display provided by the embodiment of the present invention, where all screens are controlled and displayed by the same main control board, including:
determining delay parameters of a target screen according to the setting position of the target screen;
resetting a counter display sending module associated with the target screen according to a display sending frame synchronous signal sent by a main control board;
and determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens.
Example five
The fifth embodiment of the present invention further provides a computer readable storage medium, on which a computer program is stored, where the program when executed by a processor implements a method for controlling multi-screen synchronous display provided by the present invention, where all screens are controlled and displayed by the same main control board, including:
determining delay parameters of a target screen according to the setting position of the target screen;
resetting a counter display sending module associated with the target screen according to a display sending frame synchronous signal sent by a main control board;
And determining the time for performing the reset operation on the counter display module according to the delay parameter so as to synchronously display all screens.
The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present invention may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A control method for multi-screen synchronous display is characterized in that all screens are controlled and displayed by the same main control board, and the control method comprises the following steps:
determining delay parameters of a target screen according to the setting position of the target screen;
resetting a counter display sending module associated with the target screen according to a display sending frame synchronous signal sent by a main control board;
determining a comparison result of the delay parameter and a preset single frame acquisition time according to the delay parameter, and determining the time for performing a resetting operation on the counter display module according to the comparison result so as to synchronously display all screens; the preset single frame acquisition time is determined according to the resolution of the display image.
2. The method of claim 1, wherein the delay parameter is determined based on a blanking delay time; the blanking delay time is the delay time difference between adjacent line screens;
correspondingly, the determining the time for performing the reset operation on the counter sending and displaying module according to the comparison result includes:
if the delay parameter is smaller than the preset single frame acquisition time, delaying the image display of the target screen according to the delay parameter, and then executing a reset operation of the counter display sending module;
if the delay parameter is greater than or equal to the preset single frame acquisition time, determining a frame skipping parameter and a delay allowance parameter according to the delay parameter, delaying the image display of the target screen according to the frame skipping parameter and the delay allowance parameter, and then executing the reset operation of the counter display sending module.
3. The method of claim 2, wherein the blanking delay time is determined according to the formula:
blanking delay time = horizontal total pixel (vertical total pixel-leading edge parameter-sync width parameter-trailing edge parameter)/clock parameter;
Wherein, the horizontal total pixel=horizontal effective pixel+horizontal blanking pixel, and the vertical total pixel=vertical effective pixel+vertical blanking pixel; the horizontal effective pixels, the horizontal blanking pixels, the vertical effective pixels and the vertical blanking pixels are determined according to the resolution of the display image; and the front edge parameter, the synchronous width parameter, the back edge parameter and the clock parameter are determined according to the time sequence characteristics of the display image.
4. The method of claim 1, wherein prior to determining the timing for a de-reset operation of the counter display module based on the delay parameter, the method further comprises:
determining whether the clock of the master control board and the clock of the output service board card associated with the target screen are homologous clocks;
if the clock is not the homologous clock, correcting the clock of the output service board card according to the clock of the main control board, and then determining the time for performing the reset operation on the counter display module according to the delay parameter;
and if the clock is the homologous clock, executing the time for performing the reset operation on the counter display module according to the delay parameter.
5. The method of claim 4, wherein correcting the clock of the output service card according to the clock of the master control board comprises:
The output service board card generates a local clock;
resetting a counter module associated with the target screen according to a clock frame synchronizing signal sent by a main control board;
and regenerating the reference clock according to the counter module after the reset operation.
6. The method of claim 1, wherein prior to determining the delay parameter for the target screen based on the set position of the target screen, the method further comprises:
determining a synchronous display mode of the target screen; the synchronous display mode is determined according to the screen attribute characteristics of the target screen;
if the synchronous display mode is the synchronous mode, performing a reset operation on a counter display module associated with the target screen according to a display frame synchronous signal of the main control board;
if the synchronous display mode is a synchronous delay mode, continuing to execute the delay parameter of the target screen according to the setting position of the target screen.
7. The method of claim 6, wherein the performing a reset operation on the counter send module associated with the target screen according to the send frame synchronization signal of the main control board comprises:
locking an image display parameter of a target screen;
Resetting the counter display module associated with the target screen;
and if the frame sending and displaying synchronous signal sent by the main control board is received, performing resetting operation on the counter sending and displaying module associated with the target screen.
8. A control device for multi-screen synchronous display is characterized in that all screens are controlled and displayed by the same main control board, and the control device comprises:
the delay parameter determining module is used for determining delay parameters of the target screen according to the setting position of the target screen;
the display sending and resetting module is used for resetting the counter display sending module associated with the target screen according to the display sending frame synchronizing signal sent by the main control board;
the display and reset sending module is used for determining a comparison result of the delay parameter and the preset single frame acquisition time according to the delay parameter, and determining the time for performing the reset operation on the counter display sending module according to the comparison result so as to synchronously display all screens; the preset single frame acquisition time is determined according to the resolution of the display image.
9. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs,
The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of controlling multi-screen synchronous display of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements a control method of multi-screen synchronous display according to any one of claims 1 to 7.
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