CN114241970A - Display panel and display device - Google Patents
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- CN114241970A CN114241970A CN202111587178.7A CN202111587178A CN114241970A CN 114241970 A CN114241970 A CN 114241970A CN 202111587178 A CN202111587178 A CN 202111587178A CN 114241970 A CN114241970 A CN 114241970A
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- 230000008878 coupling Effects 0.000 description 35
- 238000010168 coupling process Methods 0.000 description 35
- 238000005859 coupling reaction Methods 0.000 description 35
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- 238000010586 diagram Methods 0.000 description 20
- 230000000694 effects Effects 0.000 description 19
- 230000007704 transition Effects 0.000 description 18
- 230000003071 parasitic effect Effects 0.000 description 10
- 230000004044 response Effects 0.000 description 6
- 230000001808 coupling effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 235000019557 luminance Nutrition 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 101100420795 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sck1 gene Proteins 0.000 description 1
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 1
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- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel includes a first scan circuit for generating a light emission control signal; a light emission control signal line connected to a signal output terminal of the first scanning circuit; a light emitting clock signal line connected to a clock signal input terminal of the first scanning circuit, the light emitting clock signal line being configured to transmit a light emitting clock signal to the clock signal input terminal of the first scanning circuit; the light-emitting clock signal wire comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross-sectional area of one of the first wire and the second wire is smaller than that of the other wire so as to prolong the jump time of the light-emitting control signal. The technical scheme provided by the embodiment improves the consistency of the brightness of the light emitting elements of different pixel circuits.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, people have higher and higher requirements on display panels. The prior display panel has mura defect during displaying, which affects the display effect of the display device.
Disclosure of Invention
The embodiment of the invention provides a display device, which aims to solve the problem that the display mura is bad and the display effect of the display device is influenced.
In order to realize the technical problem, the invention adopts the following technical scheme:
an embodiment of the present invention provides a display device, including:
in a first aspect, an embodiment of the present invention provides a display panel, including:
a first scanning circuit for generating a light emission control signal;
a light emission control signal line connected to a signal output terminal of the first scanning circuit, the light emission control signal line being used for transmitting a light emission control signal;
a light emitting clock signal line connected to a clock signal input terminal of the first scanning circuit, the light emitting clock signal line being configured to transmit a light emitting clock signal to the clock signal input terminal of the first scanning circuit;
the light-emitting clock signal wire comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross-sectional area of one of the first wire and the second wire is smaller than that of the other wire so as to prolong the jump time of the light-emitting control signal.
Optionally, one of the first trace and the second trace includes a serpentine trace, and the other includes a linear trace;
optionally, the first trace includes a serpentine trace, and the second trace includes a linear trace.
Optionally, the cross-sectional area of the first trace is smaller than the cross-sectional area of the second trace.
Optionally, the display panel is divided into a display area and a non-display area, the non-display area at least partially surrounds the display area, and the non-display area includes a connection terminal setting area;
the light-emitting clock signal line is positioned in the non-display area;
the first routing is located in the connecting terminal setting area.
Optionally, the non-display area further includes a first frame area and a second frame area, the first frame area and the second frame area are arranged oppositely, and the connection terminal setting area is adjacent to the first frame area and the second frame area;
the second routing of the light-emitting clock signal wire is arranged in the first frame area and/or the second frame area.
Optionally, the serpentine trace includes:
the device comprises a plurality of clip sections, a plurality of clip sections and a plurality of connecting sections, wherein each clip section comprises a first edge, a second edge and a third edge, the first edge and the second edge are arranged oppositely, and the third edge is respectively connected with the first edge and the second edge;
and the second edge of the Nth square-shaped section is connected with the first edge of the (N + 1) th square-shaped section through the connecting section, wherein N is an integer greater than or equal to 1.
Optionally, the cross-sectional area of one of the first trace and the second trace is smaller than the cross-sectional area of the other trace, and the cross-sectional area of one of the first trace and the second trace includes at least one of the following: one of the first and second traces has a width smaller than that of the other trace, and one of the first and second traces has a thickness smaller than that of the other trace.
Optionally, when the width of one of the first trace and the second trace is smaller than the width of the other trace, the width range of the narrower trace of the first trace and the second trace includes: 0.01-10 μm.
Optionally, under the condition that the thickness of one of the first trace and the second trace is smaller than that of the other trace, the thickness range of the trace with the smaller thickness in the first trace and the second trace includes: 0.01-10 μm.
Optionally, the resistance of the light emitting clock signal line is less than or equal to 10k Ω.
In a second aspect, an embodiment of the present invention provides a display panel, including:
a first scanning circuit for generating a light emission control signal;
a light emission control signal line connected to a signal output terminal of the first scanning circuit, the light emission control signal line being used for transmitting a light emission control signal;
a light emitting clock signal line connected to a clock signal input terminal of the first scanning circuit, the light emitting clock signal line being configured to transmit a light emitting clock signal to the clock signal input terminal of the first scanning circuit;
the light emitting clock signal line comprises a snake-shaped wiring, and the snake-shaped wiring is used for prolonging the jump time of the light emitting control signal.
In a third aspect, an embodiment of the present invention provides a display device, including the display panel set forth in any of the first aspects; alternatively, the display panel of the second aspect is proposed.
According to the display panel provided by the embodiment of the invention, the luminous clock signal line comprises the first wire and the second wire, the cross sectional area of one wire of the first wire and the second wire is smaller than that of the other wire, and the resistance of the luminous clock signal line is increased. Since the delay of the light emission clock signal is increased by increasing the resistance of the light emission clock signal line, the delay of the light emission clock signal is increased, and the response speed of the corresponding first scan circuit is slowed down, thereby increasing the transition time of the light emission control signal. The light emitting clock signal transmitted by the light emitting clock signal line can prolong the transition time of the light emitting control signal, so that the charge amount in the unit time of the light emitting control signal is reduced. The quantity of electric charges in the unit time of the light-emitting control signal is reduced, so that the coupling capacitance between the source of the driving transistor and the light-emitting control signal line and the coupling capacitance between the drain of the driving transistor and the light-emitting control signal line are reduced, and the difference between the grid voltages of the driving transistors of different pixel circuits caused by the influence of parasitic capacitance is reduced. The arrangement improves the consistency of the brightness of the light emitting elements of different pixel circuits, and improves the display effect of the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another display panel structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another display panel structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a serpentine trace according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another display panel structure according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a display panel according to another embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the display panel in the prior art has poor display mura, which affects the display effect of the display panel.
Based on the above technical problem, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. With reference to fig. 1 and 2, the display panel includes a plurality of light emitting cells including a light emitting element D1 and its corresponding pixel circuit 1. The display panel further includes a first power supply signal line ELVDD, a second power supply signal line ELVSS, and an initialization signal line Vref. Each of the pixel circuits 1 is connected to the first power supply signal line ELVDD, the second power supply signal line ELVSS, and the initialization signal line Vref, respectively. In each light emitting unit, the pixel circuit 1 includes a plurality of thin film transistors and a storage capacitor, the thin film transistors may include a driving transistor T1 and a switching transistor, the first power supply signal line ELVDD is connected to a first terminal of the driving transistor T1, a second terminal of the driving transistor T1 is connected to an anode of the light emitting element D1, and a cathode of the light emitting element D1 is connected to the second power supply signal line ELVSS. The driving transistor T1 can generate a driving current to drive the light emitting element D1 connected to the pixel circuit 1 to emit light, and the switching transistor mainly performs a switching function. The first power source signal line ELVDD and the second power source signal line ELVSS serve as power sources for generating the driving current for the driving transistor T1, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light.
Referring to fig. 1, the display panel may further include a plurality of Scan signal lines Scan 1-Scan n, a plurality of data signal lines Vdata 1-Vdata n, a plurality of emission control signal lines EM 1-EM n, and a connection terminal 300, the pixel circuit 1 is disposed in a region defined by the Scan signal lines Scan crossing the data signal lines Vdata, the scanning signal is input to the corresponding pixel circuit 1 through the scanning signal line Scan, the pixel circuit 1 is communicated with the data signal line Vdata correspondingly and electrically connected with the pixel circuit under the action of the scanning signal input by the scanning signal line Scan electrically connected with the pixel circuit, the connecting terminal 300 can be connected with a driving chip, the driving chip is connected with the connecting terminal 300, a data signal is input to the corresponding pixel circuit 1 through the data signal line Vdata, and the voltage of the data signal determines the emission luminance of the light-emitting element D1, that is, the display gray scale of the light-emitting element D1, in accordance with the driving voltage. It is to be noted that the driving transistor, the switching transistor, and the storage capacitor may form the pixel circuit 1 in various forms in various connection relationships. The pixel circuit 1 shown in fig. 2 is only an example, and may be other types of pixel circuits, such as a 3T1C pixel circuit, a 7T1C pixel circuit, an 8T2C pixel circuit, and the like, where T represents a transistor and C represents a capacitor. Fig. 2 exemplarily shows a case of the 7T1C pixel circuit, and does not limit the pixel circuit 1.
Referring to fig. 1 and 2, the first power signal line ELVDD may be used to transmit a first power signal, and the second power signal line ELVSS may be used to transmit a second power signal. The voltage on the first power supply signal line ELVDD is generally a high level voltage, and the voltage on the second power supply signal line ELVSS is generally a low level voltage. In the light emitting period, the first power signal on the first power signal line ELVDD is applied to the first electrode of the driving transistor T1, the second power signal on the second power signal line ELVSS is applied to the second electrode of the light emitting element D1, for example, the second electrode is a cathode, and the first power signal and the second power signal serve as a power source for generating the driving current by the driving transistor T1, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light. The first power supply signal line ELVDD may be a signal line directly connected to one pole (e.g., a drain or a source) of the driving transistor T1 in the pixel circuit 1, or a signal line indirectly connected to one pole of the driving transistor T1 in the pixel circuit 1 through a switching transistor (e.g., a light emission control transistor), and the second power supply signal line ELVSS may be a signal line connected to a cathode of the light emitting element D1. The initialization signal line Vref may be used to transmit an initialization signal to the pixel circuit 1.
With reference to fig. 1 and 2, the display panel may include a plurality of pixel circuits 1, the pixel circuits 1 being configured to drive the light emitting elements D1 to emit light, the pixel circuits 1 controlling the light emission luminance of the light emitting elements D1 by controlling the driving current flowing through the light emitting elements D1.
Referring to fig. 2, the pixel circuit provided by the embodiment of the invention may correspond to an embodied circuit structure of the pixel circuit 1 in the display panel shown in fig. 1, such as a 7T1C pixel circuit. With reference to fig. 1 and 2, the pixel circuit 1 includes a driving transistor T1, a first initialization transistor T4, a second initialization transistor T7, a third transistor T2, a fourth transistor T5, a fifth transistor T6, a sixth transistor T3, and a storage capacitor C1. Fig. 2 exemplarily shows a case where the sixth transistor T3 is a double-gate transistor including the transistor T3-1 and the transistor T3-2, and the first initialization transistor T4 is a double-gate transistor including the transistor T4-1 and the transistor T4-2.
In the initialization stage, the Scan signal inputted from the first Scan signal line Scan1 may control the first initialization transistor T4 to be turned on, so as to write the initialization signal inputted from the initialization signal line Vref into the storage capacitor C1 and the gate of the driving transistor T1.
In the data writing phase, the Scan signal inputted from the third Scan signal line Scan3 may control the second initialization transistor T7 to be turned on to transmit the initialization signal inputted from the initialization signal line Vref to the anode of the light emitting element D1, so as to initialize the anode of the light emitting element D1. The Scan signal inputted from the second Scan signal line Scan2 may control the third transistor T2 and the sixth transistor T3 to be turned on to write the data voltage signal inputted from the data voltage signal line Vdata into the gate of the driving transistor T1 and to charge the storage capacitor C1.
In the light emitting phase, the light emitting control signal inputted from the light emitting control signal line EM may control the fourth transistor T5 and the fifth transistor T6 to be turned on, and the first power signal and the second power signal serve as power for the driving transistor T1 to generate the driving current, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light.
Since the coupling capacitance C2 exists between the source and the gate of the driving transistor T1 in the pixel circuit 1, the coupling capacitance C3 exists between the drain and the gate of the driving transistor T1, the coupling capacitance C4 exists between the source of the driving transistor T1 and the emission control signal line EM, and the coupling capacitance C5 exists between the drain of the driving transistor T1 and the emission control signal line EM. The coupling capacitor C4 existing between the source of the driving transistor T1 and the emission control signal line EM is a parasitic capacitor, and the coupling capacitor C5 existing between the drain of the driving transistor T1 and the emission control signal line EM is a parasitic capacitor.
Due to process fluctuations, the coupling capacitance C4 existing between the source of the driving transistor T1 and the emission control signal line EM and the coupling capacitance C5 existing between the drain of the driving transistor T1 and the emission control signal line EM are also different for different pixel circuits 1. Due to the variation of the gate voltage of the driving transistor T1 caused by the coupling effect of the capacitor, the coupling capacitor C4 between the source of the driving transistor T1 and the emission control signal line EM of different pixel circuits 1 is different from the coupling capacitor C5 between the drain of the driving transistor T1 and the emission control signal line EM, the gate voltages of the driving transistors T1 of different pixel circuits 1 are different, and the light emitting luminances of different light emitting elements D1 are different, so that the display panel has the defects of poor display mura, which affects the display effect of the display panel.
Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention. With reference to fig. 1 to fig. 3, the display panel according to the embodiment of the invention includes a first scan circuit 10, where the first scan circuit 10 is configured to generate a light-emitting control signal; a light emission control signal line EM connected to a signal output terminal EM _ out of the first scan circuit 10, the light emission control signal line EM being used to transmit a light emission control signal; a light emission clock signal line ECK connected to a clock signal input terminal CLK of the first scan circuit 10, the light emission clock signal line ECK being used to transmit a light emission clock signal to the clock signal input terminal CLK of the first scan circuit 10; the light-emitting clock signal line ECK includes a first trace 101 and a second trace 102, an input end of the second trace 102 is connected to a first end of the first trace 101, an output end of the second trace 102 is connected to a clock signal input end CLK of the first scan circuit 10, and a cross-sectional area of one of the first trace 101 and the second trace 102 is smaller than a cross-sectional area of the other trace, so as to prolong a transition time of the light-emitting control signal.
Specifically, the light emission clock signal line ECK is connected to a clock signal input terminal CLK of the first scan circuit 10, the first scan circuit 10 generates a light emission control signal according to the light emission clock signal transmitted through the light emission clock signal line ECK, and transmits the light emission control signal to the light emission control signal line EM through a signal output terminal EM _ out of the first scan circuit 10, the light emission clock signal may control a transition speed of the light emission control signal, and the light emission control signal line EM transmits the light emission control signal to the pixel circuit 1. The light emission control signal inputted from the light emission control signal line EM may control the fourth transistor T5 and the fifth transistor T6 of the pixel circuit 1 to be turned on, and the first power signal line ELVDD and the second power signal line ELVSS as a power source for generating the driving current by the driving transistor T1, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light. The display panel may include a plurality of light-emitting clock signal lines ECK, and fig. 3 exemplarily shows a case where the display panel includes two light-emitting clock signal lines ECK1 and ECK 2.
The input end of the second trace 102 is connected to the first end of the first trace 101, the output end of the second trace 102 is connected to the clock signal input end CLK of the first scan circuit 10, the second end of the first trace 101 is connected to the connection terminal 300, and the driver chip transmits the light emitting clock signal to the clock signal input end CLK of the first scan circuit 10 through the first trace 101 and the second trace 102 via the connection terminal 300.
One of the first trace 101 and the second trace 102 has a cross-sectional area smaller than that of the other trace, increasing the resistance of the light-emitting clock signal line ECK. Since the resistance of the emission clock signal line ECK is increased, the delay of the emission clock signal is increased. The delay of the light emission clock signal increases and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light emission control signal. The light emission clock signal extends the transition time of the light emission control signal, so that the amount of electric charge per unit time of the light emission control signal transmitted from the light emission control signal line EM becomes small. Since the coupling capacitor has a function of passing high frequency and low frequency, the amount of electric charge per unit time of the light emission control signal becomes small, and the coupling effect of the capacitor can be weakened, thereby reducing the coupling capacitor C4 existing between the source of the driving transistor T1 and the light emission control signal line EM and the coupling capacitor C5 existing between the drain of the driving transistor T1 and the light emission control signal line EM.
The coupling capacitance C4 between the source of the driving transistor T1 of the pixel circuit 1 and the emission control signal line EM is reduced, so that the difference between the coupling capacitances C4 between the source of the driving transistor T1 of different pixel circuits 1 and the emission control signal line EM becomes small. The coupling capacitor C5 between the drain of the smaller driving transistor T1 and the light-emitting control signal line EM makes the difference between the drain of the driving transistor T1 of different pixel circuits 1 and the coupling capacitor C5 between the light-emitting control signal line EM smaller, so that the influence of the parasitic capacitance on the difference between the gate voltages of the driving transistors T1 of different pixel circuits 1 is reduced, the consistency of the light-emitting brightness of the light-emitting elements D1 of different pixel circuits 1 is improved, and the display effect of the display panel is improved.
The display panel provided by the embodiment includes the first wire and the second wire by arranging the light-emitting clock signal line, and the cross-sectional area of one of the first wire and the second wire is smaller than that of the other wire, so that the resistance of the light-emitting clock signal line is increased. Since the delay of the light emission clock signal is increased by increasing the resistance of the light emission clock signal line, the delay of the light emission clock signal is increased, and the response speed of the corresponding first scan circuit is slowed down, thereby increasing the transition time of the light emission control signal. The light emitting clock signal transmitted by the light emitting clock signal line can prolong the transition time of the light emitting control signal, so that the charge amount in the unit time of the light emitting control signal is reduced. The quantity of electric charges in the unit time of the light-emitting control signal is reduced, so that the coupling capacitance between the source of the driving transistor and the light-emitting control signal line and the coupling capacitance between the drain of the driving transistor and the light-emitting control signal line are reduced, and the difference between the grid voltages of the driving transistors of different pixel circuits caused by the influence of parasitic capacitance is reduced. The arrangement improves the consistency of the brightness of the light emitting elements of different pixel circuits, and improves the display effect of the display panel.
Optionally, fig. 4 is a schematic structural diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, with reference to fig. 3 and 4, one of the first trace 101 and the second trace 102 includes a serpentine trace, and the other includes a linear trace. It should be noted that fig. 3 and 4 only exemplarily show the case where the first trace 101 includes a serpentine trace and the second trace 102 includes a straight trace, which is not limited in any way.
Specifically, one of the first trace 101 and the second trace 102 includes a serpentine trace, and the other includes a linear trace. The serpentine trace may increase the length of the emission clock signal line ECK, and thus the arrangement may further increase the resistance of the emission clock signal line ECK. Since the resistance of the emission clock signal line ECK is increased, the delay of the emission clock signal is increased. The delay of the light emission clock signal increases and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light emission control signal. The light emission clock signal extends the transition time of the light emission control signal, so that the amount of electric charge per unit time of the light emission control signal transmitted from the light emission control signal line EM becomes small. Since the coupling capacitor has a function of passing high frequency and low frequency, the amount of electric charge per unit time of the light emission control signal becomes small, and the coupling effect of the capacitor can be weakened, thereby reducing the coupling capacitor C4 existing between the source of the driving transistor T1 and the light emission control signal line EM and the coupling capacitor C5 existing between the drain of the driving transistor T1 and the light emission control signal line EM.
The coupling capacitance C4 between the source of the driving transistor T1 of the pixel circuit 1 and the light emission control signal line EM is reduced, so that the difference between the source of the driving transistor T1 of different pixel circuits 1 and the coupling capacitance C4 between the light emission control signal line EM is reduced, the influence of the parasitic capacitance on the difference between the gate voltages of the driving transistors T1 of different pixel circuits 1 is reduced, the consistency of the light emission brightness of the light emitting elements D1 of different pixel circuits 1 is further improved, and the display effect of the display panel is improved.
Optionally, on the basis of the above embodiment, with reference to fig. 4, the first trace 101 includes a serpentine trace S, and the second trace 102 includes a linear trace L.
Specifically, the first trace 101 can include a serpentine trace S, and the first trace 101 can include a serpentine trace S and a linear trace L. The second trace 102 includes a linear trace L, wherein the linear trace L may be a combination of one or more segments, and is not limited herein. The second trace 102 is used for stably outputting the light emitting clock signal transmitted by the first trace 101 to the clock signal input terminal CLK of the first scan circuit 10, so as to prolong the transition time of the rising edge and the falling edge of the light emitting control signal.
Through setting up first line 101 and including snakelike line S, second line 102 is walked including straight line shape and is walked line L, because the resistance of second line 102 of walking including straight line shape line L is less, the resistance of first line 101 of walking including snakelike line S is great, can make the luminous clock signal of being exported by driver chip increase luminous clock signal' S delay behind the great first line 101 of walking of resistance. The light emitting clock signal with increased delay is output to the clock signal input terminal of the first scan circuit 10 through the second trace 102 with smaller resistance. The second trace 102 with smaller resistance makes the light emitting clock signals received by the first scanning circuits 10 corresponding to the pixel circuits 1 in different rows as the same as possible, so that the light emitting control signals between the pixel circuits 1 in different rows are as consistent as possible. The second trace 102 with a smaller resistance can reduce the voltage drop between different output terminals, so that the light-emitting clock signal output to the clock signal input terminal of each first scanning circuit 10 is more stable, the transition time of the rising edge and the falling edge of the light-emitting control signal is prolonged, the light-emitting control signals between the pixel circuits 1 in different rows can be consistent as much as possible, and the display effect of the display panel is further improved.
Optionally, on the basis of the foregoing embodiment, a cross-sectional area of one of the first trace and the second trace, which is smaller than a cross-sectional area of the other trace, includes at least one of: one of the first and second traces has a width smaller than that of the other trace, and one of the first and second traces has a thickness smaller than that of the other trace.
It should be noted that the thickness direction of the first trace and the second trace refers to the thickness direction of the display panel.
Optionally, in a case that a width of one of the first trace and the second trace is smaller than a width of the other trace, with continuing reference to fig. 1 or fig. 4, the width of the first trace 101 is smaller than the width of the second trace 102. The thicknesses of the first trace 101 and the second trace 102 may be the same or different, and are not limited herein.
Specifically, the width of the first trace 101 may be set to be smaller than the width of the second trace 102, so that on one hand, the resistance of the first trace 101 is further increased, and the delay of the light-emitting clock signal is increased due to the increase of the resistance of the light-emitting clock signal line ECK. The delay of the light emission clock signal increases and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light emission control signal. The light emission clock signal transmitted by the light emission clock signal line ECK can make the transition time of the light emission control signal longer, so that the amount of electric charge per unit time of the light emission control signal is smaller. Therefore, coupling capacitance between the light-emission control signal lines EM 1 to EM n and the source of the driving transistor and coupling capacitance between the light-emission control signal lines EM 1 to EM n and the drain of the driving transistor are further reduced, and the difference between the gate voltages of the driving transistors of different pixel circuits caused by the influence of parasitic capacitance is further reduced. The arrangement improves the consistency of the brightness of the light emitting elements of different pixel circuits, and improves the display effect of the display panel.
On the other hand, the second trace 102 is set to have a larger width, so that the resistance of the second trace 102 of the light-emitting clock signal line ECK can be further reduced, and the second trace 102 having a smaller resistance makes the voltage drop of the light-emitting clock signal received by the first scanning circuit 10 corresponding to the pixel circuits 1 in different rows smaller, so that the difference between the light-emitting clock signals received by the first scanning circuits 10 corresponding to the pixel circuits 1 in different rows is smaller, and the light-emitting control signals between the pixel circuits 1 in different rows are made to be as consistent as possible. The second trace 102 with a smaller resistance can reduce the voltage drop between different output ends, so that the light emitting clock signal output to the clock signal input end of each first scanning circuit 10 is more stable, and the light emitting control signals output by each first scanning circuit 10 connected to the second trace 102 are as consistent as possible, thereby further improving the consistency of the light emitting brightness of the light emitting elements of different pixel circuits and improving the display effect of the display panel.
Optionally, under the condition that the thickness of one of the first trace and the second trace is smaller than that of the other trace, the thickness range of the trace with the smaller thickness in the first trace and the second trace includes: 0.01-10 μm. The widths of the first trace and the second trace may be the same or different, and are not limited herein.
Optionally, if the width of one of the first trace and the second trace is smaller than the width of the other trace, and the thickness of the one of the first trace and the second trace is smaller than the thickness of the other trace, in this case, the trace with the smaller width and the trace with the smaller thickness may be the same trace, and the trace with the larger width and the trace with the larger thickness may be the other trace.
Optionally, fig. 5 is a schematic structural diagram of another display panel provided in an embodiment of the present invention. On the basis of the above embodiments, with reference to fig. 1, fig. 3 and fig. 5, the display panel provided in the embodiment of the present invention is divided into a display area 100 and a non-display area 200, the non-display area 200 at least partially surrounds the display area 100, and the non-display area 200 includes a connection terminal setting area 203; the light emitting clock signal line is located in the non-display region 200; the first trace 101 is located in the connection terminal setting area 203.
Specifically, the light-emitting clock signal line is located in the non-display area 200, so that the light-emitting clock signal transmitted by the light-emitting clock signal line can be conveniently transmitted from the non-display area 200 to the display area 100, the light-emitting clock signal line is a metal wiring line, and the light-emitting clock signal line is provided with the non-display area 200, so that the light emitted by the light-emitting element can be prevented from being reflected by the metal wiring line, and the display effect of the display panel is further improved. The first trace 101 is disposed in the connection terminal disposition area 203, for example, taking the light emitting clock signal line includes the first light emitting clock signal line ECK1 as an example, a resistor may be added to the first light emitting clock signal line ECK1 near the connection terminal disposition area 203, so that the signals transmitted by the second trace 102 after the first light emitting clock signal line ECK1 passes through the first trace 101 are consistent, and the display uniformity of the display panel is further improved. Note that fig. 5 exemplarily shows a case where the emission clock signal line includes the first emission clock signal line ECK1 and the second emission clock signal line ECK 2.
Optionally, on the basis of the foregoing embodiment, with continuing to refer to fig. 3 and fig. 5, the non-display area 200 provided in the embodiment of the present invention may further include a first frame area 201 and a second frame area 202, where the first frame area 201 and the second frame area 202 are disposed opposite to each other, and the connection terminal setting area 203 is adjacent to the first frame area 201 and the second frame area 202; the second trace 102 of the light-emitting clock signal line ECK is disposed in the first frame region 201 and/or the second frame region 202.
Specifically, the arrangement makes the signal voltage drops of the light-emitting clock signals transmitted on the second trace 102 of the light-emitting clock signal line ECK at different output positions as small as possible, so that the light-emitting control signals output by the first scanning circuits 10 tend to be consistent, the influence of the light-emitting clock signal line ECK on the light-emitting control signals output by the first scanning circuits 10 is as same as possible, and the display effect of the display panel is further improved. It should be noted that fig. 5 exemplarily shows a case where the second trace 102 of the light-emitting clock signal line ECK is disposed in the first frame region 201 and the second frame region 202, and is not limited herein.
Optionally, fig. 6 is a schematic structural diagram of a serpentine trace according to an embodiment of the present invention. On the basis of the foregoing embodiment, with reference to fig. 3 and fig. 6, the serpentine trace S provided in the embodiment of the present invention may include a plurality of loop-shaped segments 111, where each loop-shaped segment 111 includes a first edge, a second edge, and a third edge, the first edge and the second edge are disposed opposite to each other, and the third edge is connected to the first edge and the second edge respectively; and a connecting section 121, wherein a second edge of the nth loop-shaped section 111 is connected with a first edge of the (N + 1) th loop-shaped section 111 through the connecting section 121, wherein N is an integer greater than or equal to 1.
Specifically, the first traces 101 are arranged in such a way that they are connected, and the widths of the loop-shaped segments 111 can be set to be the same or different according to needs. The number of the loop segments 111 may be set according to the space of the display panel. As long as the resistances of the light-emitting clock signal lines are ensured to be the same. The loop-shaped segment 111 may be a straight segment or an arc segment, and is not limited herein.
Optionally, fig. 7 is a schematic structural diagram of another display panel provided in an embodiment of the present invention. On the basis of the above embodiments, with reference to fig. 1 and fig. 7, the display panel provided in the embodiment of the present invention may further include a second scan circuit 20, where the second scan circuit 20 is configured to generate a scan signal; a Scan signal line Scan connected to a signal output terminal Scan _ out of the second Scan circuit 20, the Scan signal line being used to transmit a Scan signal; a scan clock signal line SCK connected to a clock signal input terminal CLK of the second scan circuit 20, the scan clock signal line SCK being used to transmit a scan clock signal; the scan clock signal line SCK is located in the non-display area 200 of the display panel; the non-display area 200 includes a connection terminal setting area 203, and the scan clock signal line SCK located in the connection terminal setting area 203 is a straight line segment.
Specifically, the Scan clock signal line SCK is connected to the clock signal input terminal CLK of the second Scan circuit 20, the second Scan circuit 20 generates a Scan control signal according to the Scan clock signal transmitted through the Scan clock signal line SCK, and transmits the Scan control signal to the Scan signal line Scan through the signal output terminal Scan _ out of the second Scan circuit 20, and the Scan signal line Scan transmits the Scan signal to the pixel circuit 1. The Scan clock signal line SCK located in the connection terminal setting area 203 is set as a straight line segment, so that the resistance of the Scan clock signal line SCK can be reduced, the signal transmission efficiency of the Scan signal line Scan is improved, and the display effect of the display panel is better. The display panel may include a plurality of scan clock signal lines SCK, and fig. 7 exemplarily shows a case where the display panel includes two scan clock signal lines SCK1 and SCK 2.
Alternatively, on the basis of the above embodiments, with reference to fig. 3 to 6, the width range of the narrower one of the first trace 101 and the second trace 102 may include 0.01 μm to 10 μm.
Optionally, on the basis of the above embodiment, with reference to fig. 3 to fig. 6, a thickness range of the trace with the smaller thickness in the first trace 101 and the second trace 102 includes: 0.01-10 μm.
Specifically, the width of the narrower one of the first trace 101 and the second trace 102 is as narrow as possible or the thickness of the thinner one of the first trace 101 and the second trace 102 is as small as possible, so that the resistance of the narrower or thinner one of the first trace 101 and the second trace 102 is as large as possible. Limited by the process, the width range of the narrower one of the first trace 101 and the second trace 102 of the light-emitting clock signal line ECK may be set to include 0.01 μm to 10 μm, or the thickness range of the thinner one of the first trace 101 and the second trace 102 of the light-emitting clock signal line ECK may be set to include 0.01 μm to 10 μm, which is convenient for the process manufacturing and can meet the requirement of increasing the resistance of the narrower one of the first trace 101 and the second trace 102. Since the resistance of the emission clock signal line ECK is increased, the delay of the emission clock signal is increased. The delay of the light emission clock signal increases and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light emission control signal. The light emission clock signal transmitted by the light emission clock signal line ECK extends the transition time of the light emission control signal, so that the amount of electric charge per unit time of the light emission control signal becomes small. By the arrangement, the coupling capacitance between the source electrode of the driving transistor and the light-emitting control signal line EM and the coupling capacitance between the drain electrode of the driving transistor and the light-emitting control signal line EM can be reduced, so that the difference between the grid voltages caused by the influence of parasitic capacitance on the driving transistors of different pixel circuits is reduced, the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits is further improved, and the display effect of the display panel is improved.
Alternatively, on the basis of the above-described embodiments, with reference to fig. 3 to 6, the resistance of the light-emitting clock signal line ECK is less than or equal to 10k Ω.
Specifically, the resistance of the light-emitting clock signal line ECK is set to be less than or equal to 10k Ω, so that the phenomenon that the time of the rising edge and the falling edge of the light-emitting control signal of the display panel is too long due to the overlarge resistance of the light-emitting clock signal line ECK can be avoided, and the display panel is ensured to have a good display effect. And the resistance of the ECK can be increased, so that the difference between grid voltages caused by the influence of parasitic capacitance on the driving transistors of different pixel circuits is reduced, the consistency of the brightness of the light emitting elements of different pixel circuits is further improved, the mura defect of the display panel is solved, and the display effect of the display panel is further improved.
Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention. On the basis of the above-described embodiment, with reference to fig. 8 and 9, the display panel according to the embodiment of the present invention includes a first scan circuit 10, where the first scan circuit 10 is configured to generate a light emission control signal; light emission control signal lines EM 1 to EM n connected to a signal output end EM _ out of the first scan circuit 10, the light emission control signal lines being used to transmit light emission control signals; a light emission clock signal line ECK connected to a clock signal input terminal CLK of the first scan circuit 10, the light emission clock signal line ECK being used to transmit a light emission clock signal to the clock signal input terminal CLK of the first scan circuit 10; the light emitting clock signal line ECK includes a serpentine trace S for extending a transition time of the light emitting control signal.
Specifically, the light-emitting clock signal line ECK is provided with the snake-shaped routing S, so that the resistance of the light-emitting clock signal line ECK can be increased. Due to the fact that the resistance of the light-emitting clock signal line ECK is increased, the time delay of the light-emitting clock signal can be increased, the light-emitting clock signal can prolong the transition time of the light-emitting control signal, and therefore the charge quantity of the light-emitting control signal transmitted by the light-emitting control signal line in unit time is reduced. Since the coupling capacitor has a function of passing high frequency and low frequency, the charge amount per unit time of the light emission control signal becomes small, and the coupling effect of the capacitor can be weakened, so that the difference between the source of the driving transistor T1 and the coupling capacitor C4 between the light emission control signal lines of different pixel circuits 1 becomes small. Therefore, the difference of the coupling capacitance C5 between the drain of the driving transistor T1 and the light-emitting control signal line of different pixel circuits 1 is reduced, the consistency of the light-emitting brightness of the light-emitting element D1 of different pixel circuits 1 is improved, and the display effect of the display panel is improved.
The display panel provided by the embodiment is provided with the light-emitting clock signal line comprising the snake-shaped routing line, so that the light-emitting clock signal transmitted by the light-emitting clock signal line can prolong the jump time of the light-emitting control signal, and the electric charge amount in the unit time of the light-emitting control signal is reduced. The quantity of electric charges in the unit time of the light-emitting control signal is reduced, so that the coupling capacitance between the source of the driving transistor and the light-emitting control signal line and the coupling capacitance between the drain of the driving transistor and the light-emitting control signal line are reduced, and the difference between the grid voltages of the driving transistors of different pixel circuits caused by the influence of parasitic capacitance is reduced. The arrangement improves the consistency of the brightness of the light emitting elements of different pixel circuits, and improves the display effect of the display panel.
Optionally, the serpentine trace comprises:
the device comprises a plurality of clip sections, a plurality of clip sections and a plurality of connecting sections, wherein each clip section comprises a first edge, a second edge and a third edge, the first edge and the second edge are arranged oppositely, and the third edge is respectively connected with the first edge and the second edge;
and the second edge of the Nth square-shaped section is connected with the first edge of the (N + 1) th square-shaped section through the connecting section, wherein N is an integer greater than or equal to 1.
Since the specific structure of the serpentine trace has been defined in the above-mentioned embodiment (refer to the embodiment in fig. 6), the present embodiment is similar to the serpentine trace in the above-mentioned embodiment (refer to the embodiment in fig. 6), and will not be repeated herein.
Optionally, referring to fig. 9, the width of the first trace 101 may be the same as the width of the second trace 102, so that the process is simple and the manufacturing is convenient. It should be noted that fig. 9 only exemplarily shows a case where the width of the first trace 101 is the same as the width of the second trace 102, and of course, the width of the first trace 101 may not be the same as the width of the second trace 102, and is not limited herein.
Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention. On the basis of the foregoing embodiments, referring to fig. 10, a display device 700 provided in an embodiment of the present invention includes the display panel 600 provided in any of the above embodiments, has the beneficial effects of the display panel 600 provided in the above embodiments, and is not described again here. The display device 700 may include mobile terminals such as mobile phones, tablet computers, and wearable devices.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
a first scanning circuit for generating a light emission control signal;
a light emission control signal line connected to a signal output terminal of the first scanning circuit, the light emission control signal line being used for transmitting a light emission control signal;
a light emitting clock signal line connected to a clock signal input terminal of the first scanning circuit, the light emitting clock signal line being configured to transmit a light emitting clock signal to the clock signal input terminal of the first scanning circuit;
the light-emitting clock signal line comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross-sectional area of one of the first wire and the second wire is smaller than that of the other wire so as to prolong the jump time of the light-emitting control signal.
2. The display panel according to claim 1,
one of the first trace and the second trace comprises a serpentine trace, and the other comprises a linear trace;
optionally, the first trace includes a serpentine trace, and the second trace includes a linear trace.
3. The display panel of claim 1, wherein the cross-sectional area of the first trace is smaller than the cross-sectional area of the second trace.
4. The display panel according to claim 1, wherein the display panel is divided into a display area and a non-display area, the non-display area at least partially surrounds the display area, the non-display area includes a connection terminal setting area;
the light-emitting clock signal line is positioned in the non-display area;
the first routing is located in the connecting terminal setting area.
5. The display panel according to claim 4, wherein the non-display region further includes a first frame region and a second frame region, the first frame region and the second frame region being disposed opposite to each other, the connection terminal disposition region being adjacent to the first frame region and the second frame region;
the second routing of the light-emitting clock signal line is arranged in the first frame area and/or the second frame area.
6. The display panel of claim 2, wherein the serpentine trace comprises:
the circuit comprises a plurality of circuit sections, a plurality of circuit sections and a plurality of control circuits, wherein each circuit section comprises a first side, a second side and a third side, the first side and the second side are arranged oppositely, and the third side is respectively connected with the first side and the second side;
and the second edge of the Nth square-shaped section is connected with the first edge of the (N + 1) th square-shaped section through the connecting section, wherein N is an integer greater than or equal to 1.
7. The display panel of claim 1, wherein the cross-sectional area of one of the first trace and the second trace is smaller than the cross-sectional area of the other trace, and wherein the cross-sectional area of one of the first trace and the second trace comprises at least one of: one of the first trace and the second trace has a width smaller than that of the other trace, and one of the first trace and the second trace has a thickness smaller than that of the other trace;
optionally, when a width of one of the first trace and the second trace is smaller than a width of the other trace, a width range of a narrower trace of the first trace and the second trace includes: 0.01-10 μm;
optionally, when the thickness of one of the first trace and the second trace is smaller than that of the other trace, the thickness range of the trace with the smaller thickness in the first trace and the second trace includes: 0.01-10 μm.
8. The display panel according to claim 1,
the resistance of the light emitting clock signal line is less than or equal to 10k omega.
9. A display panel, comprising:
a first scanning circuit for generating a light emission control signal;
a light emission control signal line connected to a signal output terminal of the first scanning circuit, the light emission control signal line being used for transmitting a light emission control signal;
a light emitting clock signal line connected to a clock signal input terminal of the first scanning circuit, the light emitting clock signal line being configured to transmit a light emitting clock signal to the clock signal input terminal of the first scanning circuit;
the light emitting clock signal line comprises a snake-shaped wiring, and the snake-shaped wiring is used for prolonging the jump time of the light emitting control signal.
10. A display device, comprising:
the display panel of any one of claims 1 to 8;
alternatively, the display panel of claim 9.
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