CN114241970B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114241970B CN114241970B CN202111587178.7A CN202111587178A CN114241970B CN 114241970 B CN114241970 B CN 114241970B CN 202111587178 A CN202111587178 A CN 202111587178A CN 114241970 B CN114241970 B CN 114241970B
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- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims description 24
- 230000002035 prolonged effect Effects 0.000 abstract description 4
- 230000008878 coupling Effects 0.000 description 35
- 238000010168 coupling process Methods 0.000 description 35
- 238000005859 coupling reaction Methods 0.000 description 35
- 230000000694 effects Effects 0.000 description 22
- 230000007704 transition Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 7
- 230000004044 response Effects 0.000 description 6
- 230000001808 coupling effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 101100420795 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sck1 gene Proteins 0.000 description 1
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- Electroluminescent Light Sources (AREA)
- Control Of El Displays (AREA)
Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel comprises a first scanning circuit, wherein the first scanning circuit is used for generating a light-emitting control signal; a light emission control signal line connected to a signal output terminal of the first scanning circuit; a light-emitting clock signal line connected to the clock signal input terminal of the first scan circuit, the light-emitting clock signal line being configured to transmit a light-emitting clock signal to the clock signal input terminal of the first scan circuit; the luminous clock signal wire comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross section area of one wire of the first wire and the second wire is smaller than that of the other wire, so that the jump time of the luminous control signal is prolonged. The technical scheme provided by the embodiment improves the consistency of the luminous brightness of the luminous elements of different pixel circuits.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, the requirements of people on the display panel are increasing. The prior display panel has mura defects during display, which affect the display effect of the display device.
Disclosure of Invention
The embodiment of the invention provides a display device, which aims to solve the problem that the display effect of the display device is affected due to poor display mura.
In order to realize the technical problems, the invention adopts the following technical scheme:
an embodiment of the present invention provides a display device including:
in a first aspect, an embodiment of the present invention provides a display panel, including:
the first scanning circuit is used for generating a light-emitting control signal;
a light-emitting control signal line connected with the signal output end of the first scanning circuit, wherein the light-emitting control signal line is used for transmitting a light-emitting control signal;
a light-emitting clock signal line connected to the clock signal input terminal of the first scan circuit, the light-emitting clock signal line being configured to transmit a light-emitting clock signal to the clock signal input terminal of the first scan circuit;
the luminous clock signal wire comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross section area of one wire of the first wire and the second wire is smaller than that of the other wire, so that the jump time of the luminous control signal is prolonged.
Optionally, one of the first trace and the second trace includes a serpentine trace, and the other trace includes a linear trace;
optionally, the first trace comprises a serpentine trace and the second trace comprises a linear trace.
Optionally, the cross-sectional area of the first trace is smaller than the cross-sectional area of the second trace.
Optionally, the display panel is divided into a display area and a non-display area, the non-display area at least partially surrounds the display area, and the non-display area comprises a connection terminal setting area;
the light-emitting clock signal line is positioned in the non-display area;
the first wiring is located in the connecting terminal setting area.
Optionally, the non-display area further includes a first frame area and a second frame area, the first frame area and the second frame area are oppositely arranged, and the connection terminal setting area is adjacent to the first frame area and the second frame area;
the second wiring of the luminous clock signal line is arranged in the first frame area and/or the second frame area.
Optionally, the serpentine trace comprises:
the plurality of the square sections comprise a first edge, a second edge and a third edge, the first edge and the second edge are oppositely arranged, and the third edge is respectively connected with the first edge and the second edge;
the second edge of the N-th rectangular section is connected with the first edge of the (n+1) -th rectangular section through the connecting section, wherein N is an integer greater than or equal to 1.
Optionally, the cross-sectional area of one of the first trace and the second trace is smaller than the cross-sectional area of the other trace includes at least one of: the width of one of the first wire and the second wire is smaller than that of the other wire, and the thickness of one of the first wire and the second wire is smaller than that of the other wire.
Optionally, in a case where a width of one of the first trace and the second trace is smaller than a width of the other trace, a width range of a narrower one of the first trace and the second trace includes: 0.01 μm to 10 μm.
Optionally, in a case where a thickness of one of the first trace and the second trace is smaller than a thickness of the other trace, a thickness range of the trace having the smaller thickness of the first trace and the second trace includes: 0.01 μm to 10 μm.
Optionally, the resistance of the light-emitting clock signal line is less than or equal to 10kΩ.
In a second aspect, an embodiment of the present invention provides a display panel, including:
the first scanning circuit is used for generating a light-emitting control signal;
a light-emitting control signal line connected with the signal output end of the first scanning circuit, wherein the light-emitting control signal line is used for transmitting a light-emitting control signal;
a light-emitting clock signal line connected to the clock signal input terminal of the first scan circuit, the light-emitting clock signal line being configured to transmit a light-emitting clock signal to the clock signal input terminal of the first scan circuit;
the light-emitting clock signal line comprises a serpentine wire which is used for prolonging the jump time of the light-emitting control signal.
In a third aspect, an embodiment of the present invention provides a display device, including the display panel set forth in any of the first aspects; alternatively, the display panel proposed in the second aspect.
According to the display panel provided by the embodiment of the invention, the luminous clock signal wire comprises the first wire and the second wire, the cross section area of one wire of the first wire and the second wire is smaller than that of the other wire, and the resistance of the luminous clock signal wire is increased. Since the resistance of the light-emitting clock signal line is increased to increase the delay of the light-emitting clock signal, the delay of the light-emitting clock signal is increased, and the response speed of the corresponding first scan circuit is slowed down to increase the transition time of the light-emitting control signal. The light-emitting clock signal transmitted by the light-emitting clock signal line can prolong the jump time of the light-emitting control signal, so that the charge amount in unit time of the light-emitting control signal is reduced. The amount of charge per unit time of the light emission control signal becomes smaller, thereby reducing the coupling capacitance existing between the source of the driving transistor and the light emission control signal line and the coupling capacitance existing between the drain of the driving transistor and the light emission control signal line, and further reducing the difference between gate voltages of the driving transistors of different pixel circuits due to the influence of parasitic capacitance. The arrangement improves the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits and improves the display effect of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 4 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a serpentine trace according to an embodiment of the present invention;
FIG. 7 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic view of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic view of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
As mentioned in the background art, the existing display panel has bad display mura, which affects the display effect of the display panel.
Based on the above technical problems, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1 and 2, the display panel includes a plurality of light emitting units including light emitting elements D1 and their corresponding pixel circuits 1. The display panel further includes a first power signal line ELVDD, a second power signal line ELVSS, and an initialization signal line Vref. Each pixel circuit 1 is connected to a first power signal line ELVDD, a second power signal line ELVSS, and an initialization signal line Vref, respectively. In each light emitting unit, the pixel circuit 1 includes a plurality of thin film transistors and a storage capacitor, the thin film transistors may include a driving transistor T1 and a switching transistor, a first power signal line ELVDD is connected to a first terminal of the driving transistor T1, a second terminal of the driving transistor T1 is connected to an anode of the light emitting element D1, and a cathode of the light emitting element D1 is connected to a second power signal line ELVSS. The driving transistor T1 can generate a driving current to drive the light emitting element D1 connected to the pixel circuit 1 to emit light, and the switching transistor mainly plays a role of switching. The first power signal line ELVDD and the second power signal line ELVSS serve as power sources for driving the transistor T1 to generate a driving current, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light.
Referring to fig. 1, the display panel may further include a plurality of Scan signal lines Scan 1-Scan n, a plurality of data signal lines Vdata 1-Vdata n, a plurality of light emission control signal lines EM 1-EM n, and a connection terminal 300, wherein the pixel circuit 1 is disposed in a region defined by the Scan signal lines Scan and Vdata intersecting each other, a Scan signal is input to the corresponding pixel circuit 1 through the Scan signal lines Scan, the pixel circuit 1 is connected to the data signal lines Vdata electrically connected thereto under the action of the Scan signal input from the Scan signal lines Scan electrically connected thereto, the connection terminal 300 may be connected to a driving chip, the driving chip inputs a data signal to the corresponding pixel circuit 1 through the connection terminal 300, and a voltage of the data signal corresponds to a driving voltage to determine a light emission luminance of the light emitting element D1, that is, a display gray scale of the light emitting element D1 is determined. It should be noted that the driving transistor, the switching transistor, and the storage capacitor may form the pixel circuit 1 in various forms in various connection relations. The pixel circuit 1 shown in fig. 2 is only an example, and other forms of pixel circuits are also possible, such as a 3T1C pixel circuit, a 7T1C pixel circuit, an 8T2C pixel circuit, etc., where T represents a transistor and C represents a capacitor. Fig. 2 exemplarily shows a case of a 7T1C pixel circuit, and is not limited to the pixel circuit 1.
Referring to fig. 1 and 2, the first power signal line ELVDD may be used to transmit the first power signal and the second power signal line ELVSS may be used to transmit the second power signal. The voltage on the first power signal line ELVDD is generally a high level voltage, and the voltage on the second power signal line ELVSS is generally a low level voltage. In the light emitting stage, the first power signal on the first power signal line ELVDD is applied to the first pole of the driving transistor T1, the second power signal on the second power signal line ELVSS is applied to the second pole, e.g., the second pole is the cathode, of the light emitting element D1, and the first power signal and the second power signal serve as the power source for generating the driving current for the driving transistor T1, so that the driving transistor T1 generates the driving current to drive the light emitting element D1 to emit light. The first power supply signal line ELVDD may be a signal line directly connected to one pole (e.g., drain or source) of the driving transistor T1 in the pixel circuit 1, or a signal line indirectly connected to one pole of the driving transistor T1 in the pixel circuit 1 through a switching transistor (e.g., light emission control transistor), and the second power supply signal line ELVSS may be a signal line connected to the cathode of the light emitting element D1. The initialization signal line Vref may be used to transmit an initialization signal to the pixel circuit 1.
Referring to fig. 1 and 2, the display panel may include a plurality of pixel circuits 1, the pixel circuits 1 for driving the light emitting elements D1 to emit light, and the pixel circuits 1 control the light emitting brightness of the light emitting elements D1 by controlling the driving current flowing through the light emitting elements D1.
Referring to fig. 2, a pixel circuit according to an embodiment of the present invention may correspond to a specific circuit structure of the pixel circuit 1 in the display panel shown in fig. 1, such as a 7T1C pixel circuit. Referring to fig. 1 and 2, the pixel circuit 1 includes a driving transistor T1, a first initializing transistor T4, a second initializing transistor T7, a third transistor T2, a fourth transistor T5, a fifth transistor T6, a sixth transistor T3, and a storage capacitor C1. Fig. 2 exemplarily shows a case where the sixth transistor T3 is a double gate transistor including the transistor T3-1 and the transistor T3-2, and the first initialization transistor T4 is a double gate transistor including the transistor T4-1 and the transistor T4-2.
In the initialization stage, the Scan signal input by the first Scan signal line Scan1 may control the first initialization transistor T4 to be turned on, so as to write the initialization signal input by the initialization signal line Vref into the storage capacitor C1 and the gate of the driving transistor T1.
In the data writing stage, the Scan signal input from the third Scan signal line Scan3 may control the second initializing transistor T7 to be turned on to transmit the initializing signal input from the initializing signal line Vref to the anode of the light emitting element D1 to initialize the anode of the light emitting element D1. The Scan signal inputted from the second Scan signal line Scan2 may control the third transistor T2 and the sixth transistor T3 to be turned on to write the data voltage signal inputted from the data voltage signal line Vdata to the gate of the driving transistor T1 and charge the storage capacitor C1.
In the light emitting stage, the light emission control signal input from the light emission control signal line EM may control the fourth transistor T5 and the fifth transistor T6 to be turned on, and the first power signal and the second power signal serve as power sources for generating driving currents for the driving transistor T1, so that the driving transistor T1 generates driving currents to drive the light emitting element D1 to emit light.
Since the coupling capacitance C2 exists between the source and the gate of the driving transistor T1 in the pixel circuit 1, the coupling capacitance C3 exists between the drain and the gate of the driving transistor T1, the coupling capacitance C4 exists between the source of the driving transistor T1 and the emission control signal line EM, and the coupling capacitance C5 exists between the drain of the driving transistor T1 and the emission control signal line EM. The coupling capacitance C4 existing between the source of the driving transistor T1 and the emission control signal line EM is a parasitic capacitance, and the coupling capacitance C5 existing between the drain of the driving transistor T1 and the emission control signal line EM is a parasitic capacitance.
Due to process fluctuation, the coupling capacitance C4 existing between the source of the driving transistor T1 and the emission control signal line EM and the coupling capacitance C5 existing between the drain of the driving transistor T1 and the emission control signal line EM of the different pixel circuits 1 are also different. The coupling effect of the capacitor may cause a change in the gate voltage of the driving transistor T1, and the coupling capacitance C4 between the source of the driving transistor T1 and the emission control signal line EM of the different pixel circuits 1 and the coupling capacitance C5 between the drain of the driving transistor T1 and the emission control signal line EM are different, which causes an inconsistency in the gate voltage of the driving transistor T1 of the different pixel circuits 1, and an inconsistency in the emission brightness of the different light emitting elements D1, which causes a display mura defect in the display panel, and affects the display effect of the display panel.
Fig. 3 is a schematic view of another display panel according to an embodiment of the invention. Referring to fig. 1 to 3, a display panel according to an embodiment of the present invention includes a first scan circuit 10, where the first scan circuit 10 is configured to generate a light emission control signal; a light emission control signal line EM connected to the signal output terminal em_out of the first scan circuit 10, the light emission control signal line EM being for transmitting a light emission control signal; a light-emitting clock signal line ECK connected to the clock signal input terminal CLK of the first scan circuit 10, the light-emitting clock signal line ECK being for transmitting a light-emitting clock signal to the clock signal input terminal CLK of the first scan circuit 10; the light emitting clock signal line ECK includes a first wire 101 and a second wire 102, an input end of the second wire 102 is connected to a first end of the first wire 101, an output end of the second wire 102 is connected to the clock signal input end CLK of the first scan circuit 10, and a cross-sectional area of one wire of the first wire 101 and the second wire 102 is smaller than a cross-sectional area of the other wire to extend a transition time of the light emitting control signal.
Specifically, the light-emitting clock signal line ECK is connected to the clock signal input terminal CLK of the first scan circuit 10, the first scan circuit 10 generates a light-emitting control signal according to the light-emitting clock signal transmitted by the light-emitting clock signal line ECK, and transmits the light-emitting control signal to the light-emitting control signal line EM through the signal output terminal em_out of the first scan circuit 10, the light-emitting clock signal can control the transition speed of the light-emitting control signal, and the light-emitting control signal line EM transmits the light-emitting control signal to the pixel circuit 1. The light emission control signal inputted from the light emission control signal line EM may control the fourth transistor T5 and the fifth transistor T6 of the pixel circuit 1 to be turned on, and the first power signal line ELVDD and the second power signal line ELVSS serve as power sources for generating driving currents for the driving transistor T1, so that the driving transistor T1 generates driving currents to drive the light emitting element D1 to emit light. The display panel may include a plurality of light-emitting clock signal lines ECK, and fig. 3 exemplarily illustrates a case where the display panel includes two light-emitting clock signal lines ECK1 and ECK 2.
The input end of the second wire 102 is connected to the first end of the first wire 101, the output end of the second wire 102 is connected to the clock signal input end CLK of the first scan circuit 10, the second end of the first wire 101 is connected to the connection terminal 300, and the driving chip transmits the light-emitting clock signal to the clock signal input end CLK of the first scan circuit 10 through the connection terminal 300 and through the first wire 101 and the second wire 102.
The cross-sectional area of one of the first and second wirings 101 and 102 is smaller than that of the other, increasing the resistance of the light-emitting clock signal line ECK. Since the resistance of the light-emitting clock signal line ECK is increased, the delay of the light-emitting clock signal is increased. The delay of the light-emitting clock signal increases, and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light-emitting control signal. The emission clock signal lengthens the transition time of the emission control signal, thereby making the amount of charge per unit time of the emission control signal transmitted by the emission control signal line EM smaller. Since the coupling capacitance has the effect of passing high frequency resistance and low frequency, the charge amount in unit time of the light emission control signal becomes smaller, and the coupling effect of the capacitance can be weakened, thereby reducing the coupling capacitance C4 existing between the source electrode of the driving transistor T1 and the light emission control signal line EM and the coupling capacitance C5 existing between the drain electrode of the driving transistor T1 and the light emission control signal line EM.
The coupling capacitance C4 between the source of the driving transistor T1 of the pixel circuit 1 and the emission control signal line EM is reduced, so that the difference between the coupling capacitances C4 between the source of the driving transistor T1 of the different pixel circuits 1 and the emission control signal line EM becomes smaller. The smaller coupling capacitance C5 between the drain of the driving transistor T1 and the emission control signal line EM makes the difference of the coupling capacitance C5 between the drain of the driving transistor T1 and the emission control signal line EM of the different pixel circuits 1 smaller, so that the difference between the gate voltages of the driving transistors T1 of the different pixel circuits 1 is reduced by the influence of the parasitic capacitance, the uniformity of the emission brightness of the light emitting elements D1 of the different pixel circuits 1 is improved, and the display effect of the display panel is improved.
The display panel provided by the embodiment comprises the first wiring and the second wiring by arranging the luminous clock signal wire, wherein the cross section area of one of the first wiring and the second wiring is smaller than that of the other wiring, and the resistance of the luminous clock signal wire is increased. Since the resistance of the light-emitting clock signal line is increased to increase the delay of the light-emitting clock signal, the delay of the light-emitting clock signal is increased, and the response speed of the corresponding first scan circuit is slowed down to increase the transition time of the light-emitting control signal. The light-emitting clock signal transmitted by the light-emitting clock signal line can prolong the jump time of the light-emitting control signal, so that the charge amount in unit time of the light-emitting control signal is reduced. The amount of charge per unit time of the light emission control signal becomes smaller, thereby reducing the coupling capacitance existing between the source of the driving transistor and the light emission control signal line and the coupling capacitance existing between the drain of the driving transistor and the light emission control signal line, and further reducing the difference between gate voltages of the driving transistors of different pixel circuits due to the influence of parasitic capacitance. The arrangement improves the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits and improves the display effect of the display panel.
Optionally, fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention. On the basis of the above embodiment, with continued reference to fig. 3 and 4, one of the first trace 101 and the second trace 102 includes a serpentine trace, and the other trace includes a linear trace. It should be noted that fig. 3 and fig. 4 only exemplarily illustrate a case where the first trace 101 includes a serpentine trace and the second trace 102 includes a linear trace, which is not limited in any way.
Specifically, one of the first trace 101 and the second trace 102 includes a serpentine trace, and the other trace includes a linear trace. The serpentine routing may increase the length of the light-emitting clock signal line ECK, and thus the arrangement may further increase the resistance of the light-emitting clock signal line ECK. Since the resistance of the light-emitting clock signal line ECK is increased, the delay of the light-emitting clock signal is increased. The delay of the light-emitting clock signal increases, and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light-emitting control signal. The emission clock signal lengthens the transition time of the emission control signal, thereby making the amount of charge per unit time of the emission control signal transmitted by the emission control signal line EM smaller. Since the coupling capacitance has the effect of passing high frequency resistance and low frequency, the charge amount in unit time of the light emission control signal becomes smaller, and the coupling effect of the capacitance can be weakened, thereby reducing the coupling capacitance C4 existing between the source electrode of the driving transistor T1 and the light emission control signal line EM and the coupling capacitance C5 existing between the drain electrode of the driving transistor T1 and the light emission control signal line EM.
The coupling capacitance C4 between the source electrode of the driving transistor T1 of the pixel circuit 1 and the light-emitting control signal line EM is reduced, so that the difference between the coupling capacitance C4 between the source electrode of the driving transistor T1 of the different pixel circuits 1 and the light-emitting control signal line EM is reduced, the difference between the grid voltages of the driving transistors T1 of the different pixel circuits 1 is reduced due to the influence of parasitic capacitance, the uniformity of the light-emitting brightness of the light-emitting elements D1 of the different pixel circuits 1 is further improved, and the display effect of the display panel is improved.
Optionally, with continued reference to fig. 4 based on the above embodiment, the first trace 101 includes a serpentine trace S and the second trace 102 includes a linear trace L.
Specifically, the first trace 101 may include a serpentine trace S, and the first trace 101 may include a serpentine trace S and a linear trace L. The second trace 102 includes a linear trace L, where the linear trace L may be a combination of one or more segments, and is not limited in any way. The second trace 102 is configured to stably output the light-emitting clock signal transmitted by the first trace 101 to the clock signal input terminal CLK of the first scan circuit 10, so as to prolong the transition time of the rising edge and the falling edge of the light-emitting control signal.
By setting the first trace 101 to include the serpentine trace S, the second trace 102 includes the linear trace L, and since the resistance of the second trace 102 including the linear trace L is smaller, the resistance of the first trace 101 including the serpentine trace S is larger, so that the delay of the light-emitting clock signal output by the driving chip is increased after passing through the first trace 101 having a larger resistance. The delayed light-emitting clock signal is output to the clock signal input terminal of the first scan circuit 10 through the second trace 102 with smaller resistance. The second wirings 102 with smaller resistance make the light-emitting clock signals received by the first scanning circuits 10 corresponding to the pixel circuits 1 of different rows as identical as possible, so that the light-emitting control signals among the pixel circuits 1 of different rows are consistent as much as possible. The second trace 102 with smaller resistance can reduce the voltage drop between different output ends, so that the light-emitting clock signals output to the clock signal input ends of the first scanning circuits 10 are stable, the jump time of the rising edge and the falling edge of the light-emitting control signals is prolonged, the light-emitting control signals among the pixel circuits 1 of different rows are consistent as much as possible, and the display effect of the display panel is further improved.
Optionally, in addition to the foregoing embodiment, the cross-sectional area of one of the first trace and the second trace is smaller than the cross-sectional area of the other trace includes at least one of: the width of one of the first wire and the second wire is smaller than that of the other wire, and the thickness of one of the first wire and the second wire is smaller than that of the other wire.
The thickness direction of the first trace and the second trace refers to the thickness direction of the display panel.
Alternatively, in the case where the width of one of the first and second traces is smaller than the width of the other trace, with continued reference to fig. 1 or 4, the width of the first trace 101 is smaller than the width of the second trace 102. The thicknesses of the first trace 101 and the second trace 102 may be the same or different, which is not limited herein.
Specifically, the width of the first trace 101 may be set smaller than the width of the second trace 102, so that on one hand, the resistance of the first trace 101 is further increased, and the resistance of the light-emitting clock signal line ECK is increased, thereby increasing the delay of the light-emitting clock signal. The delay of the light emission clock signal increases, and the response speed of each corresponding first scanning circuit 10 becomes slow, thereby increasing the transition time of the light emission control signal. The light-emitting clock signal transmitted by the light-emitting clock signal line ECK can make the transition time of the light-emitting control signal longer, so that the electric charge amount in unit time of the light-emitting control signal is smaller. Thereby, the coupling capacitance between the source electrode of each light emission control signal line EM 1-EM n and the driving transistor and the coupling capacitance between the drain electrode of each light emission control signal line EM 1-EM n and the driving transistor are further reduced, and further, the difference between gate voltages caused by the influence of parasitic capacitance on the driving transistors of different pixel circuits is reduced. The arrangement improves the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits and improves the display effect of the display panel.
On the other hand, the width of the second trace 102 is set to be larger, the resistance of the second trace 102 of the light-emitting clock signal line ECK can be further reduced, and the second trace 102 with smaller resistance makes the voltage drop of the light-emitting clock signals received by the first scanning circuits 10 corresponding to the pixel circuits 1 of different rows smaller, so that the difference between the light-emitting clock signals received by the first scanning circuits 10 corresponding to the pixel circuits 1 of different rows is smaller, and the light-emitting control signals between the pixel circuits 1 of different rows are as consistent as possible. And the second trace 102 with smaller resistance can reduce the voltage drop between different output ends, so that the light-emitting clock signals output to the clock signal input ends of the first scanning circuits 10 are stable, the light-emitting control signals output by the first scanning circuits 10 connected with the second trace 102 are consistent as much as possible, the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits is further improved, and the display effect of the display panel is improved.
Optionally, in a case that a thickness of one of the first trace and the second trace is smaller than a thickness of the other trace, a thickness range of the trace having the smaller thickness of the first trace and the second trace includes: 0.01 μm to 10 μm. The widths of the first trace and the second trace may be the same or different, and are not limited herein.
Alternatively, if the width of one of the first and second wires is smaller than the width of the other wire, and the thickness of one of the first and second wires is smaller than the thickness of the other wire, in this case, the wire with the smaller width and the wire with the smaller thickness may be the same wire, and the wire with the larger width and the wire with the larger thickness may be the other wire.
Optionally, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 1, 3 and 5, the display panel provided in the embodiment of the present invention is divided into a display area 100 and a non-display area 200, the non-display area 200 at least partially surrounds the display area 100, and the non-display area 200 includes a connection terminal setting area 203; the light-emitting clock signal line is located in the non-display area 200; the first trace 101 is located in the connection terminal arrangement region 203.
Specifically, the light-emitting clock signal line is located in the non-display area 200, so that the light-emitting clock signal transmitted by the light-emitting clock signal line is conveniently transmitted from the non-display area 200 to the display area 100, the light-emitting clock signal line is a metal wiring, and the light-emitting clock signal line is provided with the non-display area 200, so that the light emitted by the light-emitting element can be prevented from being reflected by the metal wiring, and the display effect of the display panel is further improved. By setting the first trace 101 in the connection terminal setting area 203, for example, taking the example that the light-emitting clock signal line includes the first light-emitting clock signal line ECK1, the resistance of the first light-emitting clock signal line ECK1 may be increased near one end of the connection terminal setting area 203, so that the signals transmitted by the second trace 102 after the first light-emitting clock signal line ECK1 passes through the first trace 101 are consistent, and display uniformity of the display panel is further improved. Note that fig. 5 exemplarily illustrates a case where the light-emitting clock signal lines include a first light-emitting clock signal line ECK1 and a second light-emitting clock signal line ECK 2.
Optionally, on the basis of the foregoing embodiment, with continued reference to fig. 3 and fig. 5, the non-display area 200 provided in the embodiment of the present invention may further include a first frame area 201 and a second frame area 202, where the first frame area 201 and the second frame area 202 are oppositely disposed, and the connection terminal setting area 203 is adjacent to the first frame area 201 and the second frame area 202; the second trace 102 of the light-emitting clock signal line ECK is disposed in the first frame region 201 and/or the second frame region 202.
Specifically, the voltage drop of the light-emitting clock signal transmitted on the second trace 102 of the light-emitting clock signal line ECK at different output positions is as small as possible, so that the light-emitting control signals output by the first scan circuits 10 tend to be consistent, the influence of the light-emitting clock signal line ECK on the light-emitting control signals output by the first scan circuits 10 is as same as possible, and the display effect of the display panel is further improved. Note that, fig. 5 illustrates a case where the second trace 102 of the light-emitting clock signal line ECK is disposed in the first frame region 201 and the second frame region 202, which is not limited in any way.
Optionally, fig. 6 is a schematic structural diagram of a serpentine trace according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 3 and 6, the serpentine trace S provided in the embodiment of the present invention may include a plurality of loop-shaped segments 111, where the loop-shaped segments 111 include a first edge, a second edge, and a third edge, the first edge and the second edge are opposite to each other, and the third edge is connected to the first edge and the second edge respectively; the second side of the nth loop-shaped section 111 is connected with the first side of the (n+1) th loop-shaped section 111 through the connection section 121, where N is an integer greater than or equal to 1.
Specifically, the arrangement is such that the first wirings 101 are connected, and the widths of the respective loop-shaped sections 111 may be set to be the same or different as required. The number of the loop-shaped sections 111 may be set according to the space of the display panel. As long as the same resistance of each light-emitting clock signal line is ensured. The loop-shaped section 111 may be a straight line section or an arc section, which is not limited in this regard.
Optionally, fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 1 and 7, the display panel provided in the embodiment of the present invention may further include a second scanning circuit 20, where the second scanning circuit 20 is configured to generate a scanning signal; a Scan signal line Scan connected to the signal output terminal scan_out of the second Scan circuit 20, the Scan signal line being for transmitting a Scan signal; a scan clock signal line SCK connected to the clock signal input terminal CLK of the second scan circuit 20, the scan clock signal line SCK being for transmitting a scan clock signal; the scan clock signal line SCK is located in the non-display area 200 of the display panel; the non-display area 200 includes a connection terminal setting area 203, and a scan clock signal line SCK located in the connection terminal setting area 203 is a straight line segment.
Specifically, the Scan clock signal line SCK is connected to the clock signal input terminal CLK of the second Scan circuit 20, and the second Scan circuit 20 generates a Scan control signal according to the Scan clock signal transmitted by the Scan clock signal line SCK and transmits the Scan control signal to the Scan signal line Scan through the signal output terminal scan_out of the second Scan circuit 20, and the Scan signal line Scan transmits the Scan signal to the pixel circuit 1. The Scan clock signal line SCK located in the connection terminal setting area 203 is set to be a straight line segment, which can reduce the resistance of the Scan clock signal line SCK, improve the signal transmission efficiency of the Scan signal line Scan, and ensure that the display effect of the display panel is better. The display panel may include a plurality of scan clock signal lines SCK, and fig. 7 exemplarily illustrates a case where the display panel includes two scan clock signal lines SCK1 and SCK 2.
Alternatively, the narrower of the first trace 101 and the second trace 102 may have a width ranging from 0.01 μm to 10 μm, based on the above-described embodiments, in conjunction with fig. 3 to 6.
Optionally, on the basis of the above embodiment, in conjunction with fig. 3 to 6, a thickness range of the trace having a smaller thickness of the first trace 101 and the second trace 102 includes: 0.01 μm to 10 μm.
Specifically, the narrower width of the first trace 101 and the second trace 102 or the smaller thickness of the first trace 101 and the second trace 102 may make the narrower or thinner trace of the first trace 101 and the second trace 102 have the greatest possible resistance. The narrower width range of the first trace 101 and the second trace 102 in which the light-emitting clock signal line ECK may be disposed may include 0.01 μm to 10 μm, or the smaller thickness range of the first trace 101 and the second trace 102 in which the light-emitting clock signal line ECK may be disposed may include 0.01 μm to 10 μm, which is convenient for process fabrication and satisfies the need of increasing the resistance of the narrower one of the first trace 101 and the second trace 102. Since the resistance of the light-emitting clock signal line ECK is increased, the delay of the light-emitting clock signal is increased. The delay of the light-emitting clock signal increases, and the response speed of the corresponding first scan circuit 10 becomes slow, thereby increasing the transition time of the light-emitting control signal. The light-emitting clock signal transmitted by the light-emitting clock signal line ECK prolongs the transition time of the light-emitting control signal, so that the amount of charge per unit time of the light-emitting control signal becomes smaller. The arrangement can reduce the coupling capacitance between the source electrode of the driving transistor and the light-emitting control signal line EM and the coupling capacitance between the drain electrode of the driving transistor and the light-emitting control signal line EM, thereby reducing the difference between grid voltages caused by the influence of parasitic capacitance on the driving transistors of different pixel circuits, further improving the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits and improving the display effect of the display panel.
Alternatively, on the basis of the above-described embodiments, with reference to fig. 3 to 6, the resistance of the light-emitting clock signal line ECK is less than or equal to 10kΩ.
Specifically, the resistance of the light-emitting clock signal line ECK is set to be smaller than or equal to 10kΩ, so that the situation that the rising edge and the falling edge of the light-emitting control signal of the display panel are too long due to the fact that the resistance of the light-emitting clock signal line ECK is too large can be avoided, and the display panel is guaranteed to have a good display effect. The resistance of the light-emitting clock signal line ECK can be increased, so that the difference between grid voltages caused by the influence of parasitic capacitance on the driving transistors of different pixel circuits is reduced, the uniformity of the light-emitting brightness of the light-emitting elements of the different pixel circuits is further improved, the mura defect of the display panel is solved, and the display effect of the display panel is further improved.
Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the invention. Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the invention. On the basis of the above embodiment, referring to fig. 8 and 9, the display panel provided in the embodiment of the invention includes a first scan circuit 10, where the first scan circuit 10 is used to generate a light emission control signal; emission control signal lines EM 1 to EM n connected to the signal output terminal em_out of the first scan circuit 10, the emission control signal lines being for transmitting emission control signals; a light-emitting clock signal line ECK connected to the clock signal input terminal CLK of the first scan circuit 10, the light-emitting clock signal line ECK being for transmitting a light-emitting clock signal to the clock signal input terminal CLK of the first scan circuit 10; the light-emitting clock signal line ECK includes a serpentine trace S for extending the transition time of the light-emitting control signal.
Specifically, the light-emitting clock signal line ECK is provided with the serpentine trace S, so that the resistance of the light-emitting clock signal line ECK can be increased. The delay of the light-emitting clock signal is increased due to the increase of the resistance of the light-emitting clock signal line ECK, so that the light-emitting clock signal can prolong the jump time of the light-emitting control signal, and the charge amount in unit time of the light-emitting control signal transmitted by the light-emitting control signal line is reduced. Since the coupling capacitance has the effect of passing high frequency resistance and low frequency, the charge amount in unit time of the light emission control signal becomes smaller, the coupling effect of the capacitance can be weakened, and the difference between the source of the driving transistor T1 of the different pixel circuits 1 and the coupling capacitance C4 between the light emission control signal lines becomes smaller. Therefore, the difference of the coupling capacitance C5 between the drain electrode of the driving transistor T1 of the different pixel circuits 1 and the light-emitting control signal line is reduced, the uniformity of the light-emitting brightness of the light-emitting element D1 of the different pixel circuits 1 is improved, and the display effect of the display panel is improved.
The display panel provided by the embodiment comprises the snakelike wiring through the arrangement of the light-emitting clock signal line, so that the jump time of the light-emitting control signal can be prolonged by the light-emitting clock signal transmitted by the light-emitting clock signal line, and the charge amount in unit time of the light-emitting control signal is reduced. The amount of charge per unit time of the light emission control signal becomes smaller, thereby reducing the coupling capacitance existing between the source of the driving transistor and the light emission control signal line and the coupling capacitance existing between the drain of the driving transistor and the light emission control signal line, and further reducing the difference between gate voltages of the driving transistors of different pixel circuits due to the influence of parasitic capacitance. The arrangement improves the consistency of the light-emitting brightness of the light-emitting elements of different pixel circuits and improves the display effect of the display panel.
Optionally, the serpentine trace comprises:
the plurality of the square sections comprise a first edge, a second edge and a third edge, the first edge and the second edge are oppositely arranged, and the third edge is respectively connected with the first edge and the second edge;
the second edge of the N-th rectangular section is connected with the first edge of the (n+1) -th rectangular section through the connecting section, wherein N is an integer greater than or equal to 1.
Since the specific structure of the serpentine trace has been defined in the above embodiment (refer to the embodiment of fig. 6), this embodiment is similar to the serpentine trace in the above embodiment (refer to the embodiment of fig. 6), and the detailed description thereof will not be repeated.
Alternatively, referring to fig. 9, the width of the first trace 101 may be set to be the same as the width of the second trace 102, which is simple in process and convenient for manufacturing. It should be noted that fig. 9 only illustrates the case where the width of the first trace 101 is the same as the width of the second trace 102, and of course, the width of the first trace 101 and the width of the second trace 102 may be different, which is not limited in any way.
Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention. On the basis of the foregoing embodiments, referring to fig. 10, the display device 700 provided in the embodiment of the present invention includes the display panel 600 provided in any of the foregoing embodiments, and has the beneficial effects of the display panel 600 provided in the foregoing embodiments, which are not described herein again. The display device 700 may include a mobile terminal such as a cell phone, a tablet computer, and a wearable apparatus.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. A display panel, comprising:
a first scanning circuit for generating a light emission control signal;
the light-emitting control signal line is connected with the signal output end of the first scanning circuit and is used for transmitting a light-emitting control signal;
the light-emitting clock signal line is connected with the clock signal input end of the first scanning circuit and is used for transmitting a light-emitting clock signal to the clock signal input end of the first scanning circuit;
the luminous clock signal line comprises a first wire and a second wire, the input end of the second wire is connected with the first end of the first wire, the output end of the second wire is connected with the clock signal input end of the first scanning circuit, and the cross section area of one wire of the first wire and the second wire is smaller than the cross section area of the other wire so as to prolong the jump time of the luminous control signal;
the first wire comprises a serpentine wire, and the second wire comprises a linear wire;
the display panel is divided into a display area and a non-display area, the non-display area at least partially surrounds the display area, and the non-display area comprises a connecting terminal setting area;
the light-emitting clock signal line is positioned in the non-display area;
the first wiring is positioned in the connecting terminal setting area;
the non-display area further comprises a first frame area and a second frame area, the first frame area and the second frame area are arranged oppositely, and the connecting terminal arrangement area is adjacent to the first frame area and the second frame area;
the second wiring of the light-emitting clock signal line is arranged in the first frame area and/or the second frame area;
the cross-sectional area of the first wire is smaller than the cross-sectional area of the second wire.
2. The display panel of claim 1, wherein the display panel comprises,
one of the first and second traces includes a serpentine trace and the other includes a linear trace.
3. The display panel of claim 1, wherein a cross-sectional area of the first trace is smaller than a cross-sectional area of the second trace.
4. The display panel of claim 2, wherein the serpentine trace comprises:
the plurality of the square sections comprise a first edge, a second edge and a third edge, the first edge and the second edge are oppositely arranged, and the third edge is respectively connected with the first edge and the second edge;
the second edge of the N-th square section is connected with the first edge of the (n+1) -th square section through the connecting section, wherein N is an integer greater than or equal to 1.
5. The display panel of claim 1, wherein a cross-sectional area of one of the first trace and the second trace is smaller than a cross-sectional area of the other trace comprises at least one of: the width of one of the first wire and the second wire is smaller than that of the other wire, and the thickness of one of the first wire and the second wire is smaller than that of the other wire.
6. The display panel of claim 5, wherein in a case where a width of one of the first and second traces is smaller than a width of the other trace, a width range of a narrower one of the first and second traces includes: 0.01 μm to 10 μm.
7. The display panel according to claim 5, wherein in a case where a thickness of one of the first and second wirings is smaller than a thickness of the other wiring, a thickness range of the smaller one of the first and second wirings includes: 0.01 μm to 10 μm.
8. The display panel of claim 1, wherein the display panel comprises,
the resistance of the light-emitting clock signal line is less than or equal to 10kΩ.
9. A display device, comprising: the display panel of any one of claims 1 to 8.
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