CN110189703B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN110189703B
CN110189703B CN201910579039.6A CN201910579039A CN110189703B CN 110189703 B CN110189703 B CN 110189703B CN 201910579039 A CN201910579039 A CN 201910579039A CN 110189703 B CN110189703 B CN 110189703B
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signal line
test terminal
burn
electrically connected
potential signal
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CN110189703A (en
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高娅娜
周星耀
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Wuhan Tianma Microelectronics Co Ltd
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Wuhan Tianma Microelectronics Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Abstract

The embodiment of the invention discloses a display panel and a display device, wherein the display panel comprises a display area and a peripheral circuit area; the display area is provided with a plurality of scanning signal lines, a plurality of light-emitting control signal lines, a plurality of reference signal lines and a plurality of pixel circuits which are arranged in a matrix; the peripheral circuit region is provided with a plurality of scanning driving circuits, a plurality of light-emitting control circuits, a low potential signal wire, a high potential signal wire and a reference signal bus; the peripheral circuit region further comprises a plurality of aging test terminals, at least one of the low-potential signal line, the high-potential signal line and the reference signal bus is electrically connected with the two aging test terminals respectively, different aging test signals are connected to the two aging test terminals, it is guaranteed that in an aging test stage, the luminance of the pixel units in different positions of the display region is the same or similar, the aging speed of the pixel units in different positions is the same or similar, and it is guaranteed that the pixel units in different positions of the display region are good in display uniformity in the display stage.

Description

Display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
Organic Light Emitting Diode (OLED) is one of the hot spots in the research field of flat panel displays, and compared with Liquid Crystal Displays (LCD), OLED has the advantages of low energy consumption, low generation cost, self-luminescence, wide viewing angle, fast response speed, and the like.
However, since the light emitting material of the OLED display has a certain attenuation property, an aging test is generally performed before the OLED display leaves a factory, and a large light emitting signal is input to the OLED display during the aging test to accelerate the attenuation process of the light emitting material. However, the resistance on the wire for transmitting the test current causes the voltage drop of the light-emitting signal, which causes different light-emitting signals received by different areas of the display area, and different attenuation degrees of the light-emitting material in different areas of the display area, which causes different display brightness in different areas of the display in the subsequent display stage, and affects the display uniformity of the display device.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display panel and a display device to solve the technical problems in the prior art that different areas of the display panel have different aging degrees in an aging test stage, so that the display panel has different display luminances in different areas of the display panel in a display stage, and the display uniformity is poor.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a display region and a peripheral circuit region;
the display area is provided with a plurality of scanning signal lines, a plurality of light-emitting control signal lines, a plurality of reference signal lines and a plurality of pixel circuits which are arranged in a matrix;
the peripheral circuit region is provided with a plurality of scanning driving circuits, a plurality of light-emitting control circuits, a low-potential signal wire, a high-potential signal wire and a reference signal bus;
the scanning signal input end of the scanning driving circuit is electrically connected with the low-potential signal line and the high-potential signal line respectively, and the scanning signal output end of the scanning driving circuit is electrically connected with the scanning signal line;
the light-emitting control signal input end of the light-emitting control circuit is electrically connected with the low-potential signal wire and the high-potential signal wire respectively, and the light-emitting control signal output end of the light-emitting control circuit is electrically connected with the light-emitting control signal wire;
the reference signal bus is electrically connected with a plurality of reference signal lines;
the peripheral circuit region further comprises a plurality of aging test terminals, and at least one of the low potential signal line, the high potential signal line and the reference signal bus is electrically connected with the two aging test terminals respectively.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel according to the first aspect.
According to the display panel and the display device provided by the embodiment of the invention, at least one of the low-potential signal line, the high-potential signal line and the reference signal bus is respectively and electrically connected with the two aging test terminals to receive two different aging test signals, so that the pixel circuits in different display areas of the display panel can receive the same or similar light-emitting signals to drive the same or similar light-emitting brightness of the pixel units corresponding to the pixel circuits, the aging degrees of the pixel units in different display areas of the display panel in the aging test stage are the same or similar, the display brightness of the pixel units in different areas in the subsequent display stage is the same or similar, the display brightness uniformity of the display panel is good, and the display effect of the display panel is good.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a schematic diagram of a display panel according to the prior art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Because the light-emitting material of the OLED display has certain attenuation, the attenuation rate is high in the initial use stage, and the attenuation rate area is stable in the subsequent use stage, the aging test is generally carried out before the OLED display leaves a factory, and the rapid attenuation stage of the light-emitting material is filtered. Fig. 1 is a schematic structural diagram of a display panel in the prior art, as shown in fig. 1, the display panel includes a display area 11 and a peripheral circuit area 12, an integrated driving circuit 13 is located in the peripheral circuit area 12 and located on one side of the display area 11, since a light-emitting signal is input to a pixel unit 14 in a different area of the display area 11 through the integrated driving circuit 13, and the light-emitting signal is generally large in order to accelerate an aging test process, a large voltage drop exists in a light-emitting signal transmission line 15 (e.g., a PVDD signal line, a PVEE signal line, etc.) during a transmission process of the light-emitting signal, so that the pixel unit 14 close to the integrated circuit 13 receives a large light-emitting signal, and the pixel unit 14 far from the integrated driving circuit 13 receives a small light-emitting signal. Therefore, after the burn-in test is finished, the aging degree of the pixel unit 14 close to the integrated area circuit 13 is different from that of the pixel unit 14 far from the integrated drive circuit 13, which causes the difference between the luminance of the pixel unit 14 close to the integrated area circuit 13 and that of the pixel unit 14 far from the integrated drive circuit 13 in the subsequent display process, thereby affecting the uniformity of the luminance of the display panel and the display effect of the display panel.
Based on the above technical problem, an embodiment of the present invention provides a display area and a peripheral circuit area; the display area is provided with a plurality of scanning signal lines, a plurality of light-emitting control signal lines, a plurality of reference signal lines and a plurality of pixel circuits which are arranged in a matrix; the peripheral circuit region is provided with a plurality of scanning driving circuits, a plurality of light-emitting control circuits, a low potential signal wire, a high potential signal wire and a reference signal bus; the scanning signal input end of the scanning driving circuit is electrically connected with the low-potential signal line and the high-potential signal line respectively, and the scanning signal output end of the scanning driving circuit is electrically connected with the scanning signal line; the light-emitting control signal input end of the light-emitting control circuit is electrically connected with the low-potential signal wire and the high-potential signal wire respectively, and the light-emitting control signal output end of the light-emitting control circuit is electrically connected with the light-emitting control signal wire; the reference signal bus is electrically connected with a plurality of reference signal wires; the peripheral circuit region further comprises a plurality of aging test terminals, and at least one of the low-potential signal line, the high-potential signal line and the reference signal bus is electrically connected with the two aging test terminals respectively. By adopting the technical scheme, at least one of the low-potential signal line, the high-potential signal line and the reference signal bus is respectively and electrically connected with the two aging test terminals to receive two different aging test signals, so that the pixel circuits of different display areas of the display panel can receive the same or similar light-emitting signals to drive the pixel units corresponding to the pixel circuits to have the same or similar light-emitting brightness, the aging degrees of the pixel units of the different display areas of the display panel in the aging test stage are the same or similar, the display brightness of the pixel units of different areas in the subsequent display stage is the same or similar, the display brightness uniformity of the display panel is good, and the display effect of the display panel is good.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. Based on the embodiments of the present invention, those skilled in the art can obtain all other embodiments without creative efforts, which belong to the protection scope of the embodiments of the present invention.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 2, the display panel according to the embodiment of the present invention includes: a display region 11 and a peripheral circuit region 12; the display region 11 is provided with a plurality of scanning signal lines 111, a plurality of light emission control signal lines 112, a plurality of reference signal lines 113, and a plurality of pixel circuits 114 arranged in a matrix; the peripheral circuit region 12 is provided with a plurality of scanning drive circuits 121, a plurality of light emission control circuits 122, a low potential signal line 123, a high potential signal line 124, and a reference signal bus 125; a scanning signal input end of the scanning driving circuit 121 is electrically connected to the low-potential signal line 123 and the high-potential signal line 124, respectively, and a scanning signal output end of the scanning driving circuit 121 is electrically connected to the scanning signal line 111; a light-emitting control signal input end of the light-emitting control circuit 122 is electrically connected to the low-potential signal line 123 and the high-potential signal line 124, respectively, and a light-emitting control signal output end of the light-emitting control circuit 122 is electrically connected to the light-emitting control signal line 112; the reference signal bus 125 is electrically connected to the plurality of reference signal lines 113; the peripheral circuit region 12 further includes a plurality of burn-in test terminals 20, and at least one of the low potential signal line 123, the high potential signal line 124, and the reference signal bus line 125 is electrically connected to two of the burn-in test terminals 20, respectively.
As shown in fig. 2, the display region 11 is provided with a plurality of scanning signal lines 111, a plurality of light-emitting control signal lines 112, a plurality of reference signal lines 113, and a plurality of pixel circuits 114 arranged in a matrix, and the pixel circuits 114 arranged in the same row connect the same scanning signal line 111, the same light-emitting control signal line 112, and the same reference signal line 113, and receive the same scanning signal, light-emitting control signal, and reference signal.
The peripheral circuit region 12 is provided with a plurality of scan driving circuits 121, such as scan1, scan2, … … and scan6, which are arranged in cascade, a first scan signal input terminal of the scan driving circuit 121 is electrically connected to the low potential signal line 123, a second scan signal input terminal is electrically connected to the high potential signal line 124, and a scan signal output terminal is electrically connected to the scan signal line 111, and a scan signal including a low potential signal and a high potential signal is supplied to the pixel circuit 114 through the scan signal line 111. The peripheral circuit region 12 is further provided with a plurality of light emission control circuits 122, such as emit1, emit2, … …, and emit6 shown in the figure, in which a first light emission control signal input terminal of the light emission control circuit 122 is electrically connected to the low potential signal line 123, a second light emission control signal input terminal is electrically connected to the high potential signal line 124, and a light emission control signal output terminal is electrically connected to the light emission control signal line 112, and the light emission control signal including the low potential signal and the high potential signal is supplied to the pixel circuit 114 through the light emission control signal line 112. The reference signal bus 125 is electrically connected to the plurality of reference signal lines 113, and supplies reference signals to the pixel circuits 114 through the reference signal lines 113.
The peripheral circuit region 12 is further provided with a plurality of burn-in test terminals 20, and the plurality of burn-in test terminals 20 are configured to provide burn-in test signals to the low potential signal line 123, the high potential signal line 124 and the reference signal bus 125 during the burn-in test process, so as to complete the burn-in test process. Specifically, at least one of the low potential signal line 123, the high potential signal line 124, and the reference signal bus 125 is electrically connected to the two burn-in test terminals 20, thus, at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 can simultaneously receive two burn-in test signals with different magnitudes, so as to ensure that the pixel circuits 114 at different positions in the display area 11 of the display panel can receive the same or similar light-emitting signals to drive the corresponding pixel units to emit the same or similar light-emitting intensities, and ensure that the pixel units at different positions in the display area 11 of the display panel have the same or similar burn-in degrees in the burn-in test stage, the display brightness of the pixel units at different positions in the subsequent display stage is the same or similar, so that the uniformity of the display brightness of the display panel is good, and the display effect of the display panel is good. Specifically, the low potential signal line 123 shown in fig. 2 is electrically connected to two burn-in test terminals 20, and the low potential signal line 123 receives two burn-in test signals having different sizes, thus different scanning signals are supplied to the pixel circuits 114 at different positions of the display panel through the scanning drive circuit 121, or different light emission control signals are supplied to the pixel circuits 114 at different positions of the display panel through the light emission control circuit 122, the pixel units corresponding to the pixel circuits 114 at different positions of the display panel are controlled by different scanning signals or light-emitting control signals to have the same or similar light-emitting degrees and the same or similar aging degrees in the aging test process, so that in the display stage after the aging test stage, the light emitting degrees of the pixel units at different positions are the same, and the display uniformity of the display panel is good.
Optionally, at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 is electrically connected to the two burn-in test terminals 20, which may include various implementations. In one implementation, as shown in fig. 2, the burn-in test terminal 20 includes a first test terminal portion 21 and a second test terminal portion 22, the first test terminal portion 21 and the second test terminal portion 22 are respectively located at two opposite sides of the display area 11, the arrangement is only required to respectively arrange the first test terminal portion 21 and the second test terminal portion 22 at two opposite sides of the display area 11, and at least one of the low potential signal line 123, the high potential signal line 124 and the reference signal bus line 125 is electrically connected to the first test terminal portion 21 and the second test terminal portion 22, so that the implementation is simple. Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 3 illustrates an example in which the low-potential signal line 123 and the burn-in test signal line 30 are electrically connected at a side away from the burn-in test terminal 20. As shown in fig. 3, the aging test terminals 20 are located on the same side of the display area 11, the display panel further includes at least one aging test signal line 30, one end of the aging test signal line 30 is connected to one aging test terminal 20, and the other end of the aging test signal line is electrically connected to one of the low-potential signal line 123, the high-potential signal line 124 or the reference signal bus 125 far away from the aging test terminal 20, so that at least one of the low-potential signal line 123, the high-potential signal line 124 or the reference signal bus 125 can be simultaneously connected to two aging test signals, and the setting mode can input the aging test signals from only one side of the display area 11, and the aging test signals are provided in a simple manner. The embodiment of the present invention does not limit how to electrically connect at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 to the two aging test terminals 20, and only needs to ensure that at least one of the low-potential signal line 123, the high-potential signal line 124 or the reference signal bus 125 can be connected to two different aging test signals at the same time, so as to ensure that the pixel circuits 114 at different positions in the display area 11 of the display panel can receive the same or similar aging test signals, and that the aging degrees of the pixel units at different positions in the display area 11 of the display panel at the aging test stage are the same or similar.
Next, how to electrically connect the two aging test terminals 20 through at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 respectively, so that the pixel circuits 114 at different positions in the display area 11 of the display panel can receive the same or similar light-emitting signals will be described.
Fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 4 and fig. 5, the pixel circuit 114 includes a first P-type thin film transistor T1 and a second P-type thin film transistor T2, and the light emission control signal line 112 is electrically connected to control terminals of the first P-type thin film transistor T1 and the second P-type thin film transistor T2, respectively; the low potential signal line 123 is electrically connected to the first aging test terminal 201 and the second aging test terminal 202, respectively; the low potential signal line 123 includes a first sub-low potential signal line 1231 and a second sub-low potential signal line 1232, wherein one end of the first sub-low potential signal line 1231 and one end of the second sub-low potential signal line 1232 are electrically connected to the first burn-in test terminal 201, and the other end of the first sub-low potential signal line 1231 is electrically connected to the second burn-in test terminal 202; the first sub low potential signal line 1231 is electrically connected to the plurality of light emission control signal input terminals, and the second sub low potential signal line 1232 is electrically connected to the plurality of scanning signal input terminals; the display panel includes an aging stage in which a first low potential signal VGL1 is connected to the first aging test terminal 201, and a second low potential signal VGL2 is connected to the second aging test terminal 202, wherein VGL2< VGL1< 0.
Illustratively, when the pixel circuit 114 includes the first and second P-type thin film transistors T1 and T2 and the driving control signals of the first and second P-type thin film transistors T1 and T2 are less than 0, the first and second P-type thin film transistors T1 and T2 are turned on; and the first and second P-type thin film transistors T1 and T2 operate in a linear region during an aging period.
As shown in fig. 5, since the second aging terminal 202 is close to the emission control circuit EMIT1 and the first aging terminal 201 is close to the emission control circuit EMIT6, the EMIT1 signal output from the emission control circuit EMIT1 is closer to the second low-potential signal VGL2 connected to the second aging terminal 202, and the EMIT6 signal output from the emission control circuit EMIT6 is closer to the second low-potential signal VGL1 connected to the first aging terminal 201, so that the emission control signal EMIT1 output from the emission control circuit EMIT1 and the emission control signal EMIT6 output from the emission control circuit EMIT6 satisfy EMIT1< EMIT6<0 when the first low-potential signal VGL1 connected to the first aging test terminal 201 and the second low-potential signal VGL2 connected to the second aging test terminal 202 satisfy VGL2< VGL1< 0. Meanwhile, since the first P-type thin film transistor T1 and the second P-type thin film transistor T2 operate in a linear region in an aging stage, the first P-type thin film transistor T1 and the second P-type thin film transistor T2 are turned on to a greater extent in the entire row of the pixel circuit 114 controlled by the emission control signal EMIT1, and the first P-type thin film transistor T1 and the second P-type thin film transistor T2 are turned on to a lesser extent in the entire row of the pixel circuit 114 controlled by the emission control signal EMIT 6.
As shown in fig. 4, since the first P-type tft T1 and the second P-type tft T2 are located on the transmission line of the PVDD signal, the first P-type tft T1 and the second P-type tft T2 in the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 are turned on to a greater extent, so that more emission signals (PVDD signals) can be transmitted to the pixel units (OLEDs), which can make up for the problem of a larger voltage drop caused by the fact that the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 is located at a side far away from the integrated driving circuit 13, ensure that the emission signal received by the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 is the same as or similar to the emission signal received by the entire row of pixel circuits 114 controlled by the emission control signal EMIT6, ensure that the same or similar emission signals can be received by the entire display panel from the pixel circuits 114 at different positions of the integrated driving circuit 13, the brightness of the pixel units in the whole display panel is guaranteed to be the same or similar, the aging degree of the pixel units in the aging stage is the same or similar, and therefore the brightness of the pixel units in the whole display panel is guaranteed to be the same in the display stage after the aging stage, and the display uniformity of the display panel is guaranteed to be good.
Optionally, with reference to fig. 5, in the display panel according to the embodiment of the present invention, the peripheral circuit region 12 is further provided with a plurality of display test terminals 40, and the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 are respectively connected to one display test terminal 40, and are configured to receive a display test signal in a display test stage, where the aging test terminal 20 multiplexes a part of the display test terminals 40.
For example, before or after the aging stage, the display panel needs to be subjected to a display test (VT test) to check the display performance of the display panel. The aging test terminal 20 can multiplex part of the display test terminals 40, or the display test terminal 40 can multiplex the aging test terminal 20, so that the arrangement modes of various signal terminals in the peripheral circuit region 12 of the display panel are simple, the number of various signal terminals is reduced, the area of the peripheral circuit region 12 is reduced, and the narrow frame design of the display panel is facilitated.
Further, in the display test phase, the potential on the second aging test terminal 202 is the same as the potential on the first aging test terminal 201, or the potential on the second aging test terminal 202 is floated.
For example, the display panel provided in the embodiment of the present invention only requires that the burn-in test signals on the first burn-in test terminal 201 and the second burn-in test terminal 202 are different in the burn-in stage, and by inputting different burn-in test signals to at least one of the low-potential signal line 123, the high-potential signal line 124, and the reference signal bus 125, it is ensured that different specific pixel circuits 114 of specific integrated driving circuits 13 in the display panel can receive the same or similar light-emitting signals; in other stages, for example, the display test terminal, the potential at the second aging test terminal 202 is the same as the potential at the first aging test terminal 201, or the potential at the second aging test terminal 202 is floating, and it is not necessary to set the display test signals at the first aging test terminal 201 and the second aging test terminal 202 to be different, and the display test method is simple.
Fig. 6 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, fig. 7 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, as shown in fig. 6 and fig. 7, the pixel circuit 114 includes a first N-type thin film transistor T1 'and a second N-type thin film transistor T2', and the light emission control signal line 112 is electrically connected to the control terminals of the first N-type thin film transistor T1 'and the second N-type thin film transistor T2', respectively; the high-potential signal line 124 is electrically connected to the third burn-in test terminal 203 and the fourth burn-in test terminal 204, respectively; the high-potential signal line 124 includes a first sub high-potential signal line 1241 and a second sub high-potential signal line 1242, wherein one end of the first sub high-potential signal line 1241 and one end of the second sub high-potential signal line 1242 are electrically connected to the third burn-in test terminal 203, and the other end of the first sub high-potential signal line 1241 is electrically connected to the fourth burn-in test terminal 204; the first sub high-potential signal line 1241 is electrically connected to a plurality of light emission control signal input terminals, and the second sub high-potential signal line 1242 is electrically connected to a plurality of scanning signal input terminals; the display panel includes an aging stage in which a first high potential signal VGH1 is connected to the third aging test terminal 203, and a second high potential signal VGH2 is connected to the fourth aging test terminal 204, wherein VGH2> VGH1> 0.
Illustratively, when the pixel circuit 114 includes the first and second N-type thin film transistors T1 'and T2' and the driving control signals of the first and second N-type thin film transistors T1 'and T2' are greater than 0, the first and second N-type thin film transistors T1 'and T2' are turned on; and the first and second N-type thin film transistors T1 'and T2' operate in a linear region during an aging stage.
As shown in fig. 7, since the fourth aging terminal 204 is close to the emission control circuit EMIT1 and the third aging terminal 203 is close to the emission control circuit EMIT6, the EMIT1 signal output by the emission control circuit EMIT1 is closer to the second high-potential signal VGH2 connected to the fourth aging terminal 204, and the EMIT6 signal output by the emission control circuit EMIT6 is closer to the first high-potential signal VGH1 connected to the third aging terminal 203, so that the emission control signal EMIT1 output by the emission control circuit EMIT1 and the emission control signal EMIT6 output by the emission control circuit EMIT6 satisfy EMIT1> EMIT6>0 when the first high-potential signal VGH1 connected to the third aging test terminal 203 and the second high-potential signal VGH2 connected to the fourth aging test terminal 204 satisfy VGH2> VGH1> 0. Meanwhile, since the first N-type thin film transistor T1 'and the second N-type thin film transistor T2' operate in a linear region during the aging period, the first N-type thin film transistor T1 'and the second N-type thin film transistor T2' are turned on to a greater extent in the entire row of the pixel circuit 114 controlled by the emission control signal EMIT1, and the first N-type thin film transistor T1 'and the second N-type thin film transistor T2' are turned on to a lesser extent in the entire row of the pixel circuit 114 controlled by the emission control signal EMIT 6.
As shown in fig. 6, since the first N-type thin film transistor T1 'and the second N-type thin film transistor T2' are located on the transmission line of the PVDD signal, the first N-type thin film transistor T1 'and the second N-type thin film transistor T2' in the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 are turned on to a greater extent, so that more emission signals (PVDD signals) can be transmitted to the pixel units (OLEDs), the problem of a larger voltage drop caused by the fact that the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 are located at a side far from the integrated driving circuit 13 can be solved, the emission signal received by the entire row of pixel circuits 114 controlled by the emission control signal EMIT1 is ensured to be the same or similar to the emission signal received by the entire row of pixel circuits 114 controlled by the emission control signal EMIT6, the emission signal received by the pixel circuits 114 at different positions of the integrated driving circuit 13 in the entire display panel can be ensured to be the same or similar to the emission signal, the brightness of the pixel units in the whole display panel is guaranteed to be the same or similar, the aging degree of the pixel units in the aging stage is the same or similar, and therefore the brightness of the pixel units in the whole display panel is guaranteed to be the same in the display stage after the aging stage, and the display uniformity of the display panel is guaranteed to be good.
Further, in the display test stage, the potential on the fourth burn-in test terminal 204 is the same as the potential on the third burn-in test terminal 203, or the potential on the fourth burn-in test terminal 204 floats.
For example, the display panel provided in the embodiment of the present invention only requires that the burn-in test signals on the third burn-in test terminal 203 and the fourth burn-in test terminal 204 are different in the burn-in stage, and different burn-in test signals are input to at least one of the low-potential signal line 123, the high-potential signal line 124, and the reference signal bus 125, so as to ensure that different specific pixel circuits 114 of specific integrated driving circuits 13 in the display panel can receive the same or similar light-emitting signals; in other stages, for example, the display test terminal, the potential at the fourth burn-in test terminal 204 is the same as the potential at the third burn-in test terminal 203, or the potential at the fourth burn-in test terminal 204 is floating, and it is not necessary to set the display test signals at the third burn-in test terminal 203 and the fourth burn-in test terminal 204 to be different, and the display test mode is simple.
Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 4 and 8, the pixel circuit 114 includes a third P-type thin film transistor T3 and a storage capacitor Cst, and a drain electrode of the third P-type thin film transistor T3 and a first electrode plate of the storage capacitor Cst are electrically connected at a first node N1; the scanning signal line 111 is electrically connected with the control end of the third P-type thin film transistor T3; the high-potential signal line 124 is electrically connected to the fifth burn-in test terminal 205 and the sixth burn-in test terminal 206, respectively; the high-potential signal line includes a first sub high-potential signal line 1241 and a second sub high-potential signal line 1242, wherein one end of the first sub high-potential signal line 1241 and one end of the second sub high-potential signal line 1242 are electrically connected to the sixth burn-in test terminal 206, and the other end of the second sub high-potential signal line 1242 is electrically connected to the fifth burn-in test terminal 205; the first sub high-potential signal line 1241 is electrically connected to a plurality of light emission control signal input terminals, and the second sub high-potential signal line 1242 is electrically connected to a plurality of scanning signal input terminals; the display panel comprises an aging stage, in which a third high potential signal VGH3 is connected to the fifth aging test terminal 205, and a fourth high potential signal VGH4 is connected to the sixth aging test terminal 206, wherein VGH4> VGH3> 0.
The operating principle of the pixel circuit 114 will be briefly described first: in the initialization stage, the sixth thin film transistor T6 is turned on, and the reference signal charges the storage capacitor Cst. In the data writing and compensation phase, the fourth thin film transistor T4, the fifth thin film transistor T5, and the third thin film transistor T3 are turned on, Vdata is charged in the storage capacitor Cst, and the voltage VN1 of the first node N1 is Vdata- | Vth |, where | Vth | is the threshold voltage of the fifth thin film transistor T5. At the arrival time of the light emitting period, since the scanning signal on the scanning signal line 111 changes abruptly from the low potential signal to the high potential signal, the signal change amount is VGH-VGL, and generally, a coupling capacitance Cg exists between the first node N1 and the scanning signal line 111, at this time, the potential change Δ V of the first node N1 is influenced by the jump of the scanning signal, and the potential of the first node N1 is changed to VN1+ Δ V. In the light emitting stage, the light emitting current I of the OLED is K (PVDD-Vdata-delta V)2Wherein K is a constant. Therefore, the high-potential signals on different aging test terminals 20 can affect the potential change Δ V of the node N1, and further affect the light-emitting current of the OLED and the aging degree of the OLED.
Specifically, since the fifth aging test terminal 205 is close to the SCAN drive circuit SCAN1 side and the sixth aging test terminal 206 is close to the SCAN drive circuit SCAN6 side, the SCAN1 signal output by the SCAN drive circuit SCAN1 is closer to the third high voltage signal VGH3 connected to the fifth aging test terminal 205, and the SCAN6 signal output by the SCAN drive circuit SCAN6 is closer to the fourth high voltage signal connected to the sixth aging test terminal 206The bit signal VGH4, therefore, when the third high voltage signal VGH3 connected to the fifth burn-in test terminal 205 and the fourth high voltage signal VGH4 connected to the sixth burn-in test terminal 206 satisfy VGH4>VGH3>At 0, the SCAN1 signal output by the SCAN driver circuit SCAN1 and the SCAN6 signal output by the SCAN driver circuit SCAN6 satisfy SCAN6>SCAN1>0. Therefore, the node potential change Δ V1 at the first node N1 is closer to Cg/(Cg + Cst) × (VGH3-VGL) in the entire row of pixel circuits 114 controlled by the SCAN1 signal at the transition of the SCAN signal, and the node potential change Δ V6 at the first node N1 is closer to Cg/(Cg + Cst) (VGH4-VGL) in the entire row of pixel circuits 114 controlled by the SCAN6 signal at the transition of the SCAN signal, so Δ V1<Δ V6, therefore, the SCAN1 signal controls the light emitting unit I of the pixel unit corresponding to the pixel circuit 114 in the whole row1Light emitting unit I of pixel unit corresponding to pixel circuit 114 of whole row controlled by SCAN6 signal (PVDD-Vdata- Δ V1)6K (PVDD-Vdata-delta V6) satisfies I1>I6. That is, the third high voltage signal VGH3 connected to the fifth burn-in test terminal 205 and the fourth high voltage signal VGH4 connected to the sixth burn-in test terminal 206 are set to satisfy VGH4>VGH3>0, it can be ensured that the light-emitting signals received by the pixel circuits 114 in the whole row controlled by the SCAN1 signal are the same as or similar to the light-emitting signals received by the pixel circuits 114 in the whole row controlled by the SCAN6 signal, it can be ensured that the pixel circuits 114 in different positions of the whole display panel from the integrated driving circuit 13 can receive the same or similar light-emitting signals, it is ensured that the light-emitting brightness of the pixel units in the whole display panel is the same or similar, the aging degree of the pixel units in the aging stage is the same or similar, it is further ensured that the light-emitting brightness of the pixel units in the whole display panel is the same in the display stage after the aging stage, and it is ensured that the display uniformity of the display panel is good.
Further, in the display test stage, the potential on the fifth aging test terminal 205 is the same as the potential on the sixth aging test terminal 206, or the potential on the fifth aging test terminal 205 is floated.
For example, the display panel according to the embodiment of the present invention only requires that the burn-in test signals on the fifth burn-in test terminal 205 and the sixth burn-in test terminal 206 are different in the burn-in stage, and different burn-in test signals are input to at least one of the low-potential signal line 123, the high-potential signal line 124, and the reference signal bus 125, so as to ensure that different specific pixel circuits 114 of specific integrated driving circuits 13 in the display panel can receive the same or similar light-emitting signals; in other stages, for example, the display test terminal, the potential at the fifth aging test terminal 205 is the same as the potential at the sixth aging test terminal 206, or the potential at the fifth aging test terminal 205 may float, and the display test mode is simple without setting the display test signals at the fifth aging test terminal 205 and the sixth aging test terminal 206 to be different.
Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 6 and 9, the pixel circuit 114 includes a third N-type thin film transistor T3 'and a storage capacitor Cst, and a source electrode of the third N-type thin film transistor T3' and a first electrode plate of the storage capacitor Cst are electrically connected at a first node N1; the scanning signal line 111 is electrically connected with the control end of the third N-type thin film transistor T3'; the low potential signal line 123 is electrically connected to the seventh burn-in test terminal 207 and the eighth burn-in test terminal 208, respectively; the low potential signal lines include a first sub-low potential signal line 1231 and a second sub-low potential signal line 1232, wherein one ends of the first sub-low potential signal line 1231 and the second sub-low potential signal line 1232 are electrically connected to the eighth burn-in test terminal 208, respectively, and the other end of the second sub-low potential signal line 1232 is electrically connected to the seventh burn-in test terminal 207; the first sub low potential signal line 1231 is electrically connected to the plurality of light emission control signal input terminals, and the second sub low potential signal line 1232 is electrically connected to the plurality of scanning signal input terminals; the display panel includes an aging stage in which the seventh aging test terminal 207 is connected to the third low potential signal VGL3, and the eighth aging test terminal 208 is connected to the fourth low potential signal VGL4, wherein VGL4< VGL3< 0.
The operating principle of the pixel circuit 114 will be briefly described first: in the initialization stage, the sixth thin film transistor T6' is turned on, and the reference signal charges the storage capacitor Cst. In the data writing and compensation phase, the fourth thin film transistor T4 ', the fifth thin film transistor T5' and the third thin film transistor T3 'are turned on, Vdata is charged in the storage capacitor Cst, and the voltage VN1 of the first node N1 is Vdata- | Vth |, where | Vth | is the threshold voltage of the fifth thin film transistor T5'. At the arrival time of the light emitting period, since the scanning signal on the scanning signal line 111 changes abruptly from the high potential signal to the low potential signal, the signal change amount is VGH-VGL, and generally, a coupling capacitance Cg exists between the first node N1 and the scanning signal line 111, at this time, the potential change Δ V of the first node N1 is influenced by the jump of the scanning signal, and the potential of the first node N1 is changed to VN1+ Δ V. In the light emitting stage, the light emitting current I of the OLED is K (PVDD-Vdata- Δ V), where K is a constant. Therefore, the low potential signals on different aging test terminals 20 can affect the potential change Δ V of the node N1, and further affect the light emitting current of the OLED, and the aging degree of the OLED.
Specifically, since the seventh burn-in test terminal 207 is close to the SCAN driving circuit SCAN1 and the eighth burn-in test terminal 208 is close to the SCAN driving circuit SCAN6, the SCAN driving circuit SCAN1 outputs a SCAN1 signal closer to the third low potential signal VGL3 connected to the seventh burn-in test terminal 207, and the SCAN driving circuit SCAN6 outputs a SCAN6 signal closer to the fourth low potential signal VGL4 connected to the eighth burn-in test terminal 208, so that when the third low potential signal VGL3 connected to the seventh burn-in test terminal 207 and the fourth low potential signal VGL4 connected to the eighth burn-in test terminal 208 meet the requirements of VGL4<VGL3<At 0, the SCAN1 signal output by the SCAN driver circuit SCAN1 and the SCAN6 signal output by the SCAN driver circuit SCAN6 satisfy SCAN6<SCAN1<0. Therefore, the node potential change Δ V1 at the first node N1 is closer to Cg/(Cg + Cst) × (VGH-VGL3) in the entire row of pixel circuits 114 controlled by the SCAN1 signal at the transition of the SCAN signal, and the node potential change Δ V6 at the first node N1 is closer to Cg/(Cg + Cst) (VGH-VGL4) in the entire row of pixel circuits 114 controlled by the SCAN6 signal at the transition of the SCAN signal, so Δ V1<Δ V6, therefore, the SCAN1 signal controls the light emitting unit I of the pixel unit corresponding to the pixel circuit 114 in the whole row1Light emitting unit of pixel unit corresponding to pixel circuit 114 of whole row controlled by SCAN6 signal (PVDD-Vdata- Δ V1)I6K (PVDD-Vdata-delta V6) satisfies I1>I6. That is, the VGL4 is satisfied by the third low potential signal VGL3 connected to the seventh burn-in test terminal 207 and the fourth low potential signal VGL4 connected to the eighth burn-in test terminal 208<VGL3<0, it can be ensured that the light-emitting signals received by the pixel circuits 114 in the whole row controlled by the SCAN1 signal are the same as or similar to the light-emitting signals received by the pixel circuits 114 in the whole row controlled by the SCAN6 signal, it can be ensured that the pixel circuits 114 in different positions of the whole display panel from the integrated driving circuit 13 can receive the same or similar light-emitting signals, it is ensured that the light-emitting brightness of the pixel units in the whole display panel is the same or similar, the aging degree of the pixel units in the aging stage is the same or similar, it is further ensured that the light-emitting brightness of the pixel units in the whole display panel is the same in the display stage after the aging stage, and it is ensured that the display uniformity of the display panel is good.
Further, in the display test stage, the potential on the seventh burn-in test terminal 207 is the same as the potential on the eighth burn-in test terminal 208, or the potential on the seventh burn-in test terminal 207 floats.
For example, the display panel provided in the embodiment of the present invention requires different burn-in test signals on the seventh burn-in test terminal 207 and the eighth burn-in test terminal 208 only in the burn-in stage, and by inputting different burn-in test signals to at least one of the low-potential signal line 123, the high-potential signal line 124, and the reference signal bus 125, different specific pixel circuits 114 of specific integrated driving circuits 13 in the display panel can receive the same or similar light-emitting signals; in other stages, for example, the display test terminal, the potential at the seventh burn-in test terminal 207 is the same as the potential at the eighth burn-in test terminal 208, or the potential at the seventh burn-in test terminal 207 may float, and the display test mode is simple without setting the display test signals at the seventh burn-in test terminal 207 and the eighth burn-in test terminal 208 to be different.
Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 4, 6 and 10, a pixel circuit 114 includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a storage capacitor, and a reference signal line 113, the third thin film transistor and a first electrode plate of the storage capacitor are electrically connected at a first node; the fourth thin film transistor and the fifth thin film transistor are electrically connected at a second node, and the scanning signal line 111 is electrically connected with the third thin film transistor and the control end of the fourth thin film transistor; both ends of the reference signal bus 125 are electrically connected to the ninth burn-in test terminal 209 and the tenth burn-in test terminal 210, respectively; the display panel includes an aging stage, in which a first reference signal VREF1 is connected to the ninth aging test terminal 209, and a second reference signal VREF2, | VREF2| > | VREF1| is connected to the tenth aging test terminal 210, wherein the polarities of the first reference signal VREF1 and the second reference signal VREF2 are the same.
When the tfts included in the pixel circuit 114 are all P-type tfts, VREF2< VREF1< 0; when the thin film transistors included in the pixel circuit 114 are all N-type thin film transistors, VREF2> VREF1>0 at this time.
Specifically, when the thin film transistors included in the pixel circuit 114 are all P-type thin film transistors, as shown in fig. 4, the third thin film transistor and the first electrode plate of the storage capacitor are electrically connected at the first node, which means that the drain electrode of the third P-type thin film transistor T3 and the first electrode plate of the storage capacitor Cst are electrically connected at the first node N1; the fourth thin film transistor and the fifth thin film transistor are electrically connected at the second node may be understood that the drain electrode of the fourth P-type thin film transistor T4 and the source electrode of the fifth P-type thin film transistor T5 are electrically connected at the second node N2. When the thin film transistors included in the pixel circuit 114 are all N-type thin film transistors, the third thin film transistor and the first electrode plate of the storage capacitor are electrically connected at the first node, which means that the source electrode of the third N-type thin film transistor T3' and the first electrode plate of the storage capacitor Cst are electrically connected at the first node N1; the fourth thin film transistor and the fifth thin film transistor are electrically connected at the second node may be understood that the source electrode of the fourth N-type thin film transistor T4 'and the drain electrode of the fifth N-type thin film transistor T5' are electrically connected at the second node N2.
Next, the thin film transistors in the pixel circuit 114 are all P-type thin film transistors.
According to the operation principle of the pixel circuit 114, after the initial stage is finished, the voltage of the first node N1 is VREF; in the data writing and compensation stage, the fourth thin film transistor T4, the fifth thin film transistor T5 and the third thin film transistor T3 are turned on, the voltage of the second node N2 node VN2 is Vdata, and at this time, the capacitor is charged, and the potential at the point N1 is increased; in the threshold capture phase, the potential at the NI point changes by Δ N1, and at the end of the threshold capture phase, the potential at the N1 point is VN1 ═ VREF + Δn 1. Therefore, by setting different VREF, different potential of point N1, that is, the gate potential of the fifth thin film transistor T5, can be obtained. In the light emitting stage, the light emitting current I of the OLED is K (Vgs-Vth)2The width-to-length ratio of the channel region in the K thin film transistor is a constant, Vgs is the gate-source voltage of the fifth thin film transistor T5, and the source voltage of the fifth thin film transistor T5 is a constant value Vdata; vth is a fixed value of the threshold voltage of the fifth thin film transistor T5, so that different gate potentials of the fifth thin film transistor T5 can be obtained by setting different VREF potentials, thereby obtaining different light emitting currents of the OLED corresponding to different aging degrees of the OLED.
VREF2 is satisfied by the second reference signal VREF2 at the tenth burn-in terminal 210 and the first reference signal VREF1 at the ninth burn-in terminal 209<VREF1<0, and therefore, the light emitting current I of the OLED in the pixel circuit 114 near the tenth aging terminal 210 side1＝K(Vgs-Vth)2And the light emitting current I of the OLED in the pixel circuit 114 near the ninth aging terminal 2092＝K(Vgs-Vth)2Satisfy I1>I2. Since the tenth burn-in terminal 210 is located at a side far from the integrated driver circuit 10, the second reference signal VREF2 provided on the tenth burn-in terminal 210 and the first reference signal VREF1 provided on the ninth burn-in terminal 209 satisfy VREF2<VREF1<0 can compensate the problem of small light-emitting signal due to voltage drop of the pixel circuit 114 far away from the integrated driving circuit 13, and ensure that the light-emitting signal received by the pixel circuit 114 far away from the integrated driving circuit 13 and the light-emitting signal received by the pixel circuit 114 near the integrated driving circuit 13 are both smallThe signals are the same or similar, so that it is ensured that the pixel circuits 114 at different positions of the whole display panel from the integrated driving circuit 13 can receive the same or similar light-emitting signals, and that the light-emitting brightness of the pixel units in the whole display panel is the same or similar, and the aging degrees of the pixel units in the aging stage are the same or similar, so as to ensure that the light-emitting brightness of the pixel units in the whole display panel is the same in the display stage after the aging stage, and ensure that the display uniformity of the display panel is good.
Further, in the display test stage, the potential on the tenth burn-in test terminal 210 is the same as the potential on the ninth burn-in test terminal 209, or the potential on the tenth burn-in test terminal 210 floats.
For example, the display panel provided in the embodiment of the present invention requires different burn-in test signals on the tenth burn-in test terminal 210 and the ninth burn-in test terminal 209 only in the burn-in stage, and by inputting different burn-in test signals to at least one of the low-potential signal line 123, the high-potential signal line 124, and the reference signal bus 125, it is ensured that different specific pixel circuits 114 of specific integrated driving circuits 13 in the display panel can receive the same or similar light-emitting signals; in other stages, for example, the display test terminal, the potential at the tenth burn-in test terminal 210 is the same as the potential at the ninth burn-in test terminal 209, or the potential at the tenth burn-in test terminal 210 may float, and the display test mode is simple without setting the display test signals at the tenth burn-in test terminal 210 and the ninth burn-in test terminal 209 to be different.
In summary, the above embodiments describe in detail how the pixel circuits 114 at different positions in the display area 11 of the display panel can receive the same or similar light-emitting signals by electrically connecting at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 to the two burn-in test terminals 20, and based on the above description, it can be known that by providing at least one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 to be electrically connected to the two burn-in test terminals 20 respectively and receive two different burn-in test signals, it is ensured that the pixel circuits in different display areas of the display panel can receive the same or similar light-emitting signals and drive the same or similar pixel units, thereby ensuring that the pixel units in different display areas of the display panel have the same or similar degree of burn-in test stage, in the subsequent display stage, the display brightness of the pixel units in different areas is the same or similar, so that the uniformity of the display brightness of the display panel is good, and the display effect of the display panel is good. Meanwhile, the embodiment also explains the signal requirements on each aging test terminal in the display detection stage, so that the display test mode is simple. It should be noted that, in the embodiment of the present invention, only one of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 is electrically connected to the two burn-in test terminals 20 respectively, and two different burn-in test signals are received as an example for description, it can be understood that when two or three of the low-potential signal line 123, the high-potential signal line 124 and the reference signal bus 125 are electrically connected to the two burn-in test terminals 20 respectively, the same technical effect can be achieved as well, and no further description is provided herein.
Optionally, with continued reference to fig. 2, fig. 3, fig. 5, fig. 7, fig. 8, fig. 9, and fig. 10, an integrated driving circuit 13 is further disposed in the peripheral circuit region 12 of the display panel according to the embodiment of the present invention; the low-potential signal line 123 is electrically connected to the integrated driving circuit 13, and is configured to receive a low-potential signal during the display phase; the high-potential signal line 124 is electrically connected to the integrated driving circuit 13, and is used for receiving a high-potential signal in the display stage; the reference signal bus 125 is electrically connected to the integrated driving circuit 13, and is used for receiving the reference signal in the display stage, so as to ensure that the display panel can realize normal display.
Optionally, in the case that the burn-in test terminals 20 are located on the same side of the display area 11 and the burn-in test signal line 30 is further included in the display peripheral circuit area 12, the burn-in test signal line 30 and the low-potential signal line 123, the high-potential signal line 124 or the reference signal bus 125 electrically connected thereto are located on the same side of the display area 11, as shown in fig. 3; alternatively, the display area 11 may be located on two opposite sides of the display area, as shown in fig. 11, which is not limited in this embodiment of the present invention.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, fig. 12 is a schematic diagram of the display device provided in the embodiment of the present invention, and the display device 100 provided in the embodiment of the present invention includes the display panel 101 according to any embodiment of the present invention. Optionally, the display device provided in the embodiment of the present invention may be a mobile phone shown in fig. 12, or may also be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that the features of the various embodiments of the invention may be partially or fully coupled to each other or combined and may be capable of cooperating with each other in various ways and of being technically driven. Numerous variations, rearrangements, combinations, and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (11)

1. A display panel, comprising:
a display region and a peripheral circuit region;
the display area is provided with a plurality of scanning signal lines, a plurality of light-emitting control signal lines, a plurality of reference signal lines and a plurality of pixel circuits which are arranged in a matrix;
the peripheral circuit region is provided with a plurality of scanning driving circuits, a plurality of light-emitting control circuits, a low-potential signal wire, a high-potential signal wire and a reference signal bus;
the scanning signal input end of the scanning driving circuit is electrically connected with the low-potential signal line and the high-potential signal line respectively, and the scanning signal output end of the scanning driving circuit is electrically connected with the scanning signal line;
the light-emitting control signal input end of the light-emitting control circuit is electrically connected with the low-potential signal wire and the high-potential signal wire respectively, and the light-emitting control signal output end of the light-emitting control circuit is electrically connected with the light-emitting control signal wire;
the reference signal bus is electrically connected with a plurality of reference signal lines;
the peripheral circuit region further comprises a plurality of aging test terminals, and at least one of the low-potential signal line, the high-potential signal line and the reference signal bus is electrically connected with the two aging test terminals respectively; in the aging stage, two aging test terminals electrically connected with the same signal line respectively provide different aging test signals;
the pixel circuit comprises a first P-type thin film transistor and a second P-type thin film transistor, and the light-emitting control signal line is electrically connected with the control ends of the first P-type thin film transistor and the second P-type thin film transistor respectively; the low potential signal wire is electrically connected with the first aging test terminal and the second aging test terminal respectively; the low potential signal line comprises a first sub low potential signal line and a second sub low potential signal line, wherein one end of the first sub low potential signal line and one end of the second sub low potential signal line are electrically connected with the first aging test terminal respectively, and the other end of the first sub low potential signal line is electrically connected with the second aging test terminal; the first sub low potential signal line is electrically connected with a plurality of the light-emitting control signal input ends, and the second sub low potential signal line is electrically connected with a plurality of the scanning signal input ends; the display panel comprises an aging stage, wherein a first low potential signal VGL1 is connected to the first aging test terminal, and a second low potential signal VGL2 is connected to the second aging test terminal, wherein VGL2< VGL1< 0;
or the pixel circuit comprises a first N-type thin film transistor and a second N-type thin film transistor, and the light-emitting control signal line is electrically connected with the control ends of the first N-type thin film transistor and the second N-type thin film transistor respectively; the high-potential signal wire is electrically connected with the third aging test terminal and the fourth aging test terminal respectively; the high-potential signal line comprises a first sub high-potential signal line and a second sub high-potential signal line, wherein one end of the first sub high-potential signal line and one end of the second sub high-potential signal line are electrically connected with the third aging test terminal respectively, and the other end of the first sub high-potential signal line is electrically connected with the fourth aging test terminal; the first sub high-potential signal line is electrically connected with a plurality of light-emitting control signal input ends, and the second sub high-potential signal line is electrically connected with a plurality of scanning signal input ends; the display panel comprises an aging stage, wherein a first high potential signal VGH1 is connected to the third aging test terminal, and a second high potential signal VGH2 is connected to the fourth aging test terminal, wherein VGH2> VGH1> 0;
or the pixel circuit comprises a third P-type thin film transistor and a storage capacitor, and the drain electrode of the third P-type thin film transistor and the first electrode plate of the storage capacitor are electrically connected at a first node; the scanning signal line is electrically connected with the control end of the third P-type thin film transistor; the high-potential signal wire is electrically connected with the fifth aging test terminal and the sixth aging test terminal respectively; the high-potential signal line comprises a first sub high-potential signal line and a second sub high-potential signal line, wherein one end of the first sub high-potential signal line and one end of the second sub high-potential signal line are electrically connected with the sixth aging test terminal respectively, and the other end of the second sub high-potential signal line is electrically connected with the fifth aging test terminal; the first sub high-potential signal line is electrically connected with a plurality of light-emitting control signal input ends, and the second sub high-potential signal line is electrically connected with a plurality of scanning signal input ends; the display panel comprises an aging stage, wherein a third high potential signal VGH3 is connected to the fifth aging test terminal, and a fourth high potential signal VGH4 is connected to the sixth aging test terminal, wherein VGH4> VGH3> 0;
or the pixel circuit comprises a third N-type thin film transistor and a storage capacitor, and the source electrode of the third N-type thin film transistor and the first electrode plate of the storage capacitor are electrically connected at a first node; the scanning signal line is electrically connected with the control end of the third N-type thin film transistor; the low potential signal wire is electrically connected with the seventh aging test terminal and the eighth aging test terminal respectively; the low potential signal line comprises a first sub low potential signal line and a second sub low potential signal line, wherein one end of the first sub low potential signal line and one end of the second sub low potential signal line are electrically connected with the eighth aging test terminal respectively, and the other end of the second sub low potential signal line is electrically connected with the seventh aging test terminal; the first sub low potential signal line is electrically connected with a plurality of the light-emitting control signal input ends, and the second sub low potential signal line is electrically connected with a plurality of the scanning signal input ends; the display panel comprises an aging stage, wherein a third low potential signal VGL3 is connected to the seventh aging test terminal, and a fourth low potential signal VGL4 is connected to the eighth aging test terminal, wherein VGL4< VGL3< 0;
or the pixel circuit comprises a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a storage capacitor, wherein the reference signal line, the third thin film transistor and a first electrode plate of the storage capacitor are electrically connected at a first node; the fourth thin film transistor and the fifth thin film transistor are electrically connected at a second node, and the scanning signal line is electrically connected with the control ends of the third thin film transistor and the fourth thin film transistor; two ends of the reference signal bus are electrically connected with the ninth aging test terminal and the tenth aging test terminal respectively; the display panel comprises an aging stage, wherein a first reference signal VREF1 is connected to the ninth aging test terminal, a second reference signal VREF2, | VREF2| > | VREF1| is connected to the tenth aging test terminal, and the polarities of the first reference signal VREF1 and the second reference signal VREF2 are the same.
2. The display panel according to claim 1, wherein when the two burn-in test terminals include the first burn-in test terminal and a second burn-in test terminal, the display panel further comprises a display test stage in which a potential at the second burn-in test terminal is the same as a potential at the first burn-in test terminal or a potential at the second burn-in test terminal is floating.
3. The display panel according to claim 1, wherein when the two burn-in test terminals include the third burn-in test terminal and a fourth burn-in test terminal, the display panel further comprises a display test stage in which a potential at the fourth burn-in test terminal is the same as a potential at the third burn-in test terminal or a potential at the fourth burn-in test terminal is floated.
4. The display panel according to claim 1, wherein when the two burn-in test terminals include the fifth burn-in test terminal and a sixth burn-in test terminal, the display panel further comprises a display test stage in which a potential at the fifth burn-in test terminal is the same as a potential at the sixth burn-in test terminal or a potential at the fifth burn-in test terminal floats.
5. The display panel according to claim 1, wherein when the two burn-in test terminals include the seventh burn-in test terminal and an eighth burn-in test terminal, the display panel further comprises a display test stage in which a potential at the seventh burn-in test terminal is the same as a potential at the eighth burn-in test terminal or a potential at the seventh burn-in test terminal is floated.
6. The display panel according to claim 1, wherein when the two burn-in test terminals include the ninth burn-in test terminal and a tenth burn-in test terminal, the display panel further comprises a display test stage in which a potential at the tenth burn-in test terminal is the same as a potential at the ninth burn-in test terminal or a potential at the tenth burn-in test terminal is floated.
7. The display panel according to claim 1, wherein the plurality of burn-in test terminals are located on the same side of the display region, the display panel further comprising at least one burn-in test signal line, one end of the burn-in test signal line being connected to one of the burn-in test terminals, and the other end of the burn-in test signal line being electrically connected to the low potential signal line, the high potential signal line, or the reference signal bus line on a side away from the burn-in test terminal;
or the aging test terminal comprises a first test terminal part and a second test terminal part, and the first test terminal part and the second test terminal part are respectively positioned at two opposite sides of the display area.
8. The display panel according to claim 7, wherein the burn-in test signal line and the low potential signal line, the high potential signal line, or the reference signal bus line electrically connected thereto are located on a same side of the display region, or on opposite sides of the display region, respectively.
9. The display panel according to claim 1, wherein the peripheral circuit region is further provided with an integrated driving circuit;
the low potential signal wire is electrically connected with the integrated drive circuit and is used for receiving a low potential signal in a display stage;
the high-potential signal line is electrically connected with the integrated drive circuit and is used for receiving a high-potential signal in the display stage;
the reference signal bus is electrically connected with the integrated drive circuit and used for receiving a reference signal in the display stage.
10. The display panel according to claim 1, wherein the peripheral circuit region further includes a plurality of display test terminals, and the low potential signal line, the high potential signal line and the reference signal bus are respectively connected to a display test terminal for receiving a display test signal during a display test phase;
the aging test terminal multiplexes part of the display test terminal.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.
CN201910579039.6A 2019-06-28 2019-06-28 Display panel and display device Active CN110189703B (en)

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