CN114238175A

CN114238175A - Solid state disk FTL algorithm address mapping method

Info

Publication number: CN114238175A
Application number: CN202111553644.XA
Authority: CN
Inventors: 王志奇; 何欣霖; 何卫国
Original assignee: Chengdu 30javee Microelectronics Co ltd
Current assignee: Chengdu 30javee Microelectronics Co ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-03-25

Abstract

The invention provides an FTL algorithm address mapping method of a solid state disk, aiming at the solid state disk consisting of N NAND flashes, uniformly managing each page of the N NAND flashes according to page address sequence numbers, defining a logical page set and a physical page set, wherein one page set represents the set of the M page sequence numbers of the N NAND flashes, and the mapping from a logical address to a physical address is represented by the mapping relation from the logical page set to the physical page set; and M is less than or equal to the total number of physical pages of each NAND Flash. The scheme of the invention can obviously reduce the consumed resources, has no relation with the number of NAND Flash, and can finish the high-efficiency address mapping algorithm only by consuming fixed resources no matter how many NAND Flash exist in the solid state disk.

Description

Solid state disk FTL algorithm address mapping method

Technical Field

The invention relates to the field of memories, in particular to an address mapping method for a solid state disk (FTL) algorithm.

Background

The rapid development of the semiconductor industry appears a high-performance memory NAND Flash, the NAND Flash memory uses a semiconductor as a storage medium, has the advantages of high speed, low energy consumption, shock resistance and the like, and a basic storage unit of the NAND Flash is formed by blocks (Block). Each block is in turn made up of several pages (pages). The minimum read/write unit is a page, the minimum erase unit is a block, and before a page is programmed, the block where the page is located needs to be erased. Due to the characteristic of the NAND Flash, the NAND Flash cannot perform the original writing operation, and data needs to be written into a replacement page, which needs support of an FTL algorithm, and one of core modules of the FTL algorithm is an address mapping module.

In order to pursue high performance, most page mapping mechanisms are adopted, and in such mapping mechanisms, since the NAND Flash mapping table represents a mapping relationship from a Logical Page Address (LPA) to a Physical Page Address (PPA), the PPA can be conveniently found through the LPA. For NAND Flash, the larger the capacity, the larger the address mapping table, for example, for a series of 256GB capacity NAND Flash of L85C (see fig. 1), this type of NAND Flash has 33536 blocks, each block has 512 pages, i.e. a total of 33536 × 512 to 17170432 pages, and a total of 17170432 entries are required for the page mapping table. For a large-capacity SSD, a general solid state disk with 2TB capacity needs 8 NAND flashes of the model, and needs 17170432 × 8-137363456 entries, each entry is represented by 4Byte data, and occupies 137363456 × 4-549453824 Bytes (524MB) data space, which is impractical for a solid state disk controller with limited resources, so that when a page address mapping algorithm is adopted, all entries are not loaded in a RAM inside a controller, but a CACHE mechanism is adopted to store part of page tables in the RAM, so that the advantages and disadvantages of the algorithm are related to the design of CACHE, but no matter how the CACHE is designed, the loading and rewriting of CACHE takes time, which causes performance loss.

Disclosure of Invention

Aiming at the problems in the prior art, the FTL algorithm address mapping method for the solid state disk is provided, the page mapping algorithm can be realized under the condition of limited resources, only one table entry is needed to represent the mapping relation of N pages, and the needed memory resource is one of 1/N of the previous mapping algorithm.

The technical scheme adopted by the invention is as follows: an FTL algorithm address mapping method of a solid state disk is characterized in that aiming at a solid state disk consisting of N NAND flashes, each page of the N NAND flashes is managed uniformly according to page address serial numbers, a logical page set and a physical page set are defined, one page set represents a set of M page serial numbers of the N NAND flashes, and mapping from a logical address to a physical address is represented through a mapping relation from the logical page set to the physical page set; and M is less than or equal to the total number of physical pages of each NAND Flash.

Further, a data structure L2P _ PAGE _ SET [ M ] is defined to store a mapping relationship from a logical PAGE SET LOGIC _ PAGE _ SET [ M ] to a PHYSICAL PAGE SET PHYSICAL _ PAGE _ SET [ M ], where the logical PAGE SET LOGIC _ PAGE _ SET [ M ] and the PHYSICAL PAGE SET PHYSICAL _ PAGE _ SET [ M ] respectively represent a SET of logical and PHYSICAL M-th PAGE indexes of N pieces of NAND Flash in the solid state disk, i.e., { (1, M), (2, M) … (N, M) }.

Further, the data structure L2P _ PAGE _ SET [ M ] occupies 4bytes in total and has an initial value of 0xffffff, indicating that the PAGE SET is not mapped.

Further, a data structure PAGE _ STATUS [ M ] is defined, each unit of the data structure is 1 byte, and M items are provided in total, and the data structure is used for representing the state of the corresponding PAGE set; wherein the page set state includes free pages, valid pages, obsolete pages, and corrupted pages.

Further, when data is written in, the data issued by the host computer is cached and stored; converting the logical address issued by the host into PAGE number P1, and querying data structure PAGE _ STATUS [ M ]]Find unused page set number N_freeL2P _ PAGE _ SET [ P1 ] will be SET]＝N_freeLOGIC _ PAGE _ SET [ P1 ]]Mapping to PHYSICAL _ PAGE _ SET [ N ]_free]At the same time, Page _ STATUS [ P1 ]]Set to a valid page state; finally, the buffered data is written into PHYSICAL _ PAGE _ SET [ N ] in parallel_free]In each page in the set, the write process is completed.

Further, when data is read, a cache is allocated; converting the logical address issued by the host into PAGE number P2, and querying data structure L2P _ PAGE _ SET [ P2 ]]Find the corresponding physical page set number N_freeObtaining PHYSICAL _ PAGE _ SET [ N ]_free]And concurrently reading data from the corresponding physical PAGE and storing the data in the allocated buffer, and simultaneously storing Page _ STATUS [ P1 ]]And setting the state to be an idle state, and finishing the process of data reading.

Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: the scheme provided by the invention can obviously reduce the consumed resources, is independent of the number of NAND Flash chips, and can finish an efficient address mapping algorithm by only consuming fixed resources no matter how many NAND Flash chips exist in the solid state disk.

Drawings

Fig. 1 is a physical structure diagram of a NAND Flash in an embodiment of the present invention.

Fig. 2 is a diagram illustrating a data structure according to an embodiment of the invention.

Fig. 3 is a diagram illustrating a mapping relationship according to an embodiment of the invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

The invention provides an FTL algorithm address mapping method of a solid state disk, aiming at the solid state disk consisting of N NAND flashes, uniformly managing each page of the N NAND flashes according to page address sequence numbers, defining a logical page set and a physical page set, wherein one page set represents the set of the M page sequence numbers of the N NAND flashes, and the mapping from a logical address to a physical address is represented by the mapping relation from the logical page set to the physical page set; and M is less than or equal to the total number of physical pages of each NAND Flash.

In this embodiment, a LOGIC _ PAGE _ SET data structure is proposed, where the data structure is a SET of PAGEs with the same serial number of N NAND Flash, and taking a solid state disk MT29F2T08CVCBB as an example, as shown in fig. 1, the NAND Flash has 17170432 PAGEs in total, PAGE numbers are 0 to 17170431, PAGE 0 of the first NAND Flash is defined as (1,0), PAGE 0 of the second NAND Flash is defined as (2,0), and so on, PAGE 0 of the N NAND Flash is defined as (N,0), and LOGIC _ PAGE _ SET (0) represents a SET of PAGE 0 on all NAND Flash, that is { (1,0), (2,0) … (N,0) }.

Correspondingly, a data structure L2P _ PAGE _ SET [ M ] is also defined, where M is the total number of PHYSICAL PAGEs in each NAND Flash, and this data stores the mapping relationship from logical PAGE SET LOGIC _ PAGE _ SET to PHYSICAL PAGE SET PHYSICAL _ PAGE _ SET, and unlike the general design, the mapping from logical address to PHYSICAL address is two SETs of mapping, as shown in fig. 2, the data structure has 4bytes in total, and the initial value is a default value of 0xffffff, indicating that the PAGE SET is not mapped. For example, if L2P _ PAGE _ SET [3] ═ 4; it indicates that the PHYSICAL PAGE SET mapped by the LOGIC _ PAGE _ SET (3) is PHYSICAL _ PAGE _ SET (4), and is { (1,3), (2,3) … (N,3) } mapped to { (1,4), (2,4) … (N,4) }, as shown in fig. 3.

In the present embodiment, a data structure PAGE _ STATUS [ M ] is also proposed, the data structure being 1 byte per unit and having M entries in total, the data structure indicating the STATUS of the corresponding PAGE set, the PAGE set STATUS having a free PAGE, a valid PAGE, a waste PAGE, and a damaged PAGE.

According to the address mapping design of this embodiment, when data is written, a cache needs to be allocated according to the page capacity N times, and the cache is used for storing data issued by a host. Converting the logical address issued by the host into a PAGE number P, querying a data structure of Page _ STATUS [ M ], finding an unused PAGE SET number Nfree, mapping the PAGE SET to L2P _ PAGE _ SET, namely setting L2P _ PAGE _ SET [ P ] ═ Nfree, mapping L2P _ PAGE _ YS [ P ] to PHICAL _ PAGE _ SET [ Nfree ], namely completing the mapping of { (1, P), (2, P) … (N, P) } to { (1, Nfree), (2, Nfree) … (N, Nfree) }, and simultaneously setting Page _ STATUS [ P ] to a valid PAGE state. Then, the data is concurrently written into each PAGE in the PHYSICAL _ PAGE _ SET [ Nfree ] SET, and the writing process is completed.

When reading data, a cache for storing data read from the NAND Flash needs to be allocated according to N times of the page capacity. Converting a logical address issued by a host into a PAGE number P, querying an L2P _ PAGE _ SET data structure, finding an L2P _ PAGE _ SET [ P ] ═ Nfree, obtaining a PHYSICAL _ PAGE _ SET [ Nfree ] PAGE SET, namely the mapping of { (1, Nfree), (2, Nfree) … (N, Nfree) }, and concurrently reading and storing data from the SET PAGE into an allocated cache to finish the data reading process.

The light of the united states of america MT29F2T08CVCBB type NAND Flash, which has 33536 physical blocks each having 512 pages, was used as a test object, and the NAND Flash type physical structure diagram is shown in fig. 1, and this model NAND Flash has 17170432 pages in total. Assuming that there are N NAND flashes in the solid state disk, managing the N NAND flashes of the model requires managing N × 17170432 page units in total. Taking N as an example of 8, the general address mapping algorithm needs 8 × 17170432 entries, each entry occupies 4Bytes of storage resources, and then 8 × 17170432 × 4 ═ 549453824Bytes are needed.

If the design of the present invention is adopted, the management of 8 pieces of NAND Flash needs to rely on an L2P _ PAGE _ SET data structure, which has 17170432 entries, each of which occupies 4Bytes, and 17170432 × 4 ═ 68681728Bytes, which is 1/8 of the general algorithm.

The design of the invention is irrelevant to the number of the NAND Flash, and no matter how many NAND Flash exist in the solid state disk, the invention can complete the high-efficiency address mapping algorithm only by consuming fixed resources.

The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed. Those skilled in the art to which the invention pertains will appreciate that insubstantial changes or modifications can be made without departing from the spirit of the invention as defined by the appended claims.

All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.

Any feature disclosed in this specification may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.

Claims

1. An FTL algorithm address mapping method of a solid state disk is characterized in that aiming at the solid state disk formed by N NAND flashes, each page of the N NAND flashes is managed uniformly according to page address sequence numbers, a logical page set and a physical page set are defined, one page set represents the set of the M page sequence numbers of the N NAND flashes, and the mapping from logical addresses to physical addresses is represented through the mapping relation from the logical page set to the physical page set; and M is less than or equal to the total number of physical pages of each NAND Flash.

2. The address mapping method of claim 1, wherein a data structure L2P _ PAGE _ SET [ M ] is defined to store a mapping relationship from a logical PAGE SET LOGIC _ PAGE _ SET [ M ] to a PHYSICAL PAGE SET PHYSICAL PAGE _ SET [ M ], and the logical PAGE SET LOGIC _ PAGE _ SET [ M ] and the PHYSICAL PAGE SET PHYSICAL PAGE _ SET [ M ] respectively represent a SET of logical and PHYSICAL M-th PAGE indexes of N NAND Flash in the solid state disk, i.e., { (1, M), (2, M) … (N, M) }.

3. The address mapping method for the FTL algorithm of solid state disk of claim 2, wherein the data structure L2P _ PAGE _ SET [ M ] occupies 4bytes in total, and has an initial value of 0xFFFFFFF, which indicates that the PAGE SET is not mapped.

4. A solid state disk FTL algorithm address mapping method of claim 3, characterized in that a data structure PAGE _ STATUS [ M ] is defined, each unit of the data structure is 1 byte, and there are M entries for representing the state of the corresponding PAGE set; wherein the page set state includes free pages, valid pages, obsolete pages, and corrupted pages.

5. The FTL algorithm address mapping method of claim 4, wherein when writing data, caching data issued by a storage host; converting the logical address issued by the host into PAGE number P1, and querying data structure PAGE _ STATUS [ M ]]Find unused page set number N_freeL2P _ PAGE _ SET [ P1 ] will be SET]＝N_freeLOGIC _ PAGE _ SET [ P1 ]]Mapping to PHYSICAL _ PAGE _ SET [ N ]_free]At the same time, Page _ STATUS [ P1 ]]Set to a valid page state; finally, the buffered data is written into PHYSICAL _ PAGE _ SET [ N ] in parallel_free]In each page in the set, the write process is completed.

6. The solid state disk FTL algorithm address mapping method of claim 5, wherein a cache is allocated when data is read;converting the logical address issued by the host into PAGE number P2, and querying data structure L2P _ PAGE _ SET [ P2 ]]Find the corresponding physical page set number N_freeObtaining PHYSICAL _ PAGE _ SET [ N ]_free]And concurrently reading data from the corresponding physical PAGE and storing the data in the allocated buffer, and simultaneously storing Page _ STATUS [ P1 ]]And setting the state to be an idle state, and finishing the process of data reading.