CN109960667A - The address conversion method and device of large capacity solid storage device - Google Patents
The address conversion method and device of large capacity solid storage device Download PDFInfo
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- CN109960667A CN109960667A CN201711347363.2A CN201711347363A CN109960667A CN 109960667 A CN109960667 A CN 109960667A CN 201711347363 A CN201711347363 A CN 201711347363A CN 109960667 A CN109960667 A CN 109960667A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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Abstract
This application provides the address conversion method of large capacity solid storage device and devices.The address conversion method for read operation provided, comprising: obtain the logical address of read operation access；If the logical address has hit the conversion page of caching, corresponding physical address is obtained with the logical address from the conversion page of caching.
Description
Technical field
This application involves solid storage devices, specifically, the address conversion method applied to large capacity solid storage device
With device.
Background technique
Fig. 1 illustrates the block diagram of solid storage device.Solid storage device 102 is coupled with host, for mentioning for host
For storage capacity.Host can be coupled in several ways between solid storage device 102, and coupled modes include but is not limited to
For example, by SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI
(Small Computer System Interface, small computer system interface), SAS (Serial Attached
SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics), USB
(Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect
Express, PCIe, high speed peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber it is logical
Road, cordless communication network etc. connect host and solid storage device 102.Host, which can be, to be set through the above way with storage
The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange
Machine, router, cellular phone, personal digital assistant etc..Storing equipment 102 includes interface 103, control unit 104, one or more
A NVM chip 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 is used to control the data transmission between interface 103, NVM chip 105 and DRAM 110, also
For storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit 104 can
It is realized by the various ways of software, hardware, firmware or combinations thereof, for example, control unit 104 can be FPGA (Field-
Programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 also may include place
Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders.Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110.?
DRAM can store the data of the I/O command of FTL table and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chip 105, and sent out in a manner of the interface protocol to follow NVM chip 105 to NVM chip 105
It orders out, to operate NVM chip 105, and receives the command execution results exported from NVM chip 105.Known NVM chip connects
Mouth agreement includes " Toggle ", " ONFI " etc..
Memory target (Target) is shared CE (, Chip Enable, chip enabled) signal in nand flash memory encapsulation
One or more logic units (LUN, Logic UNit).It may include one or more tube cores (Die) in nand flash memory encapsulation.
Typically, logic unit corresponds to single tube core.Logic unit may include multiple planes (Plane).It is more in logic unit
A plane can be with parallel access, and multiple logic units in nand flash memory chip can execute order and report independently of one another
State.
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block (also referred to as physical block) packet
Containing multiple pages.Block includes multiple pages.Page (referred to as Physical Page) on storage medium has fixed size, such as 17664 bytes.
Physical Page also can have other sizes.
In solid storage device, safeguarded using FTL (Flash Translation Layer, flash translation layer (FTL)) from
Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address for accessing the physical memory cell of solid storage device.In related skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL table.FTL table is that solid-state is deposited
Store up the important metadata in equipment.The data item of usual FTL table has recorded the ground in solid storage device as unit of data page
Location mapping relations.
FTL table includes multiple FTL table clauses (or list item).In one case, one is had recorded in each FTL table clause
The corresponding relationship of a logical page address and a Physical Page.In another case, it is had recorded in each FTL table clause continuous
The corresponding relationship of multiple logical page addresses and continuous multiple Physical Page.In still another case, it is recorded in each FTL table clause
The corresponding relationship of logical block address and physical block address.In the case that still another, in FTL table record logical block address with
The mapping relations and/or logical page address of physical block address and the mapping relations of physical page address.
In " DFTL:A Flash Translation Layer Employing Demand-based Selective
Caching of Page-level Address Mappings " discloses improved FTL table method and its in solid storage device
The middle mode applied, full text can be fromHttp:// www.cse.psu.edu/~buu1/papers/ps/dftl- asplos09.pdfIt obtains.
Summary of the invention
Memory capacity with storage equipment increasingly increases, and needs to serve the address conversion system of mass-memory unit
System.Address conversion system will meet following one or more demands, get rid of the limitation to memory size, provide stabilization for I/O operation
And efficient address translation capabilities, reduce the influence to storage equipment life, it is easy to accomplish.Address conversion system will also meet it
His demand.
According to a first aspect of the present application, the address turn according to the first of the application first aspect for read operation is provided
Change method, comprising: obtain the logical address of read operation access；If the logical address has hit the conversion page of caching, from caching
Conversion page obtain with the logical address corresponding physical address.
The address conversion method for being used for read operation according to the first of the application first aspect, provides according to the application first
The second of aspect is used for the address conversion method of read operation, further includes: if the conversion page of logical address miss caching, root
Conversion page is read according to the conversion page address obtained from global transformation catalogue, and is obtained from the conversion page of reading with the logical address
Corresponding physical address.
It is used for the address conversion method of read operation according to the first or second of the application first aspect, provides according to this Shen
Please the third of first aspect be used for the address conversion method of read operation, wherein the conversion page cached includes multiple entries, each
The corresponding relationship of mesh instruction logical address and physical address.
It is used for the address conversion method of read operation according to the third of the application first aspect, provides according to the application first
The 4th of aspect is used for the address conversion method of read operation, wherein the conversion page cached is that the conversion page stored in NVM chip exists
Copy in memory.
It is used for the address conversion method of read operation according to the third of the application first aspect or the 4th, provides according to this Shen
Please first aspect the 5th address conversion method for being used for read operation, wherein global transformation catalogue includes multiple entries, each
Mesh indicates logical address section and converts the corresponding relationship of page address, and conversion page address is the physics for converting page in NVM chip
Address.
The address conversion method for being used for read operation according to the 5th of the application first aspect the, provides according to the application first
The 6th of aspect is used for the address conversion method of read operation, and wherein the entry of global transformation catalogue is sequence, indicated by it
Logical address section sequence.
The address conversion method for being used for read operation according to the 5th or the 6th of the application first aspect the, provides according to this Shen
Please first aspect the 7th be used for read operation address conversion method, wherein each of global transformation catalogue program recording its correspondence
Conversion page whether have copy in memory.
One of the address conversion method for being used for read operation according to the first to the 7th of the application first aspect, provides basis
The 8th of the application first aspect is used for the address conversion method of read operation, wherein inquiry global transformation catalogue obtains the logic
Whether address hits the conversion page of caching, or the conversion page of traversal caching obtains whether the logical address hits turning for caching
It skips.
The address conversion method for being used for read operation according to the second of the application first aspect, provides according to the application first
The 9th of aspect is used for the address conversion method of read operation, further includes: if the conversion page of logical address miss caching, also
The conversion page of caching is eliminated, to discharge the conversion page that memory space accommodates the reading.
The address conversion method for being used for read operation according to the 9th of the application first aspect the, provides according to the application first
The tenth of aspect is used for the address conversion method of read operation, wherein, will be by if the conversion page for the caching being eliminated is writable type
NVM chip is written in the conversion page of superseded caching, and the conversion page that the caching being eliminated is updated in global transformation catalogue is corresponding
Conversion page conversion page address.
The address conversion method for being used for read operation according to the 9th or the tenth of the application first aspect the, provides according to this Shen
Please first aspect the 11st be used for read operation address conversion method, wherein if the conversion page for the caching being eliminated is read-only
Type discharges the memory space of the conversion page for the caching being eliminated without NVM chip is written in the conversion page for the caching being eliminated.
The address conversion method for being used for read operation according to the second of the application first aspect, provides according to the application first
The 12nd of aspect is used for the address conversion method of read operation, wherein setting the conversion page of the reading to the conversion of caching
Page.
The address conversion method for being used for read operation according to the 12nd of the application first aspect the is provided according to the application the
The 13rd of one side is used for the address conversion method of read operation, wherein by according to the caching of the conversion page setting of the reading
Conversion page is set as read-only type.
The address conversion method for being used for read operation according to the first of the application first aspect, provides according to the application first
The 14th of aspect is used for the address conversion method of read operation, further includes: if the conversion page of logical address miss caching,
Also inquire the conversion table whether logical address hits caching.
The address conversion method for being used for read operation according to the 14th of the application first aspect the is provided according to the application the
The 15th of one side is used for the address conversion method of read operation, further includes: if the conversion table of logical address hit caching,
Corresponding physical address is obtained from the conversion table of caching with the logical address according to the logical address.
The address conversion method for being used for read operation according to the 14th or the 15 of the application first aspect is provided according to this
Apply for that the 16th of first aspect is used for the address conversion method of read operation, further includes: if the logical address miss caches
Conversion table, conversion page is read according to the conversion page address that obtains from global transformation catalogue, and obtain from the conversion page of reading same
The corresponding physical address of the logical address.
One of the address conversion method for being used for read operation according to the 14th to 16 of the application first aspect the, provides root
It is used for the address conversion method of read operation according to the 17th of the application first aspect the, wherein the conversion page of the reading is arranged to
Read-only type.
One of the address conversion method for being used for read operation according to the 14th to 17 of the application first aspect the, provides root
The address conversion method of read operation is used for according to the 18th of the application first aspect the, further includes: according in the conversion table of caching
The physical address of one or more program recordings updates the conversion page of the reading.
The address conversion method for being used for read operation according to the 18th of the application first aspect the is provided according to the application the
The 19th of one side is used for the address conversion method of read operation, wherein the corresponding logical address category of one or more of entries
In the logical address section of the conversion page of the reading.
The address conversion method for being used for read operation according to the 19th of the application first aspect the is provided according to the application the
The 20th of one side is used for the address conversion method of read operation, further includes: the conversion page of the reading is arranged to writeable class
Type.
One of the address conversion method for being used for read operation according to the first to 20 of the application first aspect, provides basis
The 21st of the application first aspect is used for the address conversion method of read operation, further includes: according to the logical address pair
The physical address answered reads data.
According to a second aspect of the present application, the address turn according to the first of the application second aspect for write operation is provided
Change method, comprising: the logical address for obtaining write operation access and the physical address for write operation distribution；If the logical address life
The conversion page for having suffered caching updates the conversion page for the caching being hit according to the logical address and the physical address.
The address conversion method for being used for write operation according to the first of the application second aspect, provides according to the application second
The second of aspect is used for the address conversion method of write operation, wherein if the conversion page of the caching being hit is read-only type,
Also writable type is set by the conversion page of the caching being hit.
It is used for the address conversion method of write operation according to the first or second of the application second aspect, provides according to this Shen
Please second aspect third be used for write operation address conversion method, further includes: if the logical address miss caching turn
It skips, conversion page is read according to the conversion page address obtained from global transformation catalogue, according to the logical address and the physics
Address updates the conversion page read.
It is used for the address conversion method of write operation according to the third of the application second aspect, provides according to the application second
The 4th of aspect is used for the address conversion method of write operation, further includes: if the conversion page of logical address miss caching, also
The conversion page of caching is eliminated, to discharge the conversion page that memory space accommodates the reading.
The address conversion method for being used for write operation according to the 4th of the application second aspect the, provides according to the application second
The 5th of aspect is used for the address conversion method of write operation, wherein, will be by if the conversion page for the caching being eliminated is writable type
NVM chip is written in the conversion page of superseded caching, and the conversion page that the caching being eliminated is updated in global transformation catalogue is corresponding
Conversion page conversion page address.
The address conversion method for being used for write operation according to the 4th or the 5th of the application second aspect the, provides according to this Shen
Please second aspect the 6th be used for write operation address conversion method, wherein if the conversion page for the caching being eliminated is read-only class
Type discharges the memory space of the conversion page for the caching being eliminated without NVM chip is written in the conversion page for the caching being eliminated.
It is used for one of the address conversion method of write operation according to the third of the application second aspect to the 6th, provides basis
The 7th of the application second aspect is used for the address conversion method of write operation, wherein the conversion page of the reading is set as caching
Conversion page.
The address conversion method for being used for write operation according to the 7th of the application second aspect the, provides according to the application second
The 8th of aspect is used for the address conversion method of write operation, wherein by the conversion according to the caching of the conversion page setting of the reading
Page is set as read-only type.
One of the address conversion method for being used for write operation according to the first to the 8th of the application second aspect, provides basis
The 9th of the application second aspect is used for the address conversion method of write operation, wherein the conversion page cached includes multiple entries, often
The corresponding relationship of a entry instruction logical address and physical address.
The address conversion method for being used for write operation according to the 9th of the application second aspect the, provides according to the application second
The tenth of aspect is used for the address conversion method of write operation, wherein the conversion page cached is that the conversion page stored in NVM chip exists
Copy in memory.
One of the address conversion method for being used for write operation according to the first to the tenth of the application second aspect, provides basis
The 11st of the application second aspect is used for the address conversion method of write operation, and wherein global transformation catalogue includes multiple entries,
Each entry indicates logical address section and converts the corresponding relationship of page address, and conversion page address is conversion page in NVM chip
Physical address.
The address conversion method for being used for write operation according to the 11st of the application second aspect the is provided according to the application the
The 12nd of two aspects is used for the address conversion method of write operation, and wherein the entry of global transformation catalogue is sequence, by its institute
The logical address section of instruction sorts.
The address conversion method for being used for write operation according to the 11st or the 12nd of the application second aspect the, provides basis
The 13rd of the application second aspect is used for the address conversion method of write operation, wherein each of global transformation catalogue program recording
Whether its corresponding conversion page has copy in memory.
One of the address conversion method for being used for write operation according to the first to the 13rd of the application second aspect, provides root
Be used for the address conversion method of write operation according to the 14th of the application second aspect the, wherein inquiry global transformation catalogue obtain it is described
Whether logical address hits the conversion page of caching, or the conversion page of traversal caching obtains whether the logical address hits caching
Conversion page.
The address conversion method for being used for write operation according to the first of the application second aspect, provides according to the application second
The 15th of aspect is used for the address conversion method of write operation, further includes: if the conversion page of logical address miss caching,
It also inquires the logical address and whether hits the conversion table of caching, wherein the record instruction logical address and object of the conversion table cached
Manage the corresponding relationship of address.
The address conversion method for being used for write operation according to the 15th of the application second aspect the is provided according to the application the
The 16th of two aspects is used for the address conversion method of write operation, further includes: if the conversion table of logical address hit caching,
The conversion table of caching is updated according to the logical address and the physical address.
The address conversion method for being used for write operation according to the 15th or the 16 of the application second aspect is provided according to this
Apply for that the 17th of second aspect is used for the address conversion method of write operation, further includes: if the logical address miss caches
Conversion table, generate logical address described in new program recording of the conversion table of caching and the physical address.
One of the address conversion method for being used for write operation according to the 15th to the 17th of the application second aspect the, provides
The address conversion method for being used for write operation according to the 18th of the application second aspect the, further includes: in response to turning for the caching
It changes table and lacks the memory space for accommodating new entry, also eliminate one or more entries of the conversion table of caching, it is empty with release storage
Between accommodate new entry.
The address conversion method for being used for write operation according to the 18th of the application second aspect the is provided according to the application the
The 19th of two aspects is used for the address conversion method of write operation, wherein if the logic of the one or more entries being eliminated
The conversion page of address hit caching updates the caching being hit with the logical address and physical address of one or more of entries
Page, and one or more of entries are removed from the conversion table of caching.
The address conversion method for being used for write operation according to the 18th or the 19 of the application second aspect is provided according to this
Apply for that the 20th of second aspect is used for the address conversion method of write operation, wherein if the one or more entries being eliminated
Logical address miss caching conversion page, from global transformation catalogue obtain corresponding to the one or more entries being eliminated
The conversion page address of affiliated logical address section reads conversion page according to conversion page address, with one or more of entries
Logical address and physical address updates the caching page being hit, and one or more of are removed from the conversion table of caching
Mesh.
The address conversion method for being used for write operation according to the 19th or the 20 of the application second aspect is provided according to this
Apply for that the 21st of second aspect is used for the address conversion method of write operation, wherein be arranged to can for the conversion page of the reading
Write type.
According to the third aspect of the application, provide according to the first of the application third aspect the storage equipment, including control
Component, NVM chip and memory, NVM chip include multiple memory blocks, and memory block includes data block and conversion block；In data block
Record is written into the data of storage equipment；Conversion block records the corresponding relationship of multiple logical address and physical addresses；In memory
Record the conversion page of global transformation catalogue and caching；The control unit execution is mentioned according to the application first aspect or second aspect
One of method of confession.
According to the first of the application third aspect the storage equipment, provides and set according to the second of the application third aspect the storage
The conversion table of the standby wherein described memory also record buffer memory.
According to the fourth aspect of the application, provide according to the first of the application fourth aspect the storage equipment, including control
Component and nonvolatile memory chip, wherein control unit executes the side provided according to the application first aspect or second aspect
One of method.
According to the 5th of the application the aspect, the first journey comprising program code according to the 5th aspect of the application is provided
Sequence, when being loaded into CPU and executing in CPU, program provides CPU execution according to the application first aspect or second aspect
One of method.
According to the 6th of the application the aspect, the first address turn for read operation according to the 6th aspect of the application is provided
Change system, comprising: logical address module, for obtaining the logical address of read operation access；Physical address module, if for described
Logical address has hit the conversion page of caching, obtains with the logical address corresponding physical address from the conversion page of caching.
According to the 7th of the application the aspect, the first address turn for write operation according to the 7th aspect of the application is provided
Change system, comprising: address acquisition module, the logical address for obtaining write operation access are distributed physically with for write operation
Location；Update module, if for the logical address hit caching conversion page, according to the logical address and it is described physically
Location updates the conversion page for the caching being hit.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application can also be obtained according to these attached drawings other for those of ordinary skill in the art
Attached drawing.
Fig. 1 is the block diagram of solid storage device in the related technology；
Fig. 2 is the schematic diagram according to the address conversion system of the solid storage device of the embodiment of the present application；
Fig. 3 A is the flow chart that address conversion is carried out in response to read operation according to the embodiment of the present application；
Fig. 3 B is the flow chart that address conversion is carried out in response to write operation according to the embodiment of the present application；
Fig. 4 is the schematic diagram according to the address conversion system of the solid storage device of the another embodiment of the application；
Fig. 5 A is the flow chart that address conversion is carried out in response to read operation according to the embodiment of the application Fig. 4；And
Fig. 5 B is the flow chart that address conversion is carried out in response to write operation according to the embodiment of the application Fig. 4.
Specific embodiment
Below with reference to the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Ground description, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on the application
In embodiment, those skilled in the art's every other embodiment obtained without making creative work, all
Belong to the range of the application protection.
Fig. 2 is the schematic diagram according to the address conversion system of the solid storage device of the embodiment of the present application.Solid-state storage is set
Standby NVM chip (referring also to Fig. 1, NVM chip 105) provides multiple physical blocks.According to the difference of the content of storage, physical block
It is divided into data block and conversion block.Data block records the data for being written into solid storage device.Conversion block includes multiple conversion pages,
Conversion page is the memory space in the page or Physical Page of such as NVM storage medium with specified size (for example, 4KB).Conversion
Page has physical address (page address), by using the physical address of conversion page, may have access to the specified conversion of solid storage device
Page.For example, conversion block includes conversion page a and conversion page b in Fig. 2.Conversion page has recorded multiple records.Each record is for example
One list item of FTL table, has recorded physical address.And it is recorded in the position in conversion page and conversion block, it implys that and records institute
Corresponding logical address.For example, first record implys that logical address a in conversion page a, the value of first record is physics
Address a, and the Article 2 record of physical address increasing sequence implys that logical address a+1, the value of Article 2 record is physically
Location a1.It is noted that " logical address a " is reflected with the address recorded by a list item of FTL table " physical address a " in Fig. 2
Relationship is penetrated, but " logical address a " and " physical address a " is numerically optionally not related.It converts in page, by storage record
Multiple records of physical address sequence, have been sequentially recorded the continuous corresponding physical address of multiple logical addresses." logic
Address a " and " logical address a+1 " are numerically adjacent logical addresses, and each logical address indicates that has a specified size
Data cell (such as 4K)." physical address a " and " physical address a1 " is numerically not related, respectively can be solid-state and deposits
Arbitrary value in the address space of the NVM chip offer of equipment is provided.
Similarly, it converts in page b, first record implys that logical address b, and the value of first record is physical address b,
And the Article 2 record for recording the sequence of stored physical address increasing implys that logical address b+1, the value of Article 2 record is
Physical address b1.Further, as an example, conversion page b is adjacent with the conversion physical address of page a, and converts page b physically
Location rear, then first record of logical address b implies logical address b implied with conversion page a the last one logically
Location (being denoted as an) is adjacent, and after logical address an.
According to an embodiment of the present application, the logical address that one or more conversion pages have recorded solid storage device offer is empty
Between each logical address (using data cell as granularity) arrive physical address mapping.All records of each conversion page are implied
Continuous logic address space, referred to as logical address section.Optionally, the partial bit of logical address is used as and is represented logically
Location section.For example, 20 bit of centre of logical address, thus the logical address in logical address space included by logical address section
It need not be continuous.
With continued reference to Fig. 2, a variety of numbers are recorded in the memory (referring also to Fig. 1, such as DRAM 110) of solid storage device
According to table, the conversion page including global transformation catalogue and caching.Type that there are two types of the conversion pages of caching, respectively read-only caching
Convert page, the conversion page with writeable caching.The conversion page of caching has one or more.
Global transformation catalogue includes multiple entries, and each entry indicates<logical address section, conversion page address>correspondence
Relationship.The number of entries of global transformation catalogue is equal to the quantity of conversion page, and each entry has recorded corresponding conversion page in NVM
The conversion page of physical address (conversion page address) and/or corresponding caching in chip is in memory (for example, DRAM 110)
Address.The entry of global transformation catalogue is sequence, is sorted by the numerical order of the logical address section indicated by it, thus item
Mesh implys that logical address section indicated by the entry in the position in global transformation catalogue.
The conversion page of caching is to convert the copy of page in memory.The conversion page of caching includes multiple entries, and each
Program recording converts a record in page.Optionally, a small number of and not all conversion page has copy in memory.Read-only is slow
The conversion page deposited is identical with its corresponding conversion content of page in NVM storage medium.The conversion page of writeable caching, relatively
In conversion page in NVM storage medium corresponding with its, content is modified.To which the conversion page of read-only caching is being replaced
When changing, without being written to NVM storage medium, and the conversion page of writeable caching needs to be written to NVM storage and is situated between when being replaced
Matter.
Optionally, each entry of global transformation catalogue also records whether its corresponding conversion page has copy in memory
The address of (the conversion page of caching) and copy in memory.
Optionally, physical block allocation table, including data block table and conversion block table are also recorded in memory, wherein recording respectively
Which physical block of the NVM chip of solid storage device is used as data block, which physical block is used as conversion block.And it can
Selection of land, physical block allocation table further include free block list, and record is not used by or unassigned physical block.
Fig. 3 A is the flow chart that address conversion is carried out in response to read operation according to the embodiment of the present application.
Read operation instruction obtains data from logical address or ranges of logical addresses.It is retouched so that read operation accesses logical address as an example
State embodiments herein.For accessing the read operation of ranges of logical addresses, each address of ranges of logical addresses is obtained
Data are combined to respond read operation.
In one example, it in response to having received read operation, obtains the read operation logical address to be accessed (310), with reading
Logical address section where the logical address of operation inquires global transformation catalogue (referring also to Fig. 2), and obtaining the logical address section is
In the no conversion page for being recorded in caching (the conversion page hit referred to as cached) (340).If the logical address section has hit caching
Conversion page, access the conversion page of the caching of hit, therefrom obtain correspond to read operation logical address physical address
(360), to complete the address translation process for read operation.If the conversion page of logical address section miss caching, from the overall situation
Conversion catalogue obtains the conversion page address (being denoted as TPA) (350) corresponding to the logical address section, and conversion page address TPA has recorded
Convert physical address of the page in conversion block.And conversion page, Yi Jihuan are read from NVM chip according to conversion page address TPA
The conversion page that the conversion page is deposited to be cached, and obtained from the conversion page of reading according to the read operation logical address to be accessed
The corresponding physical address (PPA) (360) with logical address.To complete the address translation process for read operation.
And data are read from NVM chip with the physical address PPA obtained again.
Optionally, it replaces as obtaining logical address section to inquiry global transformation catalogue and whether hit the caching page of caching
In generation, searches for the conversion page of caching, to obtain the caching page whether the logical address section of read operation access hits caching.Further may be used
Selection of land searches for the conversion page of caching, with inquiry global transformation catalogue, is processed in parallel.In response to receiving read operation, both inquired complete
Office's conversion catalogue also judges whether the conversion table of caching hits to obtain conversion page address TPA.If the conversion page hit of caching,
Then conversion page address TPA is obtained from the conversion page of caching；If the conversion page miss of caching, can also obtain turning from the overall situation earlier
Change the conversion page address TPA of catalogue acquisition, and the conversion page to read.
Optionally, for read operation, in response to the conversion page miss (340) of caching, recognition memory is used to store
Whether there are also the new conversion pages of space for the memory block (referred to as conversion caching of page) of the conversion page of caching.
In one example, conversion caching of page is less than, can accommodate new conversion page, then basis is obtained from global transformation catalogue
The conversion page address TPA taken reads conversion page using conversion page address TPA from NVM chip, and reading, which is converted page and is stored in, to be turned
It skips in caching.To which the conversion page read also becomes the conversion page of caching.According to the logical address of read operation instruction from caching
Conversion page in obtain with logical address corresponding physical address PPA, and using physical address PPA access NVM chip, with read
Data.Optionally, also mark the type for converting page of the caching to be read-only.
In another example, conversion caching of page has been expired, and new conversion page can not be accommodated, and needs to select the conversion page of caching
(being denoted as TP) carries out superseded, accommodates new conversion page to obtain memory space.By turning for the conversion page TP write-in NVM chip of caching
Block is changed, the physical address of recording carrying conversion page TP in global transformation catalogue, and discharge the conversion page of conversion page TP
Caching, accommodates new conversion page to obtain memory space.Next, according to the conversion page address obtained from global transformation catalogue
TPA reads conversion page using conversion page address TPA from NVM chip, reads conversion page and is stored in conversion caching of page.From
And the conversion page read also becomes the conversion page of caching.Optionally, also mark the type for converting page of the caching to be read-only.
In still another example, to improve read operation processing speed, it is slow that solid storage device endeavours to ensure conversion page
Memory space be can get in depositing at any time to accommodate new conversion page, without eliminating turning for caching in the treatment process of read operation
It skips.For example, periodically or when specified requirements meets, (for example, the conversion page of caching is excessive, conversion caching of page is remaining empty
Between it is more low), initiate eliminate caching conversion page process, with release convert caching of page space.In turn, in processing read operation
When, if the conversion page miss of caching, (it can get storage at any time because having ensured that in conversion caching of page without selection process is implemented
Space is to accommodate new conversion page), and directly according to the conversion page address TPA obtained from global transformation catalogue, use conversion page
Address TPA reads conversion page from NVM chip.
According to an embodiment of the present application, the conversion page for the caching being eliminated is selected.
As an example, the conversion page for selecting the caching of read-only type, the conversion page as the caching being eliminated.Due to
The conversion page of the caching of read-only type is the identical copies of conversion page in memory in NVM chip, thus eliminates read-only class
The conversion page of the caching of type is written NVM chip without the conversion page that will be cached, also need not update the quilt in global transformation catalogue
The conversion page address TPA of superseded conversion page, and new conversion page is only obtained from NVM chip.
As another example, the conversion page of the caching of read-only type, then select the caching of writable type if it does not exist
Convert page.And in selection process, NVM chip is written into the conversion page of the caching of writable type, in global transformation catalogue
The new conversion page address TPA for recording the conversion page for the caching being eliminated, will also obtain new conversion page from NVM chip.
As still another example, according to the conversion number of pages of the caching of read-only type in conversion caching of page, and/or turn
Skip caching in writable type caching conversion number of pages, select the conversion page for the caching being eliminated.If read-only type is slow
The quantity for the conversion page deposited is greater than specified threshold, selects the conversion page of the caching of read-only type, as turning for the caching being eliminated
It skips.If the quantity of the conversion page of the caching of read-only type is not more than specified threshold, the conversion page of the caching of writable type is selected,
Conversion page as the caching being eliminated.
Fig. 3 B is the flow chart that address conversion is carried out in response to write operation according to the embodiment of the present application.
Write operation is indicated to logical address or ranges of logical addresses write-in data.It is retouched so that write operation accesses logical address as an example
State embodiments herein.For access ranges of logical addresses write operation, write data into ranges of logical addresses eachly
Location is to respond write operation.
It obtains the write operation logical address to be accessed (370) in response to receiving write operation according to the embodiment of Fig. 3 B, is
Write operation allocated physical address writes data into the physical address of distribution.
Global transformation catalogue (referring also to Fig. 2) (380) are inquired with the logical address section where the logical address of write operation, are obtained
In the conversion page for whether being recorded in caching to the logical address section (the conversion page hit referred to as cached) (382).If the logic
Address field has hit the conversion page of caching, and further the type of the conversion page of the caching of identification hit is read-only or writeable
(384).If the conversion page of the caching of hit be it is writeable, updated and hit with the logical address of write operation and the physical address of distribution
Caching page in (395).If the conversion page of the caching of hit be it is read-only, physically with the logical address of write operation and distribution
Location updates in the caching page of hit (395), also by the type mark for converting page of the caching of hit into writeable (386).It is optional
Ground also updates the conversion page of read-only caching, the conversion page with writeable caching, respective quantity.
If the conversion page of the corresponding logical address section miss caching of the logical address of write operation, from global transformation catalogue
The conversion page address (being denoted as TPA) corresponding to the logical address section is obtained, conversion page address TPA has recorded conversion page in conversion block
In physical address.And conversion page is read from NVM chip according to conversion page address TPA, and cache the conversion page to obtain
To the conversion page (390) of caching, and turn read is updated according to the physical address of the write operation logical address and distribution to be accessed
In skipping with logical address corresponding physical address (PPA) (395).To complete the address translation process for write operation.To also
The type mark for converting page of obtained caching is writeable (386).Optionally, the conversion page for also updating read-only caching, with
The conversion page of writeable caching, respective quantity.
Optionally, or further, in response to the conversion page miss (382) of caching, recognition memory is used to store
Whether there are also the new conversion pages of space for the memory block (referred to as conversion caching of page) of the conversion page of caching.If converting caching of page not
It is full, new conversion page can be accommodated, then according to the conversion page address TPA obtained from global transformation catalogue, uses conversion page address
TPA reads conversion page from NVM chip, reads conversion page and is stored in conversion caching of page.If conversion caching of page has been expired, can not
New conversion page is accommodated, then selects the conversion page (being denoted as TP) of caching to carry out superseded, accommodates new conversion to obtain memory space
Page.
Further, the conversion page for the caching being eliminated also is selected.Select the strategy of conversion page for the caching being eliminated
It is described in the embodiment according to Fig. 3 A.
Fig. 4 is the schematic diagram according to the address conversion system of the solid storage device of the another embodiment of the application.Physical block
It is divided into data block and conversion block.Record is written into the data of solid storage device in data block.Conversion block records logical address
With the corresponding relationship of physical address.
With continued reference to Fig. 4, a variety of numbers are recorded in the memory (referring also to Fig. 1, such as DRAM 110) of solid storage device
According to table, the conversion table including global transformation catalogue, the conversion page and caching of caching.There are two types of types for the conversion page of caching, respectively
Conversion page for the conversion page of read-only caching, with writeable caching.The conversion page of caching is to convert the pair of page in memory
This.
Global transformation catalogue includes multiple entries, and each entry indicates<logical address section, conversion page address>correspondence
Relationship.
The conversion table of caching includes multiple entries, and each entry has recorded<logical address, physical address>corresponding relationship.
Logical address instruction has the data cell of specified size in the address of logical address space, and physical address indicates the data cell
Physical address in NVM chip.Each entry in the conversion table of caching is not necessarily to sort by logical address.Optionally, CAM is used
(Content Addressable Memory, content adressable memory), Cache (cache), TLB (Translation
Lookaside Buffer bypasses translation cache) conversion tables of memory buffers, to use logical address as address, and from
Corresponding physical address is obtained with logical address in the cache table of conversion.Still optionally, with general memory and support
The conversion table for the data structure memory buffers quickly searched.According to an embodiment of the present application, the conversion table of caching is write for carrying
Operation to<logical address, physical address>corresponding relationship update.
Fig. 5 A is the flow chart that address conversion is carried out in response to read operation according to the embodiment of the application Fig. 4.
Read operation instruction obtains data from logical address or ranges of logical addresses.It is retouched so that read operation accesses logical address as an example
State embodiments herein.
According to the embodiment of Fig. 5 A, in response to having received read operation, obtain the read operation logical address to be accessed (510),
Global transformation catalogue (referring also to Fig. 4) (515) are inquired with the logical address section where the logical address of read operation, obtain the logic
Whether address field is recorded in the conversion page of caching (the conversion page hit referred to as cached) (520).Optionally, traverse one or
The conversion page of multiple cachings, to determine whether logical address section is recorded in the conversion page of caching.
If the logical address section has hit the conversion page (520) of caching, the conversion page of the caching of hit is accessed, is therefrom obtained
The physical address (540) of logical address corresponding to read operation, to complete the address translation process (550) for read operation.If
Whether the conversion page (520) of logical address section miss caching, the logical address for inquiring read operation hit the conversion table of caching
(525).If the logical address of read operation has hit the conversion table (525) of caching, obtains to correspond to from the conversion table of caching and read
The physical address (535) of the logical address of operation.
In one example, for the logical address of read operation, the conversion table of caching whether is hit relative to inquiry, and it is excellent
It first inquires its conversion page for whether hitting caching to be advantageous, because the conversion page of caching has bigger memory space, storage
More<logical address, physical address>corresponding relationship, so that the conversion page of caching has more relative to the conversion table of caching
Big probability is hit.In another example, the conversion table for whether hitting the conversion page and caching of caching concurrently inquired.With
And in the case where the two is all hit, corresponding physical address is obtained from the conversion page for the caching being hit.
If the conversion table (525) that the logical address miss of read operation caches, obtained pair according to from global transformation catalogue
Conversion page should be read using the conversion page as caching from NVM chip in the conversion page address (being denoted as TPA) of the logical address section
(530).And same patrol is obtained from the conversion page (the conversion page as caching) of reading according to the read operation logical address to be accessed
It collects the corresponding physical address in address (PPA) (540).To complete the address translation process for read operation.And again with acquisition
Physical address PPA reads data from NVM chip.
Optionally, (the conversion page read from NVM chip is denoted as turning for caching afterwards in the conversion page (530) of replacement caching
Skip CTP 1), also merge the conversion page CTP 1 of caching and the conversion table (537) of caching.As an example, the conversion page of caching
CTP 1 has recorded each logical address in logical address section (being denoted as LR) with the corresponding relationship of physical address.And what is cached turns
It changes in table, it is understood that there may be one or more record, logical address belong to logical address section LR.With logic in the conversion table of caching
Address belongs to one or more entries of logical address section LR, updates the conversion page CTP 1 of caching.In other words, with caching
Logical address belongs to the physical address of one or more entries of logical address section LR in conversion table, updates the conversion page of caching
The physical address of corresponding entry in CTP 1.And by logical address in the conversion table of caching belong to one of logical address section LR or
Multiple entries are removed from the conversion table of caching, to discharge the conversion table space of caching.
Optionally, in step 530, memory block (the referred to as conversion page of the conversion page for memory buffers of recognition memory
Caching) whether there are also the new conversion pages of space.
In one example, conversion caching of page is less than, can accommodate new conversion page, then basis is obtained from global transformation catalogue
The conversion page address TPA taken reads conversion page using conversion page address TPA from NVM chip, and reading, which is converted page and is stored in, to be turned
It skips in caching.To which the conversion page read also becomes the conversion page of caching.Optionally, the class of the conversion page of the caching is also marked
Type is read-only.
In another example, conversion caching of page can not completely accommodate new conversion page or free space lower than threshold value, need
It selects the conversion page (being denoted as TP) of caching to carry out superseded, accommodates new conversion page to obtain memory space.Next, according to from
The conversion page address TPA that global transformation catalogue obtains reads conversion page using conversion page address TPA from NVM chip, reads and turn
It skips and is stored in conversion caching of page.Optionally, also mark the type for converting page of the caching to be read-only.
In still another example, to improve read operation processing speed, it is slow that solid storage device endeavours to ensure conversion page
Memory space be can get in depositing at any time to accommodate new conversion page, without eliminating turning for caching in the treatment process of read operation
It skips.For example, periodically or when specified requirements meets, (for example, the conversion page of caching is excessive, conversion caching of page is remaining empty
Between it is more low), initiate eliminate caching conversion page process, with release convert caching of page space.
Fig. 5 B is the flow chart that address conversion is carried out in response to write operation according to the embodiment of the application Fig. 4.
Write operation is indicated to logical address or ranges of logical addresses write-in data.It is retouched so that write operation accesses logical address as an example
State embodiments herein.
It obtains the write operation logical address to be accessed (560) in response to receiving write operation according to the embodiment of Fig. 5 B, is
Write operation allocated physical address writes data into the physical address of distribution.
Global transformation catalogue (referring also to Fig. 4) (565) are inquired with the logical address section where the logical address of write operation, are obtained
In the conversion page for whether being recorded in caching to the logical address section (the conversion page hit referred to as cached) (570).Optionally, time
The conversion page of one or more cachings is gone through, to determine whether logical address section is recorded in the conversion page of caching.
If the logical address section has hit the conversion page (570) of caching, the conversion page for the caching that further identification is hit
Type is read-only or writeable (572).If the conversion page of the caching of hit is writeable (572), with the logic of write operation
The physical address of address and distribution updates the conversion page (585) of the caching of hit.If the conversion page of the caching of hit is read-only
(572), by the type mark for converting page of the caching of hit into writeable (576), with logical address and the distribution of write operation
Physical address updates the conversion page (585) of the caching of hit.Optionally, the conversion page for also updating read-only caching, and it is writeable
The conversion page of caching, respective quantity.
If the conversion page (570) of the corresponding logical address section miss caching of the logical address of write operation, uses write operation
Logical address query caching conversion table, whether decision logic address, which is recorded in the conversion table of caching, (referred to as caches
Conversion table hit) (575).If the logical address of write operation has hit the conversion table of caching, with the logical address of write operation with point
The physical address matched updates the conversion table (594) of caching.
In one example, for the logical address of write operation, the conversion table of caching whether is hit relative to inquiry
(575), it preferentially inquires its conversion page (570) for whether hitting caching to be advantageous, because the conversion page of caching has more greatly
Memory space, store more<logical address, physical address>corresponding relationship, so that the conversion page of caching is relative to slow
The conversion table deposited has bigger probability to be hit.It is preferentially that write operation is corresponding also, but also compared to the conversion table of caching
Logical address and physical address is updated into the conversion page of caching.In another example, concurrently inquires and whether hit caching
Conversion page and caching conversion table.And in the case where the two is all hit, the conversion page for updating the caching being hit is corresponding
Physical address.
If the conversion table (575) that the logical address miss of write operation caches, is obtained from the conversion table of caching and be used for new item
Purpose memory space (580), to record the corresponding logical address and physical address of write operation in the conversion table of caching.
In one example, the entry that the conversion table of caching has space new, in the new entry of the conversion table of caching
Record the corresponding logical address and physical address (594) of write operation.In another example, the space of the conversion table of caching is lower than
Threshold value can not accommodate new entry, then select the conversion table one or more entry of caching to carry out superseded, empty to obtain storage
Between accommodate new entry.
Logical address section belonging to its logical address is chosen in one example to eliminate the entry of the conversion table of caching
The one or more entries for having hit the conversion page of (one or more) caching update caching with the physical address of these entries
Page is converted, and these entries are removed from the conversion table of caching.
In another example, identify that the number of entries of the conversion table for the caching which logical address section is covered is most,
(one or more) entry of the conversion table of caching corresponding to the logical address section is selected to carry out superseded.If the logical address section
The conversion page of corresponding caching, the conversion page of caching is updated with the physical address of these entries.If the logical address section corresponds to NVM core
The conversion page of on piece reads corresponding conversion page, updates conversion page with the physical address of these entries.And turn what is be updated
Change be writing for caching convert page (type into writeable).And by these entries of the conversion table of caching from the conversion table of caching
It removes.
Judge whether the corresponding logical address of write operation has hit the conversion page (590) of caching again.If the logical address
Section has hit the conversion page (590) of caching, turns to step 572 and is handled.If the conversion of logical address section miss caching
Page (590) updates the conversion table (594) of caching with the logical address of write operation and the physical address of distribution.In response to write operation
The process for carrying out address conversion terminates (598).
It is to be appreciated that in step 580, if the entry that the conversion table of caching has space new, or eliminate caching
When the entry of conversion table, the entry hit that the is eliminated conversion page of caching, since the logical address section of the conversion page of caching does not have
It changes, then records the corresponding logical address and physical address (594) of write operation directly in the new entry of the conversion table of caching,
And without step 590.
In step 580, cause to have read conversion page from NVM chip if eliminating the entry of the conversion table of caching, so that caching
The logical address section of conversion page change, then by step 590, judge whether the corresponding logical address of write operation orders again
The conversion page of caching is suffered.
A kind of solid storage device is additionally provided according to an embodiment of the present application, which includes that controller is deposited with non-volatile
Memory chip, wherein controller executes any one processing method provided by the embodiments of the present application.
A kind of program being stored on readable medium is additionally provided according to an embodiment of the present application, when by solid storage device
Controller operation when so that solid storage device execute according to any one processing method provided by the embodiments of the present application.
Although the preferred embodiment of the application has been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the application range.Obviously, those skilled in the art can be to the application
Various modification and variations are carried out without departing from spirit and scope.If in this way, these modifications and variations of the application
Belong within the scope of the claim of this application and its equivalent technologies, then the application is also intended to encompass these modification and variations and exists
It is interior.
Claims (10)
1. a kind of address conversion method for read operation, comprising:
Obtain the logical address of read operation access；
If the logical address has hit the conversion page of caching, corresponding object is obtained with the logical address from the conversion page of caching
Manage address.
2. according to the method described in claim 1, further include:
If the conversion page of the logical address miss caching, reads according to the conversion page address obtained from global transformation catalogue and turns
It skips, and obtains with the logical address corresponding physical address from the conversion page of reading.
3. according to the method described in claim 2, further include:
If the conversion page of the logical address miss caching, also eliminates the conversion page of caching, institute is accommodated to discharge memory space
State the conversion page of reading.
4. according to the method described in claim 3, wherein,
If the conversion page for the caching being eliminated is writable type, NVM chip is written into the conversion page for the caching being eliminated, and complete
The conversion page address of the corresponding conversion page of conversion page for the caching being eliminated is updated in office's conversion catalogue.
5. the method according to claim 3 or 4, wherein
If the conversion page for the caching being eliminated is read-only type, the memory space of conversion page for the caching being eliminated is discharged without inciting somebody to action
NVM chip is written in the conversion page for the caching being eliminated.
6. a kind of address conversion method for write operation, comprising:
The logical address for obtaining write operation access and the physical address for write operation distribution；
If the logical address has hit the conversion page of caching, it is hit according to the logical address and physical address update
Caching conversion page.
7. according to the method described in claim 6, further include:
If the conversion page of the logical address miss caching, reads according to the conversion page address obtained from global transformation catalogue and turns
It skips, the conversion page read is updated according to the logical address and the physical address.
8. according to the method described in claim 6, further include:
If the conversion page of the logical address miss caching, also inquires the conversion table whether logical address hits caching,
The corresponding relationship of the record instruction logical address and physical address of the conversion table wherein cached.
9. according to the method described in claim 8, further include:
If the conversion table of the logical address miss caching, generates logical address described in new program recording of the conversion table of caching
With the physical address.
10. a kind of storage equipment, including control unit, NVM chip and memory, NVM chip include multiple memory blocks, memory block
Including data block and conversion block；Record is written into the data of storage equipment in data block；Conversion block record multiple logical addresses with
The corresponding relationship of physical address；The conversion page of global transformation catalogue and caching is recorded in memory；
The control unit executes method described in one of -9 according to claim 1.
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Address after: 100192 room A302, building B-2, Dongsheng Science Park, Zhongguancun, 66 xixiaokou Road, Haidian District, Beijing Applicant after: Beijing yihengchuangyuan Technology Co.,Ltd. Address before: 100192 room A302, building B-2, Dongsheng Science Park, Zhongguancun, 66 xixiaokou Road, Haidian District, Beijing Applicant before: BEIJING MEMBLAZE TECHNOLOGY Co.,Ltd. |
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