CN114968067A

CN114968067A - Data sorting method using persistent memory and memory storage system

Info

Publication number: CN114968067A
Application number: CN202110213112.5A
Authority: CN
Inventors: 侯冠宇; 傅子瑜
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2021-02-25
Filing date: 2021-02-25
Publication date: 2022-08-30

Abstract

A data organization method using persistent memory and memory storage system. The method comprises the following steps: enabling persistent memory in a host system; storing a management table maintained by a memory device into the persistent memory in a state where a connection between a host system and the memory device is established; and in the process of executing data sorting operation by the memory device, the memory device updates the management table in the persistent memory through the connection, and copies the target data from at least one first type entity unit to at least one second type entity unit for storage according to the updating result.

Description

Data sorting method using persistent memory and memory storage system

Technical Field

The present invention relates to a memory management technology, and more particularly, to a data organization method using a persistent memory and a memory storage system.

Background

As the size of Memory storage devices is becoming smaller and smaller, and the cost of manufacturers is becoming a consideration, reducing the capacity and size of Dynamic Random Access Memory (DRAM) in Memory storage devices is becoming one of the design choices. Generally, in a DRAM-less Memory storage device, the shortage of DRAM in the Memory storage device itself can be compensated by sharing Memory (also called Host Memory Buffer (HMB)) with the Host system. However, based on current standard specifications, the memory provided by the host system is volatile memory (e.g., DRAM), which can cause data loss when power is unexpectedly turned off. Therefore, the memory storage device generally does not store the important data in the HMB, so as to avoid the important data loss during the sudden power off and cannot be repaired. Under the limitation, when the DRAM-less memory storage device performs internal data organization (e.g. data transfer), the memory storage device can only use the buffer with smaller internal capacity (the capacity may be only 2-8 MB) to perform data organization, thereby causing the operation efficiency to be greatly reduced.

Disclosure of Invention

The invention provides a data sorting method using a persistent memory and a memory storage system, which can improve the efficiency of executing internal data sorting by using the persistent memory at a host system end.

The embodiment of the invention provides a data sorting method using a persistent memory, which comprises the following steps: enabling persistent memory in a host system; storing a management table maintained by a memory device into the persistent memory in a state where a connection between the host system and the memory device is established; and in the process of executing data sorting operation by the memory device, the memory device updates the management table in the persistent memory through the connection, and copies target data from at least one first type entity unit in the memory device to at least one second type entity unit in the memory device for storage according to the updating result.

An embodiment of the present invention further provides a memory storage system using persistent memory, which includes a host system and a memory device. The host system is configured with persistent memory. The memory device is coupled to the host system. The host system is to enable the persistent memory. In a state where a connection between the host system and the memory device is established, a memory controller of the memory device stores a management table maintained by the memory device into the persistent memory. During the data sorting operation performed by the memory device, the memory controller updates the management table in the persistent memory via the connection, and copies the target data from at least one first type entity unit in the memory device to at least one second type entity unit in the memory device for storage according to the update result.

Based on the above, the host system may enable its internal persistent memory. In a state where a connection between the host system and the memory device is established, a management table maintained by the memory device may be stored into the persistent memory. Then, during the data sorting operation performed by the memory device, the memory device may update the management table in the persistent memory via the connection, and copy the target data from at least one first type entity unit to at least one second type entity unit in the memory device for storage according to the update result. Therefore, the efficiency of the memory storage device for executing internal data arrangement can be effectively improved.

Drawings

Fig. 1 is a schematic diagram of a memory storage system according to an embodiment of the invention.

FIG. 2 is a flow chart illustrating a data organization method using persistent memory according to an embodiment of the invention.

Wherein:

10, a memory storage system;

11, a host system;

111, a processor;

112, persistent memory;

12 a memory device;

121, a memory controller;

122, a non-volatile memory module;

1221,1222 storage area;

s201 to S203.

Detailed Description

Fig. 1 is a schematic diagram of a memory storage system according to an embodiment of the invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory device 12. The interface specification between the host system 11 and the memory device 12 conforms to the NVM Express (NVMe) interface standard. The memory storage system 10 is also referred to as NVMe storage system.

The host system 11 is coupled to the memory device 12 and can store data in the memory device 12 or read data from the memory device 12. For example, the host system 11 may be any system that substantially cooperates with the memory device 12 to store data, such as a computer system, a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory device 12 may be a Flash disk, a memory card, a Solid State Drive (SSD), a Secure Digital (SD) card, a Compact Flash (CF) card, or various non-volatile memory storage devices such as an embedded storage device.

The host system 11 includes a processor 111 and a persistent memory (persistent memory) 112. The processor 111 is coupled to persistent memory 112. The processor 111 may run an operating system (e.g., Windows or iOS, etc.) and may be responsible for partial or complete functioning of the host system 11. For example, the Processor 111 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable controller, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.

The persistent memory 112 is disposed in the host system 11 and is used for storing data. The location of the persistent memory 112 in the storage medium of each level may be between a conventional DRAM and a Solid State Disk (SSD). That is, although the data access speed of the persistent memory 112 is slightly slower than that of the DRAM, the storage capacity of the persistent memory 112 can approach that of a general SSD. For example, assuming that the storage capacity of a conventional DRAM is between 4GB and 32GB, the storage capacity of the persistent memory 112 may be between 128GB and 512GB or even larger. In addition, the data access speed of the persistent memory 112 may be, for example, more than 6 times the data access speed of a conventional SSD.

The persistent memory 112 may be selectively operated in a volatile mode and a persistent mode. In the volatile mode, data stored in the persistent memory 112 is lost due to a (sudden) power down of the host system 11. That is, in the volatile mode, the persistent memory 112 is used similar to a conventional DRAM, which can store data in a volatile manner. In one embodiment, the persistent memory 112 operating in the volatile mode may also be used to replace or as an extension of conventional DRAM.

In the persistent mode, data stored in the persistent memory 112 is not lost due to a (sudden) power down of the host system 11. That is, in the persistent mode, the use of persistent memory 112 is SSD-like and can persistently store data. However, compared to the SSD which employs the NAND package model, the persistent Memory 112 is packaged using Dual In-line Memory Module (DIMM). Thus, the persistent memory 112 is compatible with the buses or channels traditionally used by DRAMs.

In one embodiment, the host system 11 may further include other storage media (e.g., DRAM and/or SSD), a power supply circuit (e.g., battery), and various input/output devices (e.g., screen, keyboard, mouse, touch pad, speaker, microphone, and/or network interface card), which are not limited in the invention.

The memory device 12 includes a memory controller (also referred to as a flash memory controller) 121 and a nonvolatile memory module 122. The memory controller 121 can be used to control the nonvolatile memory module 122. For example, the memory controller 121 may control the non-volatile memory module 122 to perform reading, writing, and erasing of data.

The non-volatile memory module 122 is used for non-volatile data storage. For example, the nonvolatile memory module 122 may include a plurality of physical units. Each physical unit may include a plurality of memory cells. Each memory cell can store data by changing the threshold voltage. It is noted that multiple memory cells in the same physical cell can be programmed (e.g., by applying a write voltage) simultaneously to store data. For example, an entity unit may be an entity fan, entity page, or other entity management unit.

The non-volatile memory module 122 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store 1 bit), a multi-level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store 2 bits), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store 3 bits), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell can store 4 bits), and/or other types of flash memory modules.

The nonvolatile memory module 122 includes a storage area (also referred to as a cache area) 1221 and a storage area 1222. Each physical unit in the storage area 1221 is also referred to as a first type of physical unit. Each physical unit in the storage area 1222 is also referred to as a second type of physical unit. A single physical unit in the storage area 1221 is used to store n bits. A single physical unit in the storage area 1222 is used to store m bits. m and n are positive integers, and m is greater than n. In one embodiment, n may be 1 and m may be 2, 3, or 4.

In one embodiment, each physical cell in the storage area 1221 may be programmed based on a virtual SLC (pSLC) mode. Thus, a single memory cell programmed in the storage area 1221 can store 1 bit. In one embodiment, each physical cell in the storage area 1222 may be programmed based on TLC or QLC mode. Thus, a single memory cell programmed in the storage area 1222 can store 3 or 4 bits.

In one embodiment, the memory device 12 may not have DRAM therein, so the memory device 12 may also be referred to as a DRAM-less memory device. In one embodiment, the Memory controller 121 and/or the nonvolatile Memory module 122 may have a Static Random Access Memory (SRAM). For example, the storage space of the SRAM in the memory controller 121 and/or the nonvolatile memory module 122 may be about 2 to 8MB or more.

In an embodiment, the processor 111 of the host system 11 may enable the persistent memory 112. For example, the processor 111 may update an indication value indicating the use state of the persistent memory 112 from a bit "0 (disabled)" to a bit "1 (enabled)". In addition, the processor 111 may set the amount of storage space in the persistent memory 112 that is allowed to be provided for use by the memory device 12. For example, the processor 111 may set 500MB of storage space in the persistent memory 112 available to the memory device 12.

In one embodiment, the host system 11 may perform a handshake (handshake) procedure with the memory device 12. For example, in the handshake process, the host system 11 and the memory device 12 may communicate one or more signals to each other for mutual authentication. The handshake process may be used to establish a connection between the host system 11 and the memory device 12. The connection also conforms to the NVMe interface standard.

In one embodiment, in a state where a connection between the host system 11 and the memory device 12 is established, the memory controller 121 of the memory device 12 may store one or more management tables maintained by the memory device 12 into the persistent storage 112 of the host system 11. For example, the management table may include a logical-to-physical mapping table originally stored in the nonvolatile memory module 122. The logic-to-entity mapping table may record logic-to-entity mapping information associated with certain physical units in the nonvolatile memory module 122. For example, the logic-to-entity mapping information may include mapping information between one entity unit and one logic unit in the nonvolatile memory module 122. Wherein a logical unit may refer to one or more logical addresses.

In one embodiment, memory controller 121 may perform data grooming operations. The data sorting operation can copy the valid data (also called target data) stored in the storage area 1221 to the storage area 1222 for centralized storage. Wherein the valid data refers to the data currently mapped by the logical unit. For example, in the data sorting operation, the valid data stored in m (e.g. 3 or 4) first-type physical units in the storage area 1221 can be copied to n (e.g. 1) second-type physical units in the storage area 1222 for centralized storage. Thereafter, the first type physical unit in the storage area 1221, in which valid data has been copied, can be associated with a free pool (free pool) and can be erased before the next use, thereby achieving the purpose of releasing the available space in the storage area 1221.

In one embodiment, during the data consolidation operation, the memory controller 121 may update the management table in the persistent memory 112 via the connection between the host system 11 and the memory device 12, and copy the target data from m (e.g., 3 or 4) entity units of the first type in the storage area 1221 to n (e.g., 1) entity units of the second type in the storage area 1222 for storage according to the update result.

In one embodiment, memory controller 121 may update the management table in persistent memory 112 based on the new logical-to-physical mapping information associated with the target material. For example, assume that the management table (i.e., the logical-to-physical mapping table) originally read from the nonvolatile memory module 122 records old logical-to-physical mapping information associated with the target data. The old logical-to-physical mapping information may reflect an old mapping relationship between an old physical unit (i.e., the first type of physical unit) originally used to store the target data and the logical unit to which the target data belongs.

After storing the management table in the persistent memory 112, the memory controller 121 may modify and update the information in the management table in the persistent memory 112. For example, the memory controller 121 may update old logic-to-entity mapping information associated with the target profile to new logic-to-entity mapping information associated with the target profile in the persistent memory 112. The new logical-to-physical mapping information may be reflected in the data consolidation operation to store a new mapping relationship between a new physical unit (i.e., a second type of physical unit) of the target data and the logical unit to which the target data belongs. That is, the updated management table in the persistent storage 112 can reflect the new mapping relationship between the entity unit (i.e., the second type entity unit) that is finally used to store the target data and the logic unit to which the target data belongs in the data sorting operation.

In one embodiment, after completing the data sorting operation, the memory controller 121 may read the updated management table back from the persistent memory 112 and store it back into the non-volatile memory module 122. Thereafter, when the target data needs to be accessed, the memory controller 121 may determine the physical unit currently used to store the target data according to the management table.

In an embodiment, the processor 111 of the host system 11 may also configure storage space in the persistent memory 112 that is allowed to be provided for use by the memory device 12 to operate in the persistent mode. In the persistent mode, the management table stored in the persistent memory 112 will not be lost due to an unexpected power down of the host system 11. Thereby, the reliability of the memory device 12 performing the data sorting operation can be improved.

In one embodiment, if the memory device 12 is a DRAM-less memory device (i.e. the memory device 12 has no DRAM or insufficient storage space of DRAM), the memory device 12 can only use the SRAM in the memory controller 121 and/or the nonvolatile memory module 122 to store the management table without using the persistent memory 112 in the host system 11 (or only using the volatile memory such as DRAM in the host system 11). If the data amount of the management table is larger than the capacity of the SRAM, the management table needs to be stored in the SRAM in batch for querying and modifying during the execution of the data sorting operation, thereby reducing the execution efficiency of the data sorting operation.

In one embodiment, it is assumed that the memory device 12 is a DRAM-less memory device (i.e., there is no DRAM in the memory device 12 or insufficient storage space for DRAM). However, on the premise that the persistent memory 112 in the host system 11 can be used (and the storage space in the available persistent memory 112 is operated in the persistent mode), the execution efficiency of the data organization operation can be effectively improved by storing the management table by the large-capacity persistent memory 112 with data persistence.

In one embodiment, regardless of whether the memory device 12 has enough DRAM storage space, the management table required for performing the data sorting operation can be transmitted to the persistent memory 112 of the host system 11 for storage, query and update at a time during the data sorting operation, thereby improving the execution efficiency of the data sorting operation. After the profiling operation is completed, the management table updated in the persistent memory 112 can be restored to the non-volatile memory module 122 of the memory device 12 for subsequent use.

FIG. 2 is a flow chart illustrating a data organization method using persistent memory according to an embodiment of the invention. Referring to fig. 2, in step S201, a persistent memory in a host system is enabled. In step S202, in a state where a connection between the host system and a memory device is established, a management table maintained by the memory device is stored in the persistent memory. In step S203, during the data sorting operation performed by the memory device, the memory device updates the management table in the persistent memory via the connection, and copies the target data from at least one first type entity unit in the memory device to at least one second type entity unit in the memory device for storage according to the update result.

However, the steps in fig. 2 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 2 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 2 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the embodiments of the invention can use the persistent memory with data persistence on the host system side to store the management table required for executing the data organization operation when the memory device executes the internal data organization operation. Therefore, the operating efficiency of the memory storage device for executing internal data arrangement can be effectively improved.

Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for collating data using persistent memory, comprising:

enabling a persistent memory in a host system;

storing a management table maintained by a memory device into the persistent memory in a state where a connection between the host system and the memory device is established; and

during the process of executing a data sorting operation, the memory device updates the management table in the persistent memory via the connection, and copies a target data from at least one first type entity unit in the memory device to at least one second type entity unit in the memory device for storage according to an update result.

2. The method of claim 1, wherein the persistent storage is operable in a volatile mode and a persistent mode,

in the volatile mode, data stored in the persistent memory is lost due to the host system being powered down, and

in the persistent mode, the data stored in the persistent memory is not lost due to the host system being powered down.

3. The method as claimed in claim 2, further comprising:

at least a portion of the storage space of the persistent memory is configured to operate in the persistent mode, and the management table is stored in the at least a portion of the storage space operating in the persistent mode.

4. The method as claimed in claim 1, wherein the at least one first type of physical unit and the at least one second type of physical unit are both included in a non-volatile memory module of the memory device, a single memory cell of the at least one first type of physical unit is configured to store n bits, a single memory cell of the at least one second type of physical unit is configured to store m bits, m and n are positive integers, and m is greater than n.

5. The method as claimed in claim 1, wherein the management table comprises a logical-to-physical mapping table.

6. A memory storage system using persistent memory, comprising:

a host system configured with a persistent memory; and

a memory device coupled to the host system,

wherein the host system is configured to enable the persistent memory,

in a state where a connection between the host system and the memory device is established, a memory controller of the memory device stores a management table maintained by the memory device in the persistent memory, and

during the process of executing a data sorting operation by the memory device, the memory controller updates the management table in the persistent memory via the connection, and copies a target data from at least one first type entity unit in the memory device to at least one second type entity unit in the memory device for storage according to an update result.

7. The memory storage system of claim 6, wherein said persistent memory is operable in a volatile mode and a persistent mode,

8. The memory storage system of claim 7, wherein said host system is further configured to configure at least a portion of storage space of said persistent memory to operate in said persistent mode, and wherein said host system is further configured to configure at least a portion of storage space of said persistent memory to operate in said persistent mode

The management table is stored in the at least a portion of the storage space operating in the persistent mode.

9. The memory storage system of claim 6, wherein the at least one first type of physical unit and the at least one second type of physical unit are both included in a non-volatile memory module of the memory device, a single memory cell of the at least one first type of physical unit is configured to store n bits, a single memory cell of the at least one second type of physical unit is configured to store m bits, m and n are positive integers, and m is greater than n.

10. The memory storage system of claim 6, wherein the management table comprises a logic-to-entity mapping table.