CN110309081B - FTL data page reading and writing method based on compressed storage and address mapping table entry - Google Patents

FTL data page reading and writing method based on compressed storage and address mapping table entry Download PDF

Info

Publication number
CN110309081B
CN110309081B CN201910476609.9A CN201910476609A CN110309081B CN 110309081 B CN110309081 B CN 110309081B CN 201910476609 A CN201910476609 A CN 201910476609A CN 110309081 B CN110309081 B CN 110309081B
Authority
CN
China
Prior art keywords
page
data
logical
pages
compressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910476609.9A
Other languages
Chinese (zh)
Other versions
CN110309081A (en
Inventor
潘玉彪
张惠臻
王成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huaqiao University
Original Assignee
Huaqiao University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huaqiao University filed Critical Huaqiao University
Priority to CN201910476609.9A priority Critical patent/CN110309081B/en
Publication of CN110309081A publication Critical patent/CN110309081A/en
Application granted granted Critical
Publication of CN110309081B publication Critical patent/CN110309081B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention discloses a method for FTL to read and write a data page based on compressed storage and address mapping table entries, which comprises the following steps: for a data page needing to be written is issued by a host, an FTL mechanism based on compression tries to compress the S pages into a page size range together through a specific compression algorithm; designing address mapping table entries, recording the corresponding relation between a logical page number and a physical page number in each mapping table entry, adding N-bit storage overhead to each table entry, and recording the state (sequence) information of the logical page after aggregation compression; the FTL reads the data page; the FTL writes the data page. The invention can avoid generating write amplification, reduce the storage cost of the mapping table and obtain good compression ratio.

Description

FTL data page reading and writing method based on compressed storage and address mapping table entry
Technical Field
The invention relates to the field of computer storage, in particular to a method for FTL (flash translation layer) reading and writing data pages based on compressed storage and address mapping table entries.
Background
Due to the advantages of the solid state disk in various aspects such as performance, energy consumption and shock resistance, the solid state disk has been deployed in large-scale systems such as data centers as an important storage medium by most companies. However, there is a limit to the number of erasures (P/E) per cell in a solid state disk, such as SLC type solid state disk, which has about 10 ten thousand erasures per block. When the erasing frequency of a block reaches the limit, the data stored in the block is likely to generate bit errors, and the service life of the solid state disk is influenced.
Thus, in the same case, fewer data writes will result in fewer erasures. Data compression techniques provide solid state disk designers with an option to extend solid state disks. A solid state disk designer can deploy a data compression technology to a Flash Translation Layer (FTL) inside a solid state disk, and data stored in the solid state disk by a user is compressed and then stored on a flash memory chip. According to the method, from the perspective of a user, the written data volume is unchanged; but from the flash memory perspective, the data write volume is indeed reduced. In addition, as the data actually written and read becomes smaller, the solid state disk access performance can be improved.
The unit of the internal read-write operation of the solid state disk is a Page (Page), and the size of each Page is generally 4KB; when the data compression technology compresses the page data, it will generate data smaller (compressible data) or larger (non-compressible data) than one page size, so the address mapping table design needs to be modified so that the FTL can correctly identify the compressed data and correctly read or write the compressed data.
The traditional method comprises the steps of page independent compression single-page storage, page combination compression cross-page storage and page independent compression cross-page storage. 1) The page single-page compression single-page storage requires that the FTL compresses all written page data one by one and puts the data into a certain page, and if the space of the certain page is not enough, an empty page is reallocated for writing; the process is inefficient. 2) Page combination compression cross-page storage, which requires that an FTL caches a plurality of pages first, and uniformly compresses and stores the pages on a medium in a cross-page manner; although the compression rate is improved, read amplification is introduced, i.e. if one 4KB page is to be read, multiple 4KB are read, because the data is compressed in one block, which results in decompression requiring other data to be correctly decompressed. 3) Page-only, page-spread storage can improve compression relative to the first approach, but still introduces read amplification due to page-spread storage. In addition, in all three methods, marking data such as offset in a page, page size after compression and the like are added to each mapping table item, and the information increases the size of the mapping table. For example, an internal page of a 256GB solid-state hard disk is 4KB, so the intra-page offset needs 12 bits to represent, the page size needs 12 bits to represent after compression, and an extra 1 bit is needed to represent whether compression is performed, and finally the entire mapping table needs an extra (12 + 1) × 256GB/4KB =200mb space.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a method for FTL to read and write a data page based on compressed storage and address mapping table entries, can avoid the generation of write amplification, reduces the storage overhead of a mapping table, and can obtain good compression rate.
The technical scheme adopted by the invention for solving the technical problem is as follows:
in one aspect, the present invention provides a method for an FTL to read a data page based on a compressed storage and address mapping table entry, including:
for a data page needing to be written is issued by a host, the FTL of the solid state disk caches the data page in the built-in RAM; when buffer 2 in RAMNS pages in RAM (1 < = S < = 2) at 1 page or at the time of a write operation forced by the hostN-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter;
each address mapping table entry records the corresponding relation between a logical page number and a physical page number, the storage overhead of N bits is added for each mapping table entry, and the state information of the logical page after aggregation compression is recorded; when one logical page cannot be compressed or cannot be compressed together with the next logical page into a physical page size range, setting the state information of the logical page to be 0; otherwise, indicating that multiple logical pages can be compressed together for storage on a particular physical page, 1 to 2 of the N-bit representation are usedN-1 kind of state information is assigned to the corresponding logical pages in order;
and the FTL reads the data page.
Preferably, the FTL reads the data page, which specifically includes:
step 21, the ftl searches the corresponding table entry of the address mapping table according to the logical page number of the read request issued by the host, and obtains the corresponding physical page number and N-bit state information i, where 0 < = i < =2N-1；
Step 22, finding the flash memory page and reading the page data by the FTL through the physical page number;
step 23, judging whether the acquired state i is 0; if 0, jumping to step 24; otherwise, jumping to step 25;
step 24, the state i is 0, which indicates that the read physical page data is original data, and the data is returned to the host;
step 25, the state i is not 0, which indicates that the read physical page data is compressed data; decompressing the physical page data by using a decompression algorithm;
step 26, decompressing a 4KB data;
step 27, judging whether the 4KB in the step 26 is the ith 4KB data, if so, jumping to the step 28; otherwise, jumping to step 26, continuing the decompression operation, and decompressing the next 4KB data;
step 28, stop the decompression algorithm and return the ith 4KB to the host, completing a page read.
On the other hand, the invention discloses a method for FTL to write data pages based on compressed storage and address mapping table entries, which comprises the following steps: for a data page needing to be written is issued by a host, the FTL of the solid state disk caches the data page in the built-in RAM; when buffering 2 in RAMNS pages in RAM (1 < = S < = 2) at 1 page or at the time of host forced issuing of write operationN-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter;
each address mapping table entry records the corresponding relation between a logical page number and a physical page number, adds N-bit storage overhead for each mapping table entry, and records the state information of the logical page after aggregation compression; when one logical page cannot be compressed or cannot be compressed together with the next logical page into a physical page size range, setting the state information of the logical page to be 0; otherwise, indicating that multiple logical pages can be compressed together for storage on a particular physical page, 1 to 2 of the N-bit representation are usedN-1 kind of state information is assigned to the corresponding logical pages in order;
the FTL writes the data page.
Preferably, the writing of the FTL to the data page specifically includes:
step 41, sending the cached S logic pages into a writing flow in an RAM of the FTL;
step 42, initializing i to 1, representing a first logical page, trying to compress the first 1/4 of the data of the first logical page, and judging whether the page is compressible; if not, jumping to step 43; if compression is possible, go to step 44;
step 43, if the compression cannot be performed, it indicates that the first logical page cannot be compressed either or cannot be compressed together with the second logical page to a physical page; at this time, writing the original data of the first logical page into the allocated physical page, updating the mapping table entry for the logical page, and setting the N-bit state information as 0; finally, the subsequent S-1 logical pages are put back into the RAM; skipping to step 49;
step 44, making i = i +1, judging whether i is greater than S, and if so, jumping to step 45; otherwise, go to step 46;
step 45, testing whether i-1 is equal to 1, if so, indicating that the first logical page and the second logical page can not be compressed into a physical page together, or indicating that S is equal to 1, and jumping to step 43; otherwise, a plurality of logical pages can be compressed into one physical page, and the step 48 is jumped to;
step 46, trying to compress the ith logical page and the first i-1 logical pages into a physical page;
step 47, judging whether the compression result of the ith logical page and the previous i-1 logical pages is less than or equal to one physical page, if so, jumping to step 44; otherwise, jumping to step 45;
step 48, indicating that the result of compressing the first i-1 logical pages together can be put into one physical page at most, writing the result into the allocated physical page, writing the same physical page number into the mapping table entry corresponding to the first i-1 logical pages, updating the respective N-bit state information according to the sequence, and finally putting the subsequent S-i +1 pages back into the RAM;
step 49, completing the write once page.
The invention has the following beneficial effects:
(1) The method for FTL to read and write the data page based on the compressed storage and the address mapping table entry does not introduce read amplification, because a plurality of logical page data can be compressed into one physical page only, each logical page read request just triggers one physical page read request;
(2) The invention relates to a method for FTL to read and write data pages based on compressed storage and address mapping table entries, which has the advantages that the additional consumption of the storage space of the mapping table entries is minimum; according to the setting, each entry is increased by at most 5 bits (when the system sets N = 5), while other policies are increased by at least 25 bits per entry. Moreover, in the future when large-page solid state disks become a trend (e.g., page size increases by 8 KB), the benefit of the invention is more obvious because the overhead per entry is fixed (5 bits at most), while other strategies increase the overhead per entry as the page increases, eventually consuming more RAM space, affecting performance;
(3) Compared with the method for compressing a single page, the method for reading and writing the data page by the FTL based on the compressed storage and the address mapping table entry can obtain a moderate and acceptable compression rate by compressing a plurality of page data together, thereby prolonging the service life of the solid state disk.
The present invention will be described in further detail with reference to the accompanying drawings and embodiments, but the method for the FTL to read and write data pages based on compressed storage and address mapping table entries according to the present invention is not limited to the embodiments.
Drawings
FIG. 1 is a diagram of compression-based FTL mechanism and map table design according to the present invention
FIG. 2 is a read flow chart of the compression-based FTL mechanism and the mapping table design according to an embodiment of the present invention
Fig. 3 is a write flow diagram of a compression-based FTL mechanism and a map entry design according to a second embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments.
Example one
In one aspect, the present invention provides a method for an FTL to read a data page based on a compressed storage and address mapping table entry, which includes:
step 1, for a data page needing to be written in issued by a host, FTL of a solid state diskCaching the data in a built-in RAM; when buffering 2 in RAMNS pages in RAM (1 < = S < = 2) at 1 page or at the time of a write operation forced by the hostN-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter; if the host generated data is convenient for compression, N may be set to 4 or 5; otherwise N is set to 2 or 3.
Attempting to compress S pages together into a physical page size range would yield three possibilities:
1) The compression rate is good, and S page data can be compressed into one physical page;
2) The compression rate is general, data of t pages (1 < t < S) can be compressed into one physical page;
3) The compression rate is poor, only one page data can be compressed into one physical page or the page cannot be compressed.
And step 2, each mapping table entry records the corresponding relation between the logical page number and the physical page number, and in order to support the compression characteristic (a plurality of logical pages are compressed and stored on one physical page), the storage overhead of N bits is added to each mapping table entry. The N bits may represent 2NA state, wherein all 0 states indicate that the physical page corresponding to the logical page is compressed, and the stored data is original data; the rest 2N-1 status indication indicating that the logical page is compressed together with other logical page data for storage on a particular physical page, and the status of the N-bit representation (non-all zeros) indicating the number of the logical page at the time of compression, which number is available to correctly respond to a read operation.
For example, in the setting of N =3, it is possible to compress 2 of logical page numbers a, B, C, D, E, F, and G (compressed together in the order from a → G), respectively3-1=7 pages of data are compressed together into one physical page (physical page number X). Therefore, mapping table entries of seven logical pages, a, B, C, D, E, F and G, all point to the physical page number X, except that the 3 bits added to each table entry are different, namely, the last 3 bits 001 of logical page a, the last 3 bits 010 of logical page B, and the last 3 bits 010 of logical page C3-bit 011, last 3-bit 100 of logical page D, last 3-bit 101 of logical page E, last 3-bit 110 of logical page F, and last 3-bit 111 of logical page G. Supposing that the logical page B needs to be read, the logical page B is known to be stored on the physical page X through the mapping table entry, so that the physical page X is read out; since the last 3 bits of the mapping table entry of logical page B are 010, it means that physical page X stores compressed data, decompresses the compressed data, and indicates decimal 2 according to 010, so the second 4KB is intercepted from the decompressed data, i.e. the data of logical page B that the system wants to read.
As shown in FIG. 1 (a), 2 or more3-1=7 logical page data can be compressed into one physical page. At this time, the physical page numbers of the logical pages 0000, 0001, 0002, 0003, 0004, 0005 and 0006 in their respective address mapping table entries are all 0105, and their additionally added 3-bit state information is 001, 010, 011, 100, 101, 110 and 111, respectively.
FIG. 1 (b) shows that 4 (1 < 4 < 7) logical pages of data can be compressed into one physical page. At this time, the corresponding physical page numbers of the logical pages 0000, 0001, 0002 and 0003 in their respective address mapping table entries are 0105, and their additionally added 3-bit state information is 001, 010, 011 and 100.
Fig. 1 (c) shows that the first two logical page data cannot be compressed in both physical pages or the first logical page data cannot be compressed. At this time, the original data of the first logical page is directly written into the allocated physical page, and the physical page number of the logical page 0000 in the address mapping table entry is 0105, and its additionally added 3-bit status information is 000.
Step 3, FTL reads the data page, including:
1) Firstly, a host issues a logical page number to be read, an FTL of a solid state disk queries a corresponding mapping table entry in a mapping table according to the logical page number, and acquires a corresponding physical page number and additionally added N-bit state information;
2) Secondly, the FTL sends out a reading operation to read out the page content corresponding to the physical page number;
3) Then, whether the read N-bit state information is all zeros is determined. If all the page data are 0, the read physical page data are original data, namely the page content is the content required by the host read operation; otherwise, decompressing the page data, and intercepting the needed page data according to the decimal system represented by the N bits;
4) And finally, returning page data required by the host.
Referring to fig. 2, specifically, the method includes the following steps:
step 21, the ftl searches the corresponding table entry of the address mapping table according to the logical page number of the read request issued by the host, and obtains the corresponding physical page number and N-bit state information i, where 0 < = i < =2N-1；
Step 22, finding the flash memory page and reading the page data by the FTL through the physical page number;
step 23, judging whether the acquired state i is 0; if the value is 0, jumping to step 24; otherwise, jumping to step 25;
step 24, the state i is 0, which indicates that the read physical page data is original data, and the data is returned to the host;
step 25, the state i is not 0, which indicates that the read physical page data is compressed data; decompressing the physical page data by using a decompression algorithm;
step 26, decompressing a 4KB data;
step 27, determining whether the 4KB in step 26 is the ith 4KB data, if yes, jumping to step 28; otherwise, jumping to step 26, continuing the decompression operation, and decompressing the next 4KB data;
step 28, stop the decompression algorithm and return the ith 4KB to the host, completing a page read.
Example two
The invention discloses a method for writing data pages by an FTL (fiber to the Home) based on compressed storage and address mapping table entries, which comprises the following steps:
step 1, for a host machine to issue a data page needing to be written in, an FTL (flash translation layer) of a solid state disk caches the data page in an internal RAM (random access memory); when buffering 2 in RAMN-1 page or host forced down write operationIn operation, S pages (1 < = S < = 2) in RAMN-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter; if the host generated data is convenient for compression, N may be set to 4 or 5; otherwise N is set to 2 or 3.
Attempting to compress S pages together into a physical page size range would yield three possibilities:
1) The compression rate is good, and S page data can be compressed into one physical page;
2) The compression rate is general, data of t pages (1 < t < S) can be compressed into one physical page;
3) The compression rate is poor, only one page data can be compressed into one physical page or the page cannot be compressed.
Step 2, each mapping table entry records the corresponding relation between the logical page number and the physical page number, and in order to support the compression characteristic (a plurality of logical pages are compressed and stored on one physical page), the storage overhead of N bits is added to each mapping table entry. The N bits may represent 2NA state, wherein all 0 states indicate that the physical page corresponding to the logical page is compressed, and the stored data is original data; the rest 2N-1 status indication indicating that the logical page is compressed together with other logical page data for storage on a particular physical page, and the status of the N-bit representation (non-all zeros) indicating the number of the logical page at the time of compression, which number is available to correctly respond to a read operation.
For example, in the setting of N =3, it is possible to compress 2 of logical page numbers a, B, C, D, E, F, and G (compressed together in the order from a → G), respectively3-1=7 pages of data compressed together into one physical page (physical page number X). Therefore, mapping table entries of seven logical pages, namely, a, B, C, D, E, F and G all point to a physical page number X, except that the 3 bits added to each table entry are different, namely, the last 3 bits 001 of logical page a, the last 3 bits 010 of logical page B, the last 3 bits 011 of logical page C, the last 3 bits 100 of logical page D, the last 3 bits 101 of logical page E, and the last 3 bits of logical page F110, logical page G last 3 bits 111. Supposing that the logical page B needs to be read, the logical page B is known to be stored on the physical page X through the mapping table entry, so that the physical page X is read out; since the last 3 bits of the mapping table entry of logical page B are 010, it means that physical page X stores compressed data, decompresses the compressed data, and indicates decimal 2 according to 010, so the second 4KB is intercepted from the decompressed data, i.e. the data of logical page B that the system wants to read.
As shown in FIG. 1 (a), 2 or more3-1=7 logical pages of data can be compressed into one physical page. At this time, the physical page numbers of the logical pages 0000, 0001, 0002, 0003, 0004, 0005 and 0006 in their respective address mapping table entries are all 0105, and their additionally added 3-bit state information is 001, 010, 011, 100, 101, 110 and 111, respectively.
FIG. 1 (b) shows that 4 (1 < 4 < 7) logical pages of data can be compressed into one physical page. At this time, the corresponding physical page numbers of the logical pages 0000, 0001, 0002 and 0003 in their respective address mapping table entries are 0105, and their additionally added 3-bit state information is 001, 010, 011 and 100.
Fig. 1 (c) shows that the first two logical page data cannot be compressed in both physical pages or the first logical page data cannot be compressed. At this time, the original data of the first logical page is directly written into the allocated physical page, the physical page number of the logical page 0000 in the address mapping table entry is 0105, and the additionally added 3-bit status information is 000.
Step 3, the ftl writes the data page, including:
1) For S page data needing to be written and buffered in the RAM, testing whether the first 1/4 content of the first page data is compressible, if the first page data is not compressible, writing original data into a distributed physical page, modifying a physical page number in a logical page table entry in a mapping table, setting extra N-bit state information to be 0, and then putting the rest S-1 pages back into the RAM to finish the writing operation of one physical page; otherwise, the first page is compressed and then the remaining pages are compressed.
2) And then, trying to compress the first multiple pages of datse:Sup>A in the S into one physical page, and if A (1 < A < = S) pages can be compressed into one physical page, writing the compressed datse:Sup>A into the allocated physical page, modifying the physical page number in the A logical page table entries (A logical pages correspond to the same physical page), sequentially changing the N-bit state information corresponding to the A logical page table entries into binary systems corresponding to the decimal 1, 2.
Referring to fig. 3, specifically, the method includes the following steps:
step 41, sending the cached S logic pages into a writing flow in an RAM of the FTL;
step 42, initializing i to 1, representing the first logical page, trying to compress the first 1/4 of the data of the first logical page, and judging whether the page is compressible; if not, go to step 43; if compression is possible, go to step 44;
step 43, if the compression cannot be performed, it indicates that the first logical page cannot be compressed either, or cannot be compressed together with the second logical page to a physical page; at this time, writing the original data of the first logical page into the allocated physical page, updating the mapping table entry for the logical page, and setting the N-bit state information as 0; finally, the subsequent S-1 logical pages are put back into the RAM; jump to step 49;
step 44, making i = i +1, judging whether i is greater than S, and if so, jumping to step 45; otherwise, go to step 46;
step 45, testing whether i-1 is equal to 1, if so, indicating that the first logical page and the second logical page can not be compressed into one physical page together, or indicating that S is equal to 1, and jumping to step 43; otherwise, a plurality of logical pages can be compressed into one physical page, and the step 48 is jumped to;
step 46, trying to compress the ith logical page and the first i-1 logical pages into a physical page;
step 47, judging whether the compression result of the ith logical page and the first i-1 logical pages is less than or equal to one physical page, if so, jumping to step 44; otherwise, jumping to step 45;
step 48, indicating that the result of compressing the first i-1 logical pages together can be put into one physical page at most, writing the result into the allocated physical page, writing the same physical page number into the mapping table entry corresponding to the first i-1 logical pages, updating the respective N-bit state information according to the sequence, and finally putting the subsequent S-i +1 pages back into the RAM;
step 49, completing the write once page.
The present invention is not limited to the above embodiments, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (2)

1. A method for FTL to read data page based on compressed storage and address mapping table entry is characterized in that:
for a data page needing to be written is issued by a host, the FTL of the solid state disk caches the data page in the built-in RAM; when buffer 2 in RAMN1 pages or S pages in RAM when the host forces a write operation (1)<＝S<＝2N-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter;
each address mapping table entry records the corresponding relation between a logical page number and a physical page number, adds N-bit storage overhead for each mapping table entry, and records the state information of the logical page after aggregation compression; when one logical page cannot be compressed or cannot be compressed together with the next logical page into a physical page size range, setting the state information of the logical page to be 0; otherwise, indicating that multiple logical pages can be compressed together for storage on a particular physical page, 1 to 2 of the N-bit representation are usedN-1 kind of state information is assigned to the corresponding logical pages in order; wherein the state represented by the N bits indicates the number of the logical page when compressed;
the FTL reads the data page;
the FTL reads the data page, specifically including:
step 21, FTL searches the corresponding table entry of the address mapping table according to the logical page number of the read request issued by the host, and obtains the corresponding physical page number and N bit state information i, wherein 0<＝i<＝2N-1；
Step 22, finding the flash memory page and reading the page data by the FTL through the physical page number;
step 23, judging whether the acquired state i is 0; if 0, jumping to step 24; otherwise, jumping to step 25;
step 24, the state i is 0, which indicates that the read physical page data is original data, and the data is returned to the host;
step 25, the state i is not 0, which indicates that the read physical page data is compressed data; decompressing the physical page data by using a decompression algorithm;
step 26, decompressing a 4KB data;
step 27, judging whether the 4KB in the step 26 is the ith 4KB data, if so, jumping to the step 28; otherwise, jumping to step 26, continuing the decompression operation, and decompressing the next 4KB data;
step 28, stop the decompression algorithm and return the ith 4KB to the host, completing a page read.
2. A method for FTL to write data page based on compressed storage and address mapping table entry is characterized by comprising: for a data page needing to be written is issued by a host, the FTL of the solid state disk caches the data page in the built-in RAM; when buffer 2 in RAMN1 pages or S pages in RAM when the host forces a write operation (1)<＝S<＝2N-1) feeding compression means attempting to compress the S pages together into a physical page size range by means of a predetermined compression algorithm; wherein N is a preset system parameter;
each address mapping table entry records the corresponding relation between the logical page number and the physical page number, adds N-bit storage overhead for each mapping table entry, and records the logical page passingAggregating the state information after compression; when one logical page cannot be compressed or cannot be compressed together with the next logical page into a physical page size range, setting the state information of the logical page to be 0; otherwise, indicating that multiple logical pages can be compressed together for storage on a particular physical page, 1 to 2 of the N-bit representation are usedN-1 kind of state information is assigned to the corresponding logical pages in order; wherein the state represented by the N bits indicates the number of the logical page when compressed;
the FTL writes the data page;
the FTL writes in the data page, specifically including:
step 41, sending the cached S logic pages into a writing flow in an RAM of the FTL;
step 42, initializing i to 1, representing a first logical page, trying to compress the first 1/4 of the data of the first logical page, and judging whether the page is compressible; if not, jumping to step 43; if compression is possible, go to step 44;
step 43, if the compression cannot be performed, it indicates that the first logical page cannot be compressed either or cannot be compressed together with the second logical page to a physical page; at this time, writing the original data of the first logical page into the allocated physical page, updating the mapping table entry for the logical page, and setting the N-bit state information as 0; finally, the subsequent S-1 logical pages are put back into the RAM; jump to step 49;
step 44, making i = i +1, judging whether i is greater than S, and if so, jumping to step 45; otherwise, go to step 46;
step 45, testing whether i-1 is equal to 1, if so, indicating that the first logical page and the second logical page can not be compressed into a physical page together, or indicating that S is equal to 1, and jumping to step 43; otherwise, a plurality of logical pages can be compressed into one physical page, and the step 48 is jumped to;
step 46, trying to compress the ith logical page and the first i-1 logical pages into a physical page;
step 47, judging whether the compression result of the ith logical page and the first i-1 logical pages is less than or equal to one physical page, if so, jumping to step 44; otherwise, jumping to step 45;
step 48, indicating that the result of compressing the first i-1 logical pages together can be put into one physical page at most, writing the result into the allocated physical page, writing the same physical page number into the mapping table entry corresponding to the first i-1 logical pages, updating the respective N-bit state information according to the sequence, and finally putting the subsequent S-i +1 pages back into the RAM;
step 49, completing the write once page.
CN201910476609.9A 2019-06-03 2019-06-03 FTL data page reading and writing method based on compressed storage and address mapping table entry Active CN110309081B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910476609.9A CN110309081B (en) 2019-06-03 2019-06-03 FTL data page reading and writing method based on compressed storage and address mapping table entry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910476609.9A CN110309081B (en) 2019-06-03 2019-06-03 FTL data page reading and writing method based on compressed storage and address mapping table entry

Publications (2)

Publication Number Publication Date
CN110309081A CN110309081A (en) 2019-10-08
CN110309081B true CN110309081B (en) 2022-11-01

Family

ID=68074983

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910476609.9A Active CN110309081B (en) 2019-06-03 2019-06-03 FTL data page reading and writing method based on compressed storage and address mapping table entry

Country Status (1)

Country Link
CN (1) CN110309081B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111338989B (en) * 2020-02-12 2021-01-12 合肥康芯威存储技术有限公司 Memory, control method thereof and memory system
CN112486861B (en) * 2020-11-30 2024-05-14 深圳忆联信息系统有限公司 Solid state disk mapping table data query method and device, computer equipment and storage medium

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916228A (en) * 2010-08-17 2010-12-15 中国人民解放军国防科学技术大学 Flash translation layer (FTL) with data compression function and implementation method
CN102662856A (en) * 2012-04-27 2012-09-12 中国科学院计算技术研究所 Solid state disk and access method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101453313B1 (en) * 2013-03-25 2014-10-22 아주대학교산학협력단 Method for Page-level address mapping using flash memory and System thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101916228A (en) * 2010-08-17 2010-12-15 中国人民解放军国防科学技术大学 Flash translation layer (FTL) with data compression function and implementation method
CN102662856A (en) * 2012-04-27 2012-09-12 中国科学院计算技术研究所 Solid state disk and access method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于区域页级映射的闪存转换层设计;蔡晓乐等;《微电子学与计算机》;20160405(第04期);全文 *

Also Published As

Publication number Publication date
CN110309081A (en) 2019-10-08

Similar Documents

Publication Publication Date Title
US11789860B2 (en) Logical to physical mapping management using low-latency non-volatile memory
US8516219B2 (en) Index cache tree
US10275361B2 (en) Managing multiple namespaces in a non-volatile memory (NVM)
US20100011156A1 (en) Memory device and management method of memory device
CN113419675B (en) Write operation method and read operation method for memory
CN112463647A (en) Reducing the size of the forward mapping table using hashing
CN110309081B (en) FTL data page reading and writing method based on compressed storage and address mapping table entry
US20120131264A1 (en) Storage device
US11176033B2 (en) Data storage devices and data processing methods
CN113724775A (en) Meta information management method, solid state disk controller and solid state disk
CN113419975A (en) Control system of memory, address mapping method and address mapping device
CN114036079B (en) Mapping table compression method and system, memory controller, solid state disk and data reading method
CN113778337B (en) Solid state disk based on flash memory and data management method thereof
CN112035065B (en) Data writing method, device and equipment and computer readable storage medium
US7185020B2 (en) Generating one or more block addresses based on an identifier of a hierarchical data structure
US10289334B2 (en) Valid data merging method, memory controller and memory storage apparatus
CN108304331B (en) NorFlash-based circular queue type data storage method and device
CN113448487A (en) Computer readable storage medium, method and device for writing flash memory management table
US10942858B2 (en) Data storage devices and data processing methods
US11055231B2 (en) Data storage devices and data processing methods of skipping editing of fields in H2F table when consecutive addresses are present in F2H table
CN117891392A (en) Management method and system for compressed data of solid state disk
KR100261994B1 (en) Flash memory
CN117950590A (en) Method for optimizing ZenFS reset operation to prolong service life of ZNS-SSD
KR20220066402A (en) Self-Adaptive Wear Leveling Method and Algorithm
CN114238175A (en) Solid state disk FTL algorithm address mapping method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant