CN114237091A - Power electronic converter state data acquisition device - Google Patents
Power electronic converter state data acquisition device Download PDFInfo
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Abstract
The invention provides a state data acquisition device of a power electronic converter, which comprises a power electronic converter controller, a communication function board card and a monitoring upper computer; the power electronic converter controller and the communication function board card adopt high-speed optical fiber serial communication; the communication function board card and the monitoring upper computer adopt Ethernet communication; the high-speed optical fiber serial communication between the converter controller and the communication function board card adopts a user-defined high-speed serial protocol; the power electronic converter controller encodes the running state data of the power electronic converter according to a user-defined serial communication protocol and sends the encoded running state data to the communication function board card; the communication function board automatically decodes and converts the data into parallel data according to a user-defined serial communication protocol, and uploads the parallel data to a monitoring upper computer in real time; the invention realizes the transmission, storage and display of multi-channel and high-sampling-rate state data in the power electronic equipment so as to improve the transparency of the on-line operation and the reproducibility of the off-line operation of the converter.
Description
Technical Field
The invention belongs to the technical field of signal acquisition and communication control of a power electronic system, and particularly relates to a state data acquisition device of a power electronic converter.
Background
Along with the continuous improvement of the intelligent degree of a power electronic system, the visual operation of the power electronic power converter plays an important role in improving the usability of products and realizing the health management of the products. Especially for designers, the transparent operation of the converter is beneficial to improving the efficiency of debugging and optimal design and increasing the accuracy of troubleshooting and positioning. A complete data acquisition system in the equipment is just the premise of visual and transparent operation of the power electronic converter. At present, although medium-high power commercial and even military power electronic converters are provided with data acquisition systems including high-speed data acquisition channels such as voltage, current, on-off state and the like, the high-speed data acquisition is limited to internal control and protection, and for a visual upper computer, the transmission and display of limited and sampling rate-reduced state data in the equipment are still generally realized based on low-speed data communication, so that the online operation visualization degree of the system is greatly reduced. For example, in the currently common data acquisition and transmission systems based on buses such as RS232, RS485, CAN and the like, the data capacity is in the kbps level, the data capacity rarely reaches the Mbps level, the sampling rate of state data is in the hundred Hz level or even lower, and for a converter with high switching frequency, the state detection of an upper computer becomes a 'fuzzy' detection system. In addition, when the system runs off line, particularly when the system is in fault, few systems have a fault data storage function, and even if the systems exist, the system is based on a limited state data storage function with a low sampling rate, so that the rapid diagnosis and accurate positioning of the fault are seriously weakened. The special high-speed, multi-channel and multifunctional data acquisition system considers cost factors and is difficult to popularize and apply on products.
At present, the difficulty of popularization of a high-speed data acquisition system of a power electronic converter mainly lies in that: and a board card level developed data transmission mechanism which is easy to realize, low in cost and high in speed and a matched realization scheme thereof are lacked. Secondly, the lack of attention and investment of research and development designers on a high-speed data acquisition system suitable for a power electronic converter is also one of the reasons for the lack of visualization and transparent operation of the existing power electronic device.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a state data acquisition device for a power electronic converter, which realizes the acquisition, transmission, storage and display of multi-channel and high-sampling-rate real-time state data in power electronic equipment so as to improve the transparency of the on-line operation and the reproducibility of the off-line operation of the converter.
The technical scheme adopted by the invention is as follows: a state data acquisition device of a power electronic converter comprises a power electronic converter controller, a communication function board card and a monitoring upper computer; the power electronic converter controller and the communication function board card adopt high-speed optical fiber serial communication; the communication function board card and the monitoring upper computer adopt Ethernet communication; the high-speed optical fiber serial communication between the converter controller and the communication function board card adopts a user-defined high-speed serial protocol;
the power electronic converter controller encodes the running state data of the power electronic converter according to a user-defined serial communication protocol to form serial encoded data and sends the serial encoded data to the communication function board card; the communication function board automatically decodes the received serial coded data according to a user-defined serial communication protocol, converts the serial coded data into parallel data, and uploads the parallel data to a monitoring upper computer in real time according to an Ethernet communication protocol;
the monitoring upper computer sends control data to the communication function board card; the communication function board card converts received control data into parallel data according to an Ethernet communication protocol, encodes the parallel data according to a user-defined serial communication protocol to generate serial encoding data, and transmits the serial encoding data to the power electronic converter controller; the power electronic converter controller decodes and receives serial coded data according to a self-defined high-speed serial protocol, converts the serial coded data into control data, and executes corresponding operation according to the control data.
The technical scheme of the invention is a non-intrusive monitoring method, which is simple to realize on software and hardware and can realize hot plug connection.
In the technical scheme, the communication function board card is provided with a data buffer, a file management controller and a mobile storage medium; the communication function board card is used for converting the received state data from the power electronic converter controller or the control data from the monitoring upper computer into parallel data and then caching the parallel data into a data buffer; after the storage space of the data buffer is used up, a file management controller on the communication function board card executes the mobile medium data storage operation; the mobile medium data storage operation means that the file management controller stores all data in the data buffer into the mobile storage medium in sequence and generates a corresponding data file in the mobile storage medium. The data storage mechanism can accurately store the running state data of the power electronic converter which runs independently under each switching frequency, and further has the reproducibility of off-line running.
In the technical scheme, the monitoring upper computer issues control data through the man-machine interaction interface and displays the running state of the power electronic converter.
In the technical scheme, a high-speed serial communication mode based on an optical fiber link is adopted between the power electronic converter controller and the communication function board card, and a Manchester code is selected as a line code of the high-speed optical fiber serial communication; the power electronic converter controller or the communication function board card is used as a sending end, and parallel data to be sent are coded into serial coded data bit by bit according to a self-defined serial communication protocol and a coding rule of a Manchester code; the parallel data to be transmitted are state data or control data reflecting the operation of the power electronic converter in the power electronic converter controller. The self-defined serial communication protocol can be realized only by means of FPGA programming, and has the advantages of simple realization of software and hardware, low cost, high communication speed and hot-pluggable application.
In the above technical solution, the serial encoded data includes a synchronous decoding clock; a power electronic converter controller or a communication function board card is used as a receiving end and is provided with a clock data recovery module; after receiving the serial coded data, a receiving end firstly recovers a synchronous decoding clock from the serial coded data by using a clock data recovery module, and then samples the serial coded data by using the recovered synchronous decoding clock to obtain non-coded serial data; and decoding according to the self-defined serial communication protocol, and restoring the non-coded serial data into the originally sent parallel data. The decoding method can be realized by means of FPGA programming and has the characteristics of self-decoding and low hardware cost.
In the technical scheme, a sending end encodes and converts parallel data to be sent into serial encoding data according to a user-defined serial communication protocol and a Manchester code encoding format, packages the serial encoding data into a serial data frame, and sends the serial data frame according to an agreed frequency; the coding method can be realized by means of FPGA programming without additional hardware circuits.
The serial data frame format comprises a starting frame head, a plurality of serial coding data, 1 serial coding check data and an ending frame tail; the starting frame header is a high level with more than 2 bit numbers, and the inherent characteristics of the starting frame header can not appear in the serial coding data so as to represent the start of a frame of serial coding data and serve as a unique identifier for a receiving end to identify a serial data frame; the frame head is started and then the serial coding data is next, and the serial coding data is serial coding data bit stream converted from the parallel data to be transmitted according to the coding format of the Manchester code; after the serial coding check data is connected with the last serial coding data, the coding mode still adopts the coding format of Manchester code coding; the end frame is connected with the serial coding check data in a tail mode, is used for representing the end of one frame of serial coding data and is a low level with more than 2 bit numbers; the self-defined serial communication protocol has the characteristics of simple protocol and hot plug application.
In the above technical solution, the serial code check data is data generated by calculating all parallel data to be transmitted corresponding to one frame of serial code data by using a CRC check algorithm; after the receiving end decodes and receives a frame of serial encoding data, all parallel data except the check data corresponding to the serial encoding data in the serial data frame are calculated by adopting the same CRC (cyclic redundancy check) algorithm to generate a new check value, the new check value is compared with the serial encoding check data in the frame of serial encoding data received by decoding, and if the new check value is equal to the serial encoding check data, the receiving end judges that the frame of serial encoding data is correctly encoded and decoded and transmitted and continues to execute subsequent decoding operation; if the new check value is not equal to the serial encoding check data, the receiving end judges that the frame of serial encoding data is encoded and decoded and has transmission errors, and the receiving end requests the sending end to resend the serial data frame.
In the technical scheme, the transmitting end is provided with an optical fiber transmitting port, and the receiving end is provided with an optical fiber receiving port; the method comprises the steps that a sending end converts a serial data frame to be sent into a serial optical signal from a serial electric signal through an optical fiber sending port, and sends the serial optical signal to an optical fiber link for connecting the sending end and a receiving end bit by bit; the receiving end converts the received serial data frame from a serial optical signal into a serial electric signal through the optical fiber receiving end.
In the above technical solution, the communication function board is configured with an FPGA timing and logic control module and an ethernet controller; the self-defined high-speed serial communication protocol is developed by adopting an FPGA; the Ethernet communication is developed by adopting an FPGA, and a TCP or UDP protocol is adopted; the FPGA timing and logic control module decodes the serial coded data to obtain parallel data based on a synchronous decoding clock obtained by clock data recovery, and sends the parallel data to the Ethernet controller; under the control of the FPGA data sending time sequence, the Ethernet controller transmits the parallel data words to a monitoring upper computer in real time through an Ethernet interface according to a TCP protocol or a UDP protocol; the Ethernet controller receives control data from a monitoring upper computer through an Ethernet interface under the control of the FPGA data receiving time sequence, converts the received control data into parallel data and sends the parallel data to the FPGA time sequence and logic control module; the FPGA timing and logic control module is further used for initializing the Ethernet controller so as to configure the working mode of the Ethernet controller. The data acquisition scheme can acquire, transmit and store the running state data of the converter at the switching frequency, and has the characteristics of high data real-time performance and good data integrity.
In the technical scheme, the FPGA time sequence and logic control module caches parallel data obtained by decoding into a data buffer under the control of the FPGA data caching time sequence; under the control of an FPGA data storage time sequence, an operation file management controller executes the data storage operation of the mobile medium; after the communication function board card is powered on, the FPGA time sequence and logic control module executes one-time initialization on the file management controller so as to set the working mode of the file management controller and connect and operate the mobile storage medium.
The invention has the beneficial effects that: the invention adopts high-speed serial optical fiber communication, Ethernet communication and data storage technology developed based on FPGA to realize the online real-time high-speed data transmission and data storage functions between the power electronic converter controller and the monitoring upper computer in the operation process of the power electronic converter, thereby forming a set of power electronic converter state data acquisition system with complete functions. The invention has the technical effects of simple realization of software and hardware, high communication speed and high operation transparency of the power electronic converter.
Drawings
FIG. 1 is a block diagram of the system of the present invention;
FIG. 2 is a custom high-speed serial protocol implemented by FPGA programming of the present invention;
FIG. 3 is a schematic diagram of the custom high-speed serial communication codec of the present invention;
FIG. 4 is a functional block diagram of the FPGA programming of the present invention implementing Ethernet communications;
FIG. 5 is a functional block diagram of the FPGA programming implementation of the present invention for data storage.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
As shown in fig. 1, the invention provides a state data acquisition device for a power electronic converter, which mainly comprises a power electronic converter controller function part, a communication function board card function part and a monitoring upper computer function part. By utilizing the multithreading parallel processing capability of the FPGA, data receiving and sending and data storage operation in the communication function board card are carried out in parallel.
The power electronic converter controller comprises an FPGA, a clock data recovery module, an optical fiber sending port and an optical fiber receiving port. The FPGA encodes running state data of the power electronic converter according to a self-defined high-speed serial protocol and then sends the encoded running state data to the communication function board card through the optical fiber sending port under the control of FPGA time sequence and logic at appointed frequency, such as converter switching frequency, control frequency and the like.
The communication function board card comprises an FPGA, a clock data recovery module, an optical fiber sending port, an optical fiber receiving port, an Ethernet controller, an Ethernet interface, a data buffer, a file management controller and a mobile storage medium. The communication function board converts the serial optical signal into a serial electric signal through the optical fiber receiving port, and then directly recovers a synchronous decoding clock from serial encoding data through the clock data recovery module by adopting a phase-locked loop technology, and further samples the serial encoding data by utilizing the recovered synchronous decoding clock to obtain non-encoded serial data. The FPGA is provided with an FPGA time sequence and logic control module. Under the control of the FPGA time sequence and logic module, the non-coded serial data is converted and restored into parallel data according to the self-defined high-speed serial protocol coding format. The FPGA carries out Ethernet protocol conversion on the received parallel data, the Ethernet controller is controlled by utilizing the FPGA time sequence and logic module, the parallel data are sent to the monitoring upper computer through the Ethernet interface, and the real-time running state of the power electronic converter is displayed under the assistance of the software function of the monitoring upper computer. Meanwhile, the received parallel data is cached in a data buffer under the control of the FPGA time sequence and logic module. And under the control of the FPGA time sequence and logic module, the data in the data buffer is stored into an external mobile storage medium by driving the file management controller.
And on the other hand, the monitoring upper computer issues control data through the man-machine interaction interface, and the control data are transmitted to the Ethernet controller of the communication function board card through the Ethernet interface. And under the control of the FPGA time sequence and logic module, carrying out Ethernet protocol conversion on the control data received by the Ethernet controller to obtain parallel control data. Under the FPGA time sequence and logic control, the communication function board card encodes the parallel control data according to a self-defined high-speed serial protocol to generate serial encoding data, and then transmits the serial encoding data to an optical fiber receiving port of the power electronic converter controller through an optical fiber transmitting port. The power electronic converter controller converts a serial optical signal into a serial electric signal by using the optical fiber receiving port, then directly sends the serial electric signal into the clock data recovery module, recovers a synchronous decoding clock from serial coded data by using a phase-locked loop technology, and then samples the serial coded data by using the recovered synchronous decoding clock to obtain non-coded serial data. And decoding the non-coded serial data obtained by serial decoding into parallel control data according to a user-defined high-speed serial protocol, and executing corresponding operation according to the control data.
The state data acquisition device of the power electronic converter can be generally divided into high-speed data communication and data storage based on FPGA development and matched software and hardware thereof.
The high-speed data communication based on FPGA development mainly comprises high-speed optical fiber serial communication realized by FPGA programming and high-speed Ethernet communication realized by FPGA programming.
The power electronic converter controller and the communication function board card adopt a high-speed serial communication mode based on an optical fiber link, communication data are coded according to a user-defined serial communication protocol to form serial coding data, and the serial coding data are packaged into a serial data frame. The communication data, namely the parallel data, comprises state data of the power electronic converter and control data sent by the monitoring upper computer. The transmitting end transmits the serial data frames bit by bit on the optical fiber link at each encoding clock. The transmitting end is provided with an optical fiber transmitting port, and the receiving end is provided with an optical fiber receiving port; the method comprises the steps that a sending end converts a serial data frame to be sent into a serial optical signal from a serial electric signal through an optical fiber sending port, and sends the serial optical signal to an optical fiber link for connecting the sending end and a receiving end bit by bit; the receiving end converts the received serial data frame from a serial optical signal into a serial electric signal through the optical fiber receiving end.
The sending end sends the serial data frame formed by encoding according to the appointed frequency, such as the switching frequency and the control frequency of the converter. The receiving end converts the serial optical signal into a serial electric signal by using the optical fiber receiving port, directly recovers a synchronous decoding clock from serial coded data by using a clock data recovery module and a phase-locked loop technology, further samples the serial coded data by using the recovered synchronous decoding clock to obtain non-coded serial coded data, and then converts the non-coded serial data into parallel data according to a self-defined high-speed serial protocol coding format. The data of serial communication is state data and control data which are collected inside the power electronic converter controller in each switching period and can comprehensively reflect the operation of the power electronic converter. And the high-speed optical fiber serial communication realizes bidirectional data transmission between the power electronic converter controller and the communication function board card. The clock data recovery module adopted by the invention is realized by adopting an FPGA phase-locked loop, and can also be a special clock data recovery integrated circuit such as SY87700 AL.
The serial data frame format of the custom serial communication protocol developed based on the FPGA programming is shown in fig. 2. The serial data frame format comprises a starting frame head, a plurality of serial coding data, 1 serial coding check data and an ending frame tail. The start frame header is a high level with more than 2 bit numbers, and the inherent characteristics of the start frame header can not appear in the serial coding data so as to represent the start of one frame of serial coding data and serve as a unique identifier for identifying the serial data frame by the receiving end. The start frame header is followed by the serial encoded data. The serial encoded data is a bit stream of serial encoded data converted from parallel data to be transmitted according to the encoding format of the line code, so as to adapt to the optical fiber serial communication link. The line code used in the present invention is a manchester code. After the serial coding check data is connected with the last serial coding data, the coding mode still adopts a Manchester code coding format. And the serial code check adopts a CRC (cyclic redundancy check) algorithm to calculate all data to be transmitted to generate data. After the receiving end decodes and receives a frame of serial encoding data, all parallel data except the check data corresponding to the serial encoding data frame are calculated by adopting the same CRC algorithm to generate a new check value, and the new check value is compared with the serial encoding check word in the frame of serial encoding data received by decoding to check the correctness of encoding, decoding and transmission of the frame of serial encoding data. If the two check data are not equal, the data is checked to be correct, and the receiving end continues to execute decoding operation; if the two check data are not equal, the data check is wrong, and the receiving end requests the sending end to resend the serial data frame. The ending frame end represents the ending of a frame of serial coded data, is a low level with more than 2 bit numbers, and has the same bit width as that of the starting frame head. And after the receiving end identifies the end frame, judging that the receiving of one frame of data is finished.
The present invention presents an embodiment of a process for decoding serially encoded data, as shown in fig. 3. And at the data transmitting end, coding each bit data of the parallel data to be transmitted according to the coding protocol of the Manchester code. Wherein, data "1" is coded into "10", data "0" is coded into "01", each coded data contains 1 level jump. Further, all parallel data encodings form serial encoded data of "1" and "0". The serial encoded data includes both data information and encoding clock information. And the receiving end extracts the synchronous decoding clock from the serial coded data by using the clock data recovery module. And then, sampling from the serial coded data by using a synchronous decoding clock to obtain non-coded original data.
The invention realizes Ethernet communication based on FPGA programming, and the communication function board card mainly controls an Ethernet controller for FPGA programming so as to realize data sending and data receiving functions, as shown in FIG. 4. And the data transmission is realized after the communication function board card decodes and receives a frame of serial data frame transmitted by the power electronic converter controller. The FPGA time sequence and logic module comprises a data sending time sequence control module, a data receiving time sequence control module and an initialization module. And the data sending time sequence control module controls the Ethernet controller to transmit the decoded parallel data to the monitoring upper computer in real time according to an Ethernet communication TCP protocol or a UDP protocol. And the data receiving is that when the communication function board card monitors that data arrives at the Ethernet receiving port in real time, the data receiving time sequence control module is used for controlling the Ethernet controller to receive control data sent by the monitoring upper computer in real time according to the Ethernet communication TCP protocol or UDP protocol. After the communication function board card receives control data sent by an upper computer through the Ethernet, the FPGA time sequence and logic module serially encodes the control data into a frame of serial encoding data according to a self-defined high-speed serial protocol, and the frame of serial encoding data is sent to the power electronic converter controller through the optical fiber sending port. In addition, the FPGA timing and logic module realizes Ethernet communication based on FPGA programming, and the initialization module is used for initializing the Ethernet controller so as to configure the working mode of the Ethernet controller, such as communication rate, bus bit width, interrupt configuration, basic network information setting, buffer memory setting and the like. The Ethernet controller adopted in the invention is WIZnet W5300.
The data storage developed based on the FPGA comprises a data cache time sequence control module, a data cache, a data storage time sequence control module, a file management controller, an initialization module and a mobile storage medium, and realizes the functions of onboard high-speed data cache and data storage based on the mobile storage medium, as shown in FIG. 5. In the communication function board card, considering that the rate of receiving data is very high and the data volume of each frame of data is relatively small, a storage operation mode of executing once based on each frame of data is adopted, the data storage efficiency is low, and the file management controller cannot execute file operation quickly and frequently. Thus, the cache data buffer is utilized as a transition between real-time data reception and data storage. After each frame of data transmitted by the power electronic converter controller or the monitoring upper computer is decoded and received by the communication function board card, the data cache sequential control module drives the FPGA to cache the decoded data into the data cache under the control of the FPGA data cache sequential control. After the storage space of the data buffer is used up, the data storage time sequence control module drives the FPGA to execute one-time mobile medium data storage operation under the FPGA data storage time sequence control, the buffer data in the buffer is stored in the mobile storage medium, and a corresponding data file is generated in the mobile storage medium. In addition, after the communication function board card is powered on, the initialization module is used for driving the FPGA to execute one-time initialization on the file management controller so as to set the operation mode of the file management controller, connect the mobile storage medium and the like. In the invention, the used data buffer is a high-capacity SRAM, the used file management controller is a CH378 chip, and the used mobile storage medium is a U disk or an SD card.
The matched software and hardware comprises communication function board card hardware such as an onboard power supply, an optical fiber and Ethernet communication port, a mobile memory (mobile storage medium) interface and the like, FPGA software for realizing high-speed data communication and data storage functions, and monitoring upper computer software for man-machine interaction and comprising functions of state display, data issuing control, data operation and the like. The communication function board card is provided with a corresponding onboard power supply circuit, a corresponding communication interface circuit and a corresponding memory interface circuit which are respectively used for accessing an onboard power supply, a corresponding communication interface and a corresponding mobile memory. The onboard power supply realizes the function of converting input voltage of the communication function board card into target required power supply voltage including 3.3V, 2.5V, 1.2V and the like. The optical fiber communication port is an optical fiber receiving and transmitting module for optical fiber serial communication and a peripheral circuit thereof, and photoelectric signal conversion is realized. The Ethernet communication port is an interface for realizing Ethernet communication and peripheral circuits thereof. The FPGA in the power electronic converter controller is configured with high-speed data communication FPGA software, and is mainly program software which is realized by FPGA programming and is used for controlling the encoding and decoding of the optical fiber serial communication. The FPGA on the communication function board card is provided with high-speed data communication FPGA software, program software which is mainly implemented by FPGA programming and used for controlling the encoding and decoding of the optical fiber serial communication, and program software which is implemented by FPGA programming and used for controlling an Ethernet controller to implement Ethernet communication. The FPGA on the communication function board card is provided with data storage FPGA software, and the FPGA software is mainly program software which is realized by FPGA programming and is used for controlling a data buffer to realize data caching and controlling a file management controller to realize data storage of the mobile storage medium. And monitoring upper computer software, which is interface design software for realizing human-computer interaction based on Ethernet communication and including functions of data and waveform chart display, data issuing control, data operation and the like, such as Labview design software and MATLAB design software.
In addition to the technical details given in the above embodiments, the present invention should not be limited to the contents of high-speed data communication, data caching and storage developed based on FPGA, and the like, which are stated and disclosed in the drawings, and there may be other embodiments such as conversion of optical fiber serial communication line codes and change of serial data frame format, change of data caching mode, change of file management controller and storage medium, and any technical solutions adopting equivalent substitution or equivalent conversion form fall within the protection scope of the present patent claims.
Those not described in detail in this specification are within the skill of the art.
Claims (10)
1. A power electronic converter state data acquisition device is characterized in that: the device comprises a power electronic converter controller, a communication function board card and a monitoring upper computer; the power electronic converter controller and the communication function board card adopt high-speed optical fiber serial communication; the communication function board card and the monitoring upper computer adopt Ethernet communication; the high-speed optical fiber serial communication between the converter controller and the communication function board card adopts a user-defined high-speed serial protocol;
the power electronic converter controller encodes the running state data of the power electronic converter according to a user-defined serial communication protocol to form serial encoded data and sends the serial encoded data to the communication function board card; the communication function board automatically decodes the received serial coded data according to a user-defined serial communication protocol, converts the serial coded data into parallel data, and uploads the parallel data to a monitoring upper computer in real time according to an Ethernet communication protocol;
the monitoring upper computer sends control data to the communication function board card; the communication function board card converts received control data into parallel data according to an Ethernet communication protocol, encodes the parallel data according to a user-defined serial communication protocol to generate serial encoding data, and transmits the serial encoding data to the power electronic converter controller; the power electronic converter controller decodes and receives serial coded data according to a self-defined high-speed serial protocol, converts the serial coded data into control data, and executes corresponding operation according to the control data.
2. A power electronic converter status data collection device according to claim 1, wherein: the communication function board card is provided with a data buffer, a file management controller and a mobile storage medium; the communication function board card is used for converting the received state data from the power electronic converter controller or the control data from the monitoring upper computer into parallel data and then caching the parallel data into a data buffer; after the storage space of the data buffer is used up, a file management controller on the communication function board card executes the mobile medium data storage operation; the mobile medium data storage operation means that the file management controller stores all data in the data buffer into the mobile storage medium in sequence and generates a corresponding data file in the mobile storage medium.
3. A power electronic converter status data collection device according to claim 1, wherein: and the monitoring upper computer issues control data through a human-computer interaction interface and displays the running state of the power electronic converter.
4. A power electronic converter status data collection device according to claim 1, wherein: a high-speed serial communication mode based on an optical fiber link is adopted between the power electronic converter controller and the communication function board card, and a Manchester code is selected as a line code of the high-speed optical fiber serial communication; the power electronic converter controller or the communication function board card is used as a sending end, and parallel data to be sent are coded into serial coded data bit by bit according to a self-defined serial communication protocol and a coding rule of a Manchester code; the parallel data to be transmitted are state data or control data reflecting the operation of the power electronic converter in the power electronic converter controller.
5. A power electronic converter state data acquisition device according to claim 4, characterized in that: the serial encoded data includes a synchronous decoding clock; a power electronic converter controller or a communication function board card is used as a receiving end and is provided with a clock data recovery module; after receiving the serial coded data, a receiving end firstly recovers a synchronous decoding clock from the serial coded data by using a clock data recovery module, and then samples the serial coded data by using the recovered synchronous decoding clock to obtain non-coded serial data; and decoding according to the self-defined serial communication protocol, and restoring the non-coded serial data into the originally sent parallel data.
6. A power electronic converter state data acquisition device according to claim 4, characterized in that: the method comprises the steps that a sending end encodes parallel data to be sent according to a user-defined serial communication protocol and a Manchester code encoding format into serial encoding data, packages the serial encoding data into a serial data frame, and sends the serial data frame according to an agreed frequency;
the serial data frame format comprises a starting frame head, a plurality of serial coding data, 1 serial coding check data and an ending frame tail; the starting frame header is a high level with more than 2 bit numbers, and the inherent characteristics of the starting frame header can not appear in the serial coding data so as to represent the start of a frame of serial coding data and serve as a unique identifier for a receiving end to identify a serial data frame; the frame head is started and then the serial coding data is next, and the serial coding data is serial coding data bit stream converted from the parallel data to be transmitted according to the coding format of the Manchester code; after the serial coding check data is connected with the last serial coding data, the coding mode still adopts the coding format of Manchester code coding; the end frame is connected to the end of the serial coding check data in a tail mode, is used for representing the end of one frame of serial coding data and is a low level with more than 2 bit numbers.
7. A power electronic converter state data acquisition device according to claim 6, characterized in that: the serial coding check data is generated by calculating all parallel data to be sent corresponding to one frame of serial coding data by adopting a CRC (cyclic redundancy check) algorithm; after the receiving end decodes and receives a frame of serial encoding data, all parallel data except the check data corresponding to the serial encoding data in the serial data frame are calculated by adopting the same CRC (cyclic redundancy check) algorithm to generate a new check value, the new check value is compared with the serial encoding check data in the frame of serial encoding data received by decoding, and if the new check value is equal to the serial encoding check data, the receiving end judges that the frame of serial encoding data is correctly encoded and decoded and transmitted and continues to execute subsequent decoding operation; if the new check value is not equal to the serial encoding check data, the receiving end judges that the frame of serial encoding data is encoded and decoded and has transmission errors, and the receiving end requests the sending end to resend the serial data frame.
8. A power electronic converter state data acquisition device according to claim 6, characterized in that: the transmitting end is provided with an optical fiber transmitting port, and the receiving end is provided with an optical fiber receiving port; the method comprises the steps that a sending end converts a serial data frame to be sent into a serial optical signal from a serial electric signal through an optical fiber sending port, and sends the serial optical signal to an optical fiber link for connecting the sending end and a receiving end bit by bit; the receiving end converts the received serial data frame from a serial optical signal into a serial electric signal through the optical fiber receiving end.
9. A power electronic converter status data collection device according to claim 2, wherein: the communication function board card is provided with an FPGA timing and logic control module and an Ethernet controller; the self-defined high-speed serial communication protocol is developed by adopting an FPGA; the Ethernet communication is developed by adopting an FPGA, and a TCP or UDP protocol is adopted; the FPGA timing and logic control module decodes the serial coded data to obtain parallel data based on a synchronous decoding clock obtained by clock data recovery, and sends the parallel data to the Ethernet controller; under the control of the FPGA data sending time sequence, the Ethernet controller transmits the parallel data words to a monitoring upper computer in real time through an Ethernet interface according to a TCP protocol or a UDP protocol; the Ethernet controller receives control data from a monitoring upper computer through an Ethernet interface under the control of the FPGA data receiving time sequence, converts the received control data into parallel data and sends the parallel data to the FPGA time sequence and logic control module; the FPGA timing and logic control module is further used for initializing the Ethernet controller so as to configure the working mode of the Ethernet controller.
10. A power electronic converter status data collection device according to claim 9, wherein: under the control of the FPGA data caching time sequence, the FPGA time sequence and logic control module caches the parallel data obtained by decoding into a data cache; under the control of an FPGA data storage time sequence, an operation file management controller executes the data storage operation of the mobile medium; after the communication function board card is powered on, the FPGA time sequence and logic control module executes one-time initialization on the file management controller so as to set the working mode of the file management controller and connect and operate the mobile storage medium.
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