CN201877891U - Circuit breaker online monitoring device based on quick message frame aggregation technology - Google Patents

Circuit breaker online monitoring device based on quick message frame aggregation technology Download PDF

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Publication number
CN201877891U
CN201877891U CN2010206554840U CN201020655484U CN201877891U CN 201877891 U CN201877891 U CN 201877891U CN 2010206554840 U CN2010206554840 U CN 2010206554840U CN 201020655484 U CN201020655484 U CN 201020655484U CN 201877891 U CN201877891 U CN 201877891U
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circuit
circuit breaker
frame aggregation
dsp
fpga
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Expired - Fee Related
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CN2010206554840U
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梅军
郑建勇
黄灿
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Southeast University
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Southeast University
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02B90/20—Smart grids as enabling technology in buildings sector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
    • Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses

Abstract

The utility model discloses a circuit breaker online monitoring device based on quick message frame aggregation technology. The device comprises a switch state monitoring loop, a conditioning circuit, a first A/D converting circuit, an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor)/ARM dual-core operating system, wherein the switch state monitoring loop is connected with the input end of the FPGA through the conditioning circuit and the A/D converting circuit sequentially; the output end of the FPGA is connected with the input end of the DSP/ARM dual-core operating system through a data bus address assembly; and the DSP/ARM dual-core operating system comprises an SDARM, a FLASH, a serial interface, a JTAG (Joint Test Action Group) debugging port, an optical fiber Ethernet port, an Ethernet port, a resetting watch dog, a second A/D converting circuit, a crystal oscillator and a power supply. The device is quick and reliable in data transmission speed, can meet the real-time requirement of message transmission, and reduces Ethernet protocol expense, message length and delay of message transmission.

Description

A kind of circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation
Technical field
The utility model relates to protecting electrical power system equipment, relates in particular to a kind of circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation.
Background technology
Circuit breaker is as realizing the important primary equipment of protection with controlled function in the electric power system, its reliable in action is directly connected to the safety and stablization of electric power system, will have serious consequences in case break down.Conventional substation adopts the off-line routine test that the circuit breaker running status is judged more, and there are shortcomings such as blindness is big, expense height in preventive trial and scheduled overhaul, and frequent operation and excessive dismounting can reduce the reliability of circuit breaker action.In recent years, along with the development of intelligent grid and digital transformer substation technology, a kind of intelligent breaker that integrates functions such as detection, control, communication is subjected to extensive concern and research.Intelligent breaker requires a switchgear except having the Based Intelligent Control function, also should have the real time on-line monitoring function, has represented electrical network digitlization, networking and intelligentized developing direction.
IEC 61850 " substation communication network and system " is that electric substation automation system is unified international standard in the present world wide; for the detection of circuit-breaker status amount has defined general OO transformer substation case (being called for short GOOSE) model, realize the information sharing of GOOSE message between intelligent electronic devices such as protection, observing and controlling, metering in the standard by serial communication network based on switching Ethernet.The important indicator of GOOSE message communication success depends on the real-time of message transmissions.For improving the real-time of data communication, IEC 61850 is divided into 7 priority (rapid message, middling speed message, low speed message, initial data message, file transfer message, time synchronized message and have the command message of access control) according to the urgency level of substation data demand with message.The GOOSE message belongs to rapid message, and specified transmission delay is limited to below the Millisecond.
The GOOSE message will be responsible for mechanical trip in the circuit breaker in the engineering, vibration signal, the divide-shut brake coil current, drop-out current, main circuit current, main circuit voltage, the temperature of electrically conducting contact position, state of insulation, the GIS gas density, the little water of SF6 gas, the transmission of numerous digital quantities such as opening and closing state monitoring and quantity of state, message length is long, real-time to message transmissions has certain influence, main at present by improving the data processing speed of ethernet processor, enlarge the transmission delay that peripheral techniques such as Ethernet switch bandwidth and reasonable disposition virtual lan reduce the GOOSE message, all fail fundamentally to improve the transmission speed of message.
Based on the techniques of frame aggregation of IEEE 802.11n standard is the method for the emerging in the world in recent years a kind of WLAN of raising handling capacity, is mainly used in the WLAN (wireless local area network) at present.Techniques of frame aggregation reduces protocol overhead by improving the physical layer and the MAC layer of message, reduces message length, can effectively improve the transmission rate of physical layer.In process bus, adopt the communication mode of multicast addressing in view of the GOOSE message, there are the characteristics of common purpose address in the multiframe message, utilize techniques of frame aggregation can effectively reduce the total length of multiframe message, reduce message in Ethernet switch the storage Forwarding Latency and the propagation delay in the light, improve the message transmissions real-time.
The utility model content
Goal of the invention: in order to overcome the deficiencies in the prior art, the utility model provides a kind of circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation, adopt dual core processor fast processing data, utilization techniques of frame aggregation compression GOOSE message, be a kind of primary cut-out on-Line Monitor Device with superpower real-time, its communication pattern and interoperability meet IEC 61850 standards.
Technical scheme: for achieving the above object, the technical solution adopted in the utility model is:
A kind of circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation, comprise the on off state monitoring circuit, modulate circuit, the one A/D change-over circuit, FPGA and DSP/ARM double-core operating system, described on off state monitoring circuit passes through modulate circuit successively, the A/D change-over circuit links to each other with the input of FPGA, the output of described FPGA links to each other with the input of DSP/ARM double-core operating system by the data/address bus address bus, and described DSP/ARM double-core operating system comprises SDARM, FLASH, serial line interface, the JTAG debug port, fiber optic Ethernet mouth (abbreviation optical fiber port), Ethernet interface, house dog resets, the 2nd A/D change-over circuit, crystal oscillator and power supply.
Wherein on off state detection loop comprises circuit breaker, and each detection loop that links to each other with circuit breaker, for example contact travel detection loop, vibration signal detection loop, switching winding current detection circuit, closing coil current detection circuit, contact temperature detect loop, drop-out current detection loop, contact action frequency detection loop, micro-water content detection loop, energy storage condition monitoring detection loop, control loop monitoring detection loop etc., and each detection loop difference is connected with an A/D change-over circuit with corresponding modulate circuit successively; The one A/D change-over circuit is responsible for the detection signal in respective detection loop is carried out the A/D conversion, to be implemented in the FPGA multiple signals is carried out synchronous acquisition; FPGA links to each other with DSP/ARM double-core operating system by the data/address bus address bus, and the system that the back that links to each other forms mainly carries out calculation process, GOOSE communication, expansion CAN communication, serial communication, Keyboard Control, LCD demonstration, remote control output etc. to each input variable; Serial ports is mainly debugged usefulness, the Debugging message and the output information of the hyper terminal display unit by main frame; JTAG debug port major function is the on-line debugging application program; The fiber optic Ethernet mouth mainly is to communicate with switch, and with the transmitting-receiving message, the number of fiber optic Ethernet mouth can be for more than one, when claimed apparatus is exported under the situation of signal more than a tunnel simultaneously by optical fiber; Because described device operation is embedded OS, various image files are bigger, and the speed of using serial line interface to download, copy can be slow, increases an Ethernet interface, can finish the high-speed traffic of Target Board and main frame; The 2nd A/D change-over circuit is mainly used in low-voltage circuit breaker information is carried out in-site collecting.
Said apparatus is passed to SDRAM with own inner program by bus at the back FLASH that powers on, and SDRAM restarts the program of gained and drives ARM/DSP work then.
DSP/ARM double-core operating system can adopt the TMS320DM64XX processor, described TMS320DM64XX processor has powerful data-handling capacity, DSP operating system and ARM operating system are responsible for the processing and the network service of monitored data respectively, can solve the numerous and jumbled problem of status monitoring data, have stronger real-time.
Described serial line interface adopts MAX203, and described MAX203 two-way serial ports RS232 wherein drives port as sending, and described MAX203 two-way serial ports RS232 in addition wherein drives port as receiving; The maximum current that described MAX203 can bear is 15mA, and operating voltage is+5V.
Describedly carry Ethernet MAC layer (be called for short MAC layer) controller based on the DSP/ARM double-core operating system in the circuit breaker on-Line Monitor Device of rapid message techniques of frame aggregation, the MAC layer is positioned between logic link layer (being called for short LLC) and the physical layer (being called for short PHY), mainly form, finish encapsulation, opening, transmission and the receiving function of data by data encapsulation and two modules of media interviews management.ARM adopts the working method of DMA or FIFO, connects PHY twisted-pair feeder or fiber optical transceiver by Media Independent Interface (being called for short MII).
The PHY layer of described circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation adopts LXT971A, finishes physical codes sublayer and the physical codes extra play stipulated in the IEE802.3 standard, and all functions of physical medium independent stratum; LXT971A directly supports the 10/100Mbit/s twisted pair applications, also supports the 100Mbit/s optical fiber interface.
Described circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation adopts techniques of frame aggregation to the GOOSE rapid message, and the GOOSE identical to a plurality of destination addresses carries out polymerization, makes its public MAC layer destination address, to reduce message length.
Described circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation also comprises network card chip, when system needs the multichannel ethernet communication, need extend out ethernet control chip, network card chip is connected with described device by ethernet control chip, make the GOOSE message in the system pass through Optical Fiber Transmission, rather than pass through cable transmission.Ethernet control chip can be LAN9215, and LAN9215 is 16 10/100Mbit/s ethernet control chips, outside MII interface, and its main feature is: integrated ethernet mac layer and PHY layer; Meet the IEEE802.3/802.3u standard fully; The support of 10base-T and 100BASE-TX; Support the full and half duplex pattern; Automatic 32 are CRC generation and verification; The full duplex flow control; Loopback mode.
Beneficial effect: the circuit breaker on-Line Monitor Device that the utility model provides based on the rapid message techniques of frame aggregation, its communication system is based on the IE61850 standard traffic, monitored data are transmitted with the form of GOOSE message, and replace long cable section of ingoing line transfer of data, fast and reliable by optical fiber; And the GOOSE message belongs to rapid message, and transmission delay is fixed on Millisecond, and transfer of data is in the special occasion, i.e. when breaker tripping and closing order and mode bit changed, this device can the fine requirement of satisfying the message transmissions real-time.Described device adopts techniques of frame aggregation, in the communication process of GOOSE message multicast addressing, the multiframe message convergence that destination address is identical is a frame, reduces the Ethernet protocol expense, reduce message length, fundamentally shortened the transmission delay of GOOSE message in Ethernet.Simultaneously, A/D module that described device is inner integrated is not only monitored digital information, all right monitor analogue quantity information, realize in-site collecting, monitoring and the control of circuit-breaker status amount, the drainage pattern of compatible conventional transformer station and digital transformer substation, engineering adaptability is strong.
Description of drawings
Fig. 1 is the structural representation of the utility model device;
Fig. 2 is the data schematic diagram of frame aggregation;
Fig. 3 is the watchdog reset circuit schematic diagram;
Fig. 4 is the circuit theory diagrams of serial line interface;
Fig. 5 is the physical layer circuit schematic diagram;
Fig. 6 is an ethernet control chip connecting circuit schematic diagram;
Fig. 7 is the telecommunication circuit schematic diagram.
Embodiment
Below in conjunction with accompanying drawing the utility model is done further explanation.
Be illustrated in figure 1 as a kind of structural representation of the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation, comprise the on off state monitoring circuit, modulate circuit, the one A/D change-over circuit, FPGA and DSP/ARM double-core operating system, described on off state monitoring circuit passes through modulate circuit successively, the A/D change-over circuit links to each other with the input of FPGA, the output of described FPGA links to each other with the input of DSP/ARM double-core operating system by the data/address bus address bus, and described DSP/ARM double-core operating system comprises SDARM, FLASH, serial line interface, the JTAG debug port, the fiber optic Ethernet mouth, Ethernet interface, house dog resets, the 2nd A/D change-over circuit, crystal oscillator and power supply.
On off state detects the loop and comprises circuit breaker, and each detection loop that links to each other with circuit breaker, for example contact travel detection loop, vibration signal detection loop, switching winding current detection circuit, closing coil current detection circuit, contact temperature detect loop, drop-out current detection loop, contact action frequency detection loop, micro-water content detection loop, energy storage condition monitoring detection loop, control loop monitoring detection loop etc., and each detection loop difference is connected with an A/D change-over circuit with corresponding modulate circuit successively.
FPGA links to each other with DSP/ARM double-core operating system by the data/address bus address bus, and the system that the back that links to each other forms mainly carries out calculation process, GOOSE communication, expansion CAN communication, serial communication, Keyboard Control, LCD demonstration, remote control output etc. to each input variable.
For guaranteeing that the GOOSE message transmits fast, the GOOSE message transmissions only adopts application layer, presentation layer and the data link layer in the ICP/IP protocol.The GOOSE message generates protocol Data Unit PDU to application program in application layer by abstract syntax notation one ASN.1, and the Basic Encoding Rules BER (Basic Encoding Rules) that presentation layer is followed ASN.1 transmits on the Ethernet being adapted at the PDU coding.Mac header in the GOOSE message frame form comprises source address, destination address and their length of frame.When a plurality of PDU when same receiving terminal transmits, destination address is identical, a plurality of PDU can a shared MAC head, simplified the structure of frame, removed interFrameGap between the protocol frame and competition time in the past, thereby improved the throughput of MAC layer, the data schematic diagram of frame aggregation as shown in Figure 2.Only needing after the polymerization of these map of services cell S DU subframe to send a mac frame header, significantly reduced the nose heave extra load of bringing again of a plurality of mac frames. process realizes in ARM really.
Accompanying drawing 3 is depicted as watchdog reset circuit schematic diagram in the described device, comprises manual reset circuit S700SWITCH, watchdog chip MAX6369, chip MAX6390 resets.For the uncertain consequence that prevents system in case of system halt or descend and to occur because of supply voltage.Watchdog chip MAX6369 and manual reset circuit parallel connection insert the chip that resets, to improve the stability of system.The effect of this circuit comprises: the hand-reset button; The electrification reset pulse makes system run on a state as can be known; During power failure, promptly fall to+1.58V and when following when+3.3V main power voltage, produce reset pulse, make CPU be in reset mode, do not carry out any instruction, recover normal until supply voltage; When overflowing, WatchDog Timer resets; The software reset.
According to the specific requirement of described device, the WatchDog Timer time of MAX6369 chip can be adjusted in 3s, promptly SET2, SET0 connect high level, SET1 ground connection.Refresh time can be set by pin connection difference, promptly in setting-up time, if do not refresh Watch Dog, then produces reset pulse, can effectively prevent program endless loop or deadlock.
Accompanying drawing 4 is depicted as the circuit theory diagrams of serial line interface in the described device, that it adopts is serial communication chip MAX203, and the two-way serial ports RS232 among the chip MAX203 sends and drives, and two-way serial ports RS232 receives and drives in addition, its operating voltage is+5V that the maximum current that can bear is 15Ma.Described device can only send, receive driving with riches all the way when doing debugging and use, the function expansion is done on another road fully, its use be that master chip is debugged dedicated pin.
Band Ethernet media interviews MAC layer controller in the master chip, the MAC layer mainly is made up of data encapsulation and two modules of media interviews management between LLC layer and HPY layer, finishes encapsulation, opening, transmission and the receiving function of data; It adopts the working method of DMA or FIFO, connects PHY layer twisted-pair feeder or fiber optical transceiver by MII.
Accompanying drawing 5 is depicted as the structural representation that described device selects for use LXT971A to use as physical layer, LXT971A is the network communication interface chip of Intel Company, can finish physical codes sublayer and the physical codes extra play stipulated in the IEE802.3 standard, also can finish all functions of physical medium independent stratum.Directly support the 10/100Mbit/s twisted pair applications, also support the 100Mbit/s optical fiber interface.
Above-mentioned LXT971A can be arranged to multiple twin communication and optical fiber communication dual mode.Multiple twin and optical fiber cable access way can be selected by mode conversion switch, and what select when mode switch is got to (being that SD/TP connects height) on the power supply is the optical fiber communication pattern, and what select when mode switch ground connection (being SD/TP ground connection) is the twisted-pair feeder communication mode.Because network signal sends signal different with encoding context with MAC layer and HPY layer at level, so need between physics socket and key-course, to increase isolating transformer and physical interface circuit physical layer, physical layer is encoded to the data that send, and transformer carries out ambipolar synthetic and level translation to the signal on the Ethernet.In this device, chip interface MDDIS ground connection, expression can be carried out read-write operation to MDIO.When operate as normal, can control word be write in the control register by MDIO, change the operating state of LXT971A, transfer of data and MDC are synchronous.The MDC clock is provided by ARM output.
Described device is when system needs the multichannel ethernet communication, need to use ethernet control chip, accompanying drawing 6 is depicted as the circuit connection diagram of ethernet control chip LAN9215, the master chip of described device is connected with network card chip by LAN9215, and the GOOSE message in the system is transmitted by optical fiber.LAN9215 is 16 10/100Mbit/s ethernet controllers, outside MII interface.Its main feature: integrated ethernet mac and PHY; Meet IEEE 802.3/802.3u standard fully; The support of 10base-T and 100BASE-TX; Support the full and half duplex pattern; Automatic 32 CRC generate and verification; The full duplex flow control; Loopback mode.
As shown in Figure 7, the communication mode of FPGA and DSP/ARM has two kinds, parallel communications and serial communication, consider breaker signal having relatively high expectations for real-time, the speed of parallel communications is about 8 times of serial communication, and the information communication amount of quantity of state is bigger between DSP and the FPGA, so this device adopts the parallel communications between DSP and the FPGA, and the channel arrangement control signal of DSP and FPGA is also passed through parallel communications, rely on some handshake and sheet the choosing and interrupt signal control: when data among the FPGA deposit according to the order of sequence finish after, send quick interrupt signal to DSP, DSP has no progeny in receiving, and jumps to the task of reading data the FPGA from other tasks immediately.Handshake mainly realizes DSP and FPGA initialization, the quantity of state communication when writing operation such as configuration information.
The above only is a preferred implementation of the present utility model; be noted that for those skilled in the art; under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.

Claims (6)

1. circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation, it is characterized in that: described device comprises the on off state monitoring circuit, modulate circuit, detection signal from the on off state monitoring circuit is carried out the A/D conversion to be implemented in an A/D change-over circuit of realizing the multiple signals synchronous acquisition in the FPGA, FPGA with input variable is carried out calculation process and carries out the DSP/ARM double-core operating system that GOOSE communicates by letter, described on off state monitoring circuit passes through modulate circuit successively, the A/D change-over circuit links to each other with the input of FPGA, the output of described FPGA links to each other with the input of DSP/ARM double-core operating system by the data/address bus address bus, and described DSP/ARM double-core operating system comprises SDARM, FLASH, serial line interface, the JTAG debug port of on-line debugging application program, communicate and receive and dispatch the fiber optic Ethernet mouth of message with switch, Ethernet interface, house dog resets, be used for low-voltage circuit breaker information is carried out the 2nd A/D change-over circuit of in-site collecting, crystal oscillator and power supply.
2. the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation according to claim 1, it is characterized in that: described serial line interface adopts MAX203, described MAX203 two-way serial ports RS232 wherein drives port as sending, and described MAX203 two-way serial ports RS232 in addition wherein drives port as receiving.
3. the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation according to claim 1 is characterized in that: described DSP/ARM double-core operating system carries Ethernet MAC layer controller.
4. the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation according to claim 1 is characterized in that: the physical layer of described device adopts LXT971A.
5. the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation according to claim 1 is characterized in that: described device carries out frame aggregation to the identical GOOSE communication information of above destination address to be handled.
6. the circuit breaker on-Line Monitor Device based on the rapid message techniques of frame aggregation according to claim 1, it is characterized in that: described device also comprises network card chip, described network card chip is connected with described device by ethernet control chip, and described ethernet control chip is LAN9215.
CN2010206554840U 2010-12-13 2010-12-13 Circuit breaker online monitoring device based on quick message frame aggregation technology Expired - Fee Related CN201877891U (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102014027A (en) * 2010-12-13 2011-04-13 东南大学 On-line breaker monitoring device based on quick massage frame aggregation technology
CN103377081A (en) * 2012-04-27 2013-10-30 沈阳高精数控技术有限公司 Implementation method for interrupt mechanism between embedded numerical control system dual-core chip and peripheral
CN108183398A (en) * 2018-01-23 2018-06-19 淮海工学院 A kind of embedded intelligence switch cabinet system
US10141127B2 (en) 2015-12-16 2018-11-27 Abb Schweiz Ag High-speed communications coupling for use in a circuit breaker assembly

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102014027A (en) * 2010-12-13 2011-04-13 东南大学 On-line breaker monitoring device based on quick massage frame aggregation technology
CN102014027B (en) * 2010-12-13 2013-01-16 东南大学 On-line breaker monitoring device based on quick massage frame aggregation technology
CN103377081A (en) * 2012-04-27 2013-10-30 沈阳高精数控技术有限公司 Implementation method for interrupt mechanism between embedded numerical control system dual-core chip and peripheral
CN103377081B (en) * 2012-04-27 2017-02-08 沈阳高精数控智能技术股份有限公司 Implementation method for interrupt mechanism between embedded numerical control system dual-core chip and peripheral
US10141127B2 (en) 2015-12-16 2018-11-27 Abb Schweiz Ag High-speed communications coupling for use in a circuit breaker assembly
CN108183398A (en) * 2018-01-23 2018-06-19 淮海工学院 A kind of embedded intelligence switch cabinet system

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