CN114222913B - Wafer appearance inspection device and method - Google Patents
Wafer appearance inspection device and method Download PDFInfo
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- CN114222913B CN114222913B CN202080057392.9A CN202080057392A CN114222913B CN 114222913 B CN114222913 B CN 114222913B CN 202080057392 A CN202080057392 A CN 202080057392A CN 114222913 B CN114222913 B CN 114222913B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/94—Investigating contamination, e.g. dust
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
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- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
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- G06T7/0004—Industrial image inspection
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
- G01N2021/8854—Grading and classifying of flaws
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- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
- G01N2021/8887—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges based on image processing techniques
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- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
- G01N2021/95615—Inspecting patterns on the surface of objects using a comparative method with stored comparision signal
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Abstract
Provided are a wafer appearance inspection device and method, which can perform inspection corresponding to a complete chip on an inspection area of a wafer even if an incomplete chip is formed on the wafer over the inspection area and a non-inspection area, and obtain a desired inspection result on the entire inspection area of the wafer. Specifically, in a wafer appearance inspection apparatus and method for inspecting a device chip by capturing an inspection target portion of a repetitive appearance pattern of the device chip formed on a wafer and comparing the inspection target portion with a reference image, a replacement process is performed for replacing a luminance value of a pixel corresponding to a non-inspection area among pixels constituting the image with a luminance value of the reference image based on positional information on the wafer and a chip layout on which the image is captured, with respect to an image obtained by capturing an incomplete chip formed throughout the inspection area and the non-inspection area, thereby generating an inspection image, and comparing the generated inspection image with the reference image, thereby inspecting the inspection target portion.
Description
Technical Field
The present invention relates to a wafer appearance inspection apparatus and method as follows: an inspection image obtained by photographing a repetitive appearance pattern of a device chip formed on a wafer is compared with a reference image, thereby performing inspection of the device chip.
Background
The semiconductor device is singulated into individual chip components after forming a large number of semiconductor device circuits (i.e., repeating appearance patterns of device chips) on 1 semiconductor wafer, and the chip components are packaged, shipped as electronic components in a single unit, or assembled into electronic products.
Before the individual chip components are singulated, an inspection image obtained by photographing a repetitive appearance pattern of a device chip formed on a wafer is compared with a reference image to perform inspection (for example, patent document 1), or an electrical inspection is performed using a probe (for example, patent document 2).
The device chips formed in a repetitive pattern in a vertically and horizontally matrix on the wafer have "complete chips" which are commercialized by dicing, and "incomplete chips" which are not commercialized due to a partial shortage of the pattern. Then, the appearance of the whole chip is photographed and compared with a reference image to determine whether the chip is good or bad (so-called inspection). On the other hand, in order to shorten the processing time, inspection of an incomplete chip is omitted (for example, patent document 3).
Prior art literature
Patent literature
Patent document 1 Japanese patent laid-open No. 2007-155610
Patent document 2 Japanese patent laid-open No. 2-290036
Patent document 3 Japanese patent laid-open No. 4-276642
Disclosure of Invention
Problems to be solved by the invention
However, if the appearance inspection is performed on the completed chip and on the other hand, the inspection of the incomplete chip is omitted, the wafer is pulled into the subsequent process even if a flaw, foreign matter, or the like is attached to the incomplete chip.
Therefore, if there is probe inspection later, flaws, foreign matters, and the like on the incomplete chip come into contact with probes (probes), and there are many problems such as breakage of the probes, wafer cracks/chipping, and the like.
On the other hand, according to the conventional visual inspection method, when a part of an inspection image obtained by photographing an incomplete chip includes a notch and is compared with a reference image, the part is determined to be abnormal and becomes a factor of suspected defect detection. Further, the processing time increases due to the suspected defect detection.
Accordingly, the present invention has been made in view of the above-described problems, and an object thereof is to provide a wafer appearance inspection apparatus and method as follows: even if incomplete chips are formed on the wafer over the inspection area and the non-inspection area, inspection corresponding to the complete chips can be performed on the inspection area of the wafer, a desired inspection result can be obtained on the entire inspection area of the wafer, and an increase in processing time can be prevented.
Means for solving the problems
In order to solve the above problems, one aspect of the present invention provides a wafer visual inspection apparatus for inspecting a device chip formed on a wafer by capturing an inspection target portion of a repetitive visual pattern of the device chip and comparing the inspection target portion with a reference image,
The wafer appearance inspection device comprises:
A wafer holding section for holding a wafer;
an imaging unit that images an image including a part to be inspected;
a relative movement unit that moves the wafer holding unit and the imaging unit relative to each other;
a reference image registration unit that registers a reference image;
A chip layout registration unit that registers a chip layout defining an inspection region and a non-inspection region of a wafer corresponding to a reference posture and a reference position of the wafer; and
An image processing unit that processes the image captured by the capturing unit,
The image processing unit includes:
A dynamic replacement processing unit that generates an inspection image by performing a replacement process of replacing a luminance value of a pixel corresponding to a non-inspection region among pixels constituting an image of an image obtained by capturing an image of an inspection target portion of an incomplete chip formed over the inspection region and the non-inspection region with a luminance value of a reference image based on positional information on a wafer on which the image was captured and a chip layout; and
And a comparison inspection unit that compares the inspection image generated by the dynamic displacement processing unit with a reference image to inspect the inspection target portion.
Another aspect of the present invention provides a wafer appearance inspection method for inspecting a device chip by photographing an inspection target portion of a repetitive appearance pattern of the device chip formed on a wafer and comparing the inspection target portion with a reference image,
The wafer appearance inspection method comprises the following steps:
Registering a reference image in advance;
registering a chip layout in advance, the chip layout defining an inspection area and a non-inspection area of a wafer corresponding to a reference posture and a reference position of the wafer;
Relatively moving the wafer and the photographing unit and photographing an image including the inspection object part; and
The image is processed and the image is processed,
And, the method comprises the following steps:
Performing a replacement process of replacing a luminance value of a pixel corresponding to a non-inspection region among pixels constituting an image of an image obtained by capturing an image of an incomplete chip formed over the inspection region and the non-inspection region with a luminance value of a reference image based on positional information on a wafer on which the image was captured and a chip layout, thereby generating an inspection image; and
The inspection image is compared with the reference image, and the inspection target portion is inspected.
According to the wafer appearance inspection apparatus and method, even if the outer edge shape is different for each imaging position, the incomplete chip is dynamically replaced according to the imaging position to generate an inspection image, and the inspection image is compared with the reference image to perform a desired inspection.
ADVANTAGEOUS EFFECTS OF INVENTION
Even if an incomplete chip is formed on a wafer so as to cross an inspection area and a non-inspection area, the inspection corresponding to the complete chip can be performed in the case of the inspection area of the wafer, a desired inspection result can be obtained for the entire inspection area of the wafer, and an increase in processing time can be prevented.
Drawings
Fig. 1 is a schematic diagram showing an overall configuration of an example of an embodiment for embodying the present invention.
Fig. 2 is a conceptual diagram illustrating a situation of photographing in an example of an embodiment of the present invention.
Fig. 3 is a plan view showing a positional relationship of each device chip C, which is an example of an embodiment of the present invention.
Fig. 4 is an image diagram showing an image Ps, a reference image Pf, an inspection image Pk, and a video of a difference between the inspection image Pk and the reference image Pf, which is an example of an embodiment embodying the present invention.
Fig. 5 is an image diagram showing an example of an image Ps, a reference image Pf, luminance values of pixels of an inspection image Pk, and a difference between luminance values of the inspection image Pk and the reference image Pf, which embody the embodiment of the present invention.
Fig. 6 is a flowchart showing an example of a mode for embodying the present invention.
Detailed Description
Hereinafter, modes for carrying out the present invention will be described with reference to the drawings. In the following description, the 3-axis of the orthogonal coordinate system is X, Y, Z, the horizontal direction is referred to as the X-direction and the Y-direction, and the direction perpendicular to the XY plane (i.e., the gravity direction) is referred to as the Z-direction. In the Z direction, the direction opposite to the gravity is expressed as up, and the direction in which the gravity acts is expressed as down. The direction in which the rotation is performed around the Z direction as the central axis is defined as the θ direction.
Fig. 1 is a schematic diagram showing an overall configuration of an example of an embodiment for embodying the present invention. Fig. 1 schematically shows the respective parts constituting the wafer visual inspection apparatus 1 of the present invention.
The wafer appearance inspection device 1 is as follows: the inspection target portion of the repetitive appearance pattern of the device chip C formed on the wafer W is photographed and compared with the reference image Pf, thereby performing the inspection of the device chip C.
Specifically, the wafer appearance inspection apparatus 1 sequentially changes the imaging location and images the inspection target portion, processes the imaged image Ps to generate an inspection image Pk, and compares the inspection image Pk with the reference image Pf to perform a desired inspection such as whether or not there is no short circuit or disconnection in the circuit pattern of the device chip C, and whether or not there is no foreign matter or flaw in the circuit pattern over the entire surface of the wafer W.
The wafer appearance inspection device 1 includes a wafer holding unit 2, an imaging unit 3, a relative movement unit 4, a chip layout registration unit 5, a reference image registration unit 6, an image processing unit 7, a control unit CN, and the like.
The wafer holding section 2 holds a wafer W.
Specifically, the wafer holding section 2 holds and supports the wafer W in a horizontal state from the lower surface side of the wafer W. More specifically, the wafer holding section 2 has a horizontal mounting table 20 on its upper surface.
The stage 20 is provided with grooves and holes at a portion contacting the wafer W, and these grooves and holes are connected to a negative pressure generating means such as a vacuum pump via a switching valve or the like. The wafer holding section 2 can hold or release the wafer W by switching the grooves and holes to a negative pressure state or an atmospheric release state.
The imaging unit 3 images an image Ps including the inspection target region.
Here, the image Ps including the inspection target portion is an image captured so as to include a part or all of the repeated appearance pattern of the device chip C to be inspected, and is an image obtained by dividing the inspection target portion of each device chip C and capturing a wide range (capturing area F) of the inspection target portion including 1 or more device chips C.
Specifically, the arrangement (number, pitch, etc.) of the device chips C, the required inspection accuracy, etc. are different for each inspection item, and therefore, the size, position interval, etc. of the range (i.e., the imaging region) imaged by the imaging unit 3 are registered so as to be suitable for each inspection item.
More specifically, the photographing section 3 has a lens barrel 30, an illumination section 31, a half mirror 32, a plurality of objective lenses 33a, 33b, a rotator mechanism 34, a camera 35, and the like.
The lens barrel 30 fixes the illumination section 31, the half mirror 32, the objective lenses 33a, 33b, the rotator mechanism 34, the camera 35, and the like in a predetermined posture, and guides illumination light or observation light. The lens barrel 30 is attached to the device frame 1f via a coupling fitting or the like (not shown).
The illumination unit 31 emits illumination light L1 required for shooting. Specifically, the illumination unit 31 may be a laser diode, a metal halide lamp, a xenon lamp, or an LED illumination.
The half mirror 32 reflects the illumination light L1 emitted from the illumination unit 31 to irradiate the wafer W side, and passes the light (reflected light, scattered light) L2 incident from the wafer W side to the camera 35 side.
The objective lenses 33a and 33b form images of the imaging region on the workpiece W on the imaging element 36 of the camera 35 at respective different predetermined observation magnifications.
The rotator mechanism 34 switches which objective lens 33a, 33b is used. Specifically, the rotator mechanism 34 is controlled manually or by an external signal, and is rotated by a predetermined angle and is stationary each time.
The camera 35 captures an imaging region F on the workpiece W, and acquires an image Ps imaged on the imaging element 36. The acquired image Ps is output to the outside as a video signal or video data, and is processed by the image processing unit 7 to generate an inspection image Pk.
The relative movement section 4 moves the wafer holding section 2 and the imaging section 3 relative to each other.
Specifically, the relative movement unit 4 includes an X-axis slider 41, a Y-axis slider 42, and a rotation mechanism 43.
The X-axis slider 41 is mounted on the apparatus frame 1f such that the Y-axis slider 42 moves at an arbitrary speed in the X-direction and is stationary at an arbitrary position. Specifically, the X-axis slider is composed of 1 pair of rails extending in the X direction, a slider portion that moves on the rails, and a slider driving portion that moves and stops the slider portion. The slider driving unit may be configured by a combination of a servo motor or a pulse motor which is rotated and stopped by a signal from the control unit CN, and a ball screw mechanism, a linear motor mechanism, and the like. Further, the X-axis slider 41 has an encoder for detecting the current position and movement amount of the slider portion. Further, the encoder may be exemplified by an encoder in which fine irregularities are engraved at predetermined pitches on a linear member called a linear scale, a rotary encoder that detects a rotation angle of a motor that rotates a ball screw, and the like.
The Y-axis slider 42 moves the rotation mechanism 43 at an arbitrary speed in the Y-direction and is stationary at an arbitrary position based on a control signal output from the control unit CN. Specifically, the Y-axis slider is composed of 1 pair of rails extending in the Y direction, a slider portion that moves on the rails, and a slider driving portion that moves and stops the slider portion. The slider driving unit may be configured by a combination of a servo motor or a pulse motor which is rotated and stopped by a signal from the control unit CN, and a ball screw mechanism, a linear motor mechanism, and the like. Further, the Y-axis slider 42 has an encoder for detecting the current position and movement amount of the slider portion. Further, the encoder may be exemplified by an encoder in which fine irregularities are engraved at predetermined pitches on a linear member called a linear scale, a rotary encoder that detects a rotation angle of a motor that rotates a ball screw, and the like.
The rotation mechanism 43 rotates the stage 20 in the θ direction at an arbitrary speed and stands still at an arbitrary angle. Specifically, the rotation mechanism 43 can be exemplified by a rotation mechanism in which a direct drive motor or the like rotates at an arbitrary angle or is stationary at an arbitrary angle in response to a signal control from an external device. The mounting table 20 of the wafer holding section 2 is attached to a member on the rotating side of the rotating mechanism 43.
The relative movement unit 4 is configured as described above, and thus, when the wafer W to be inspected is held, the wafer W can be moved independently or in combination in the xyθ direction relative to the imaging unit 3 at a predetermined speed or angle, and can be stationary at an arbitrary position/angle.
Fig. 2 is a conceptual diagram illustrating a situation of photographing in an example of an embodiment of the present invention.
The following conditions are shown in fig. 2: the camera 35 of the imaging unit 3 is moved relative to the wafer W in the direction indicated by the arrow Vs, and the imaging positions of the plurality of device chips C (2, 2) to C (5, 2) arranged at intervals on the wafer W are sequentially changed to image the inspection target portion. Further, the figure shows a state in which the imaging region F of the inspection target portion including the device chip C (4, 2) is imaged by the camera 35 at the present time.
Fig. 3 is a plan view showing a positional relationship of each device chip C, which is an example of an embodiment of the present invention. Fig. 3 shows an arrangement image of a repetitive appearance pattern of a device chip C formed on a wafer W of a certain inspection type, and illustrates a situation in which a complete chip Cn formed in an inspection area Ri of the wafer W and an incomplete chip Cb formed throughout the inspection area Ri and a non-inspection area Rn are arranged.
The chip layout registration unit 5 registers a chip layout defining positional information of the inspection region Ri and the non-inspection region Rn of the wafer corresponding to the reference posture and the reference position of the wafer W and arrangement information of the device chips C.
In the chip layout, the state in which the notch Wk of the wafer W is oriented directly downward is set as a reference posture, the center of the wafer W in this posture is set as a reference position (also referred to as an origin) in the XY direction, and positions (i.e., positional information) at which the outer edge of the inspection region Ri (i.e., the boundary between the non-inspection region Rn) is located at a radius of several millimeters, and the vertical and horizontal arrangement, pitch, offset information, and the like (i.e., arrangement information) of the repetitive appearance pattern of the device chip C are defined.
Specifically, the chip layout registration unit 5 registers data defining a chip layout for each inspection item.
The reference image registration unit 6 registers the reference image Pf.
In addition, the reference image Pf represents a reference in which the repetitive appearance pattern of the device chip C formed on the wafer W is in a normal state. Specifically, the reference image Pf becomes the following reference: the difference or variance value of the luminance value is determined to be normal for each pixel or pixel group when the difference or variance value is within a predetermined range, and is determined to be abnormal when the difference or variance value is outside the predetermined range, compared with the captured inspection image Pk. More specifically, the reference image Pf may be exemplified by 1 image representing a good image selected in advance, an image obtained by averaging a plurality of good images selected in advance, an image generated by a good learning method, or the like.
Specifically, the reference image registration unit 6 registers data of the reference image Pf for each inspection item.
Fig. 4 is an image diagram showing an image Ps, a reference image Pf, an inspection image Pk, and a video of a difference between the inspection image Pk and the reference image Pf, which is an example of an embodiment embodying the present invention.
Fig. 4 (a) illustrates a video of an image Ps obtained by capturing an incomplete chip Cb, and the image Ps includes a circuit pattern and a defect X of a detection target.
Fig. 4 (b) illustrates a video of the reference image Pf.
Fig. 4 (c) illustrates a video of the inspection image Pk.
Fig. 4 (d) illustrates a difference between the inspection image Pk and the reference image Pf.
Further, examples are shown in which each of the images Ps, pf, pk is formed of pixels in a matrix of vertically and horizontally 7×7. Further, as the defect X, a foreign substance adhering to the circuit pattern is illustrated.
Fig. 5 is an image diagram showing an image Ps, a reference image Pf, luminance values of pixels of an inspection image Pk, and a difference between luminance values of the inspection image Pk and the reference image Pf, which are examples of embodiments embodying the present invention. The images (a) to (d) in fig. 4 correspond to the positional relationship of the luminance values of the pixels shown in (a) to (d) in fig. 5, respectively.
Fig. 5 (a) illustrates an image of the luminance value of each pixel of the image Ps (including the circuit pattern and the defect X of the detection target) obtained by capturing the incomplete chip Cb.
Fig. 5 (b) illustrates a video image of the luminance value of each pixel of the reference image Pf.
Fig. 5 (c) illustrates a video of the luminance value of each pixel of the inspection image Pk.
Fig. 5 (d) illustrates a video of a difference in luminance value between the inspection image Pk and the reference image Pf.
The image processing unit 7 processes the image Ps captured by the capturing unit 3. Specifically, the image processing unit 7 includes a dynamic replacement processing unit 71, a comparison inspection unit 72, and the like.
The dynamic replacement processing unit 71 performs a replacement process of replacing the luminance value of a pixel (a portion indicated by a broken line Y) corresponding to the non-inspection region Rn among the pixels constituting the image Ps with the luminance value of the reference image Pf on the basis of the chip layout and the positional information on the wafer W on which the image Ps is captured, with respect to the image Ps obtained by capturing the incomplete chip Cb formed over the inspection region Ri and the non-inspection region Rn, thereby generating the inspection image Pk.
Specifically, the relative position between the wafer W and the imaging unit 3 at the time of capturing the image Ps is acquired, and the positional information is compared with the chip layout to determine whether each pixel in the captured image Ps is a pixel located in the inspection region Ri or a pixel located in the non-inspection region Rn. Then, a replacement process of replacing the pixels (the portion indicated by the broken line Y) located in the non-inspection region Rn with the luminance values of the corresponding pixels of the reference image Pf is performed, thereby generating an inspection image Pk. At this time, the luminance value of the pixel (also referred to as the inspection target pixel) which is not related to the non-inspection region Rn in the image Ps is directly given to the inspection image Pk. That is, if the inspection target pixel has a defect X, the luminance value of the photographed defect X is reflected in the inspection image Pk.
The comparison and inspection unit 72 compares the inspection image Pk generated by the dynamic displacement processing unit 71 with the reference image Pf, and inspects the inspection target portion.
Specifically, the comparison inspection unit 72 compares the inspection image Pk of the inspection target portion including the repetitive appearance pattern of the device chip C with the corresponding pixels of the reference image Pf, and determines that the pixel or the pixel group is normal if the difference or variance value of the luminance value is within a predetermined range, and determines that the pixel or the pixel group is abnormal if the difference or variance value is outside the predetermined range.
Therefore, the defect X can be detected by performing a comparison process on the inspection image Pk and the reference image Pf by the comparison inspection section 72, and extracting a portion where the difference in luminance value is outside the reference range.
In addition to the above functions, the image processing unit 7 has the following functions, as needed: the split images are spliced, a portion necessary for inspection is extracted (cut out) from the entire image including the edge, brightness values of the pixels are corrected, curvature of the image Ps is corrected, and the like, and arithmetic processing is performed.
The reference image registration unit 6, the chip layout registration unit 5, and the image processing unit 7 of the present invention are configured by a computer CP (i.e., hardware) having an image processing function, and an execution program or the like (i.e., software) thereof.
More specifically, the chip layout registration unit 5 and the reference image registration unit 6 are constituted by a part of a storage unit (a register, a memory, or the like) or a recording medium (HDD, SSD, or the like) of the computer CP, and the image processing unit 7 is constituted by an image processing unit (so-called GPU) of the computer CP.
The computer CP is responsible for various functions and roles, for example, as follows.
Registration of information (so-called inspection step) such as imaging magnification and imaging position, imaging path T, imaging interval (pitch, interval), and feeding speed for each inspection item
Registration of inspection conditions (normal ranges of brightness values, variance values, and the like of the inspection target portion, and the like) for each inspection item
Connected to a user interface (keyboard, SW, monitor, etc.), and inputting/outputting various information
Connected to the control unit CN, an external host computer, etc., for inputting/outputting signals and data
The inspection step or inspection condition for each inspection item is also called menu information or inspection menu.
The control unit CN is responsible for various functions and actions described below, for example.
Outputting a signal for holding/releasing the wafer W to the wafer holding section 2
Control of the rotator mechanism 34 to switch the objective lens (photographing magnification) to be used
Output of the light emission trigger by the lighting section 31
Output of a shooting trigger to the camera 35
Drive control monitoring of the relative movement section 4: monitor the current positions of the X-axis slider 41, the Y-axis slider 42, and the rotation mechanism 43, and output a driving signal
Outputting the current position information of the relative movement unit 4 (X-axis slider 41, Y-axis slider 42, rotation mechanism 43) to the computer CP
Control of the parts based on the inspection menu
The following various modes can be exemplified as the output of the shooting trigger from the control unit 9 to the shooting unit 3.
Scanning movement in the X direction and a manner of causing the illumination light L1 to emit light for an extremely short time (so-called strobe light emission) every time a predetermined distance is moved.
Or a method of moving and standing at a predetermined position and irradiating the illumination light L1 to perform imaging (so-called step & repeat).
The shooting trigger means an image capturing instruction to the camera 35 or the image processing unit 7, a lighting instruction of the illumination light L1, or the like. Specifically, as the shooting trigger, (case 1) the illumination light L1 is strobed to emit light for a time (so-called exposure time) in which shooting by the camera 35 is possible, and (case 2) shooting is performed or for a time in which the illumination light L1 is irradiated. Alternatively, the shooting trigger is not limited to the instruction to the camera 35, and (case 3) may be an image capturing instruction to an image processing apparatus that acquires an image. This can cope with a system in which video signals or video data are sequentially output from the camera 35.
More specifically, the control section CN is constituted by a computer or a programmable logic controller or the like (i.e., hardware), and an execution program or the like (i.e., software) thereof.
[ Inspection procedure ]
Fig. 6 is a flowchart showing an example of a mode for embodying the present invention. Fig. 6 shows, as a series of processes, a process of photographing and inspecting the inspection region Ri and the non-inspection region Rn of the device chip C arranged on the wafer W using the wafer appearance inspection apparatus 1 for each process.
Before inspection, the chip layout of the inspection region Ri and the non-inspection region Rn of the wafer W, which define the reference posture and the reference position for the wafer W, is registered in advance (step s 11), and the reference image Pf is registered in advance (step s 12).
Then, an inspection menu is set to determine the inspection mode and the inspection order of the wafer W (step s 13).
Next, the wafer W is placed on the stage 20 of the wafer visual inspection apparatus 1 (step s 21), and the wafer is moved to a reading position of a reference mark (not shown) formed on the wafer W, and alignment is performed (step s 22).
The wafer W and the imaging unit 3 are relatively moved, an image Ps including the inspection target portion is imaged (step s 23), and the imaged image Ps is subjected to the subsequent processing.
First, with respect to an image Ps obtained by capturing an incomplete chip Cb formed over an inspection region Ri and a non-inspection region Rn, a replacement process is performed to replace the luminance value of a pixel corresponding to the non-inspection region Rn among pixels constituting the image Ps with the luminance value of a reference image Pf based on the positional information on the wafer W and the chip layout on which the image Ps is captured, thereby generating an inspection image Pk (step s 31).
Then, the inspection image Pk and the reference image Pf are compared, and the inspection target portion is inspected (step s 32). Specifically, the corresponding pixels of the inspection image Pk and the reference image Pf are compared with each other, and if the difference or variance value of the luminance value or the like is within a predetermined range for each pixel or pixel group, the detection image Pk and the reference image Pf are judged to be normal, and if the difference or variance value is out of the predetermined range, the detection image Pk and the reference image Pf are judged to be abnormal. Then, a portion where the difference of the luminance values is outside the reference range is extracted, thereby detecting the defect X.
Then, it is determined whether or not the photographing and inspection are finished for all the predetermined inspection target parts (step 41), and if not, the photographing and inspection are continued. On the other hand, if the photographing/inspection is completed, the wafer W is taken out of the apparatus (step s 42).
Then, it is determined whether or not the next wafer W exists (step s 43), and if the next wafer W is inspected, the above steps s21 to s43 are repeated. On the other hand, if there is no next wafer W, the series of processes is ended.
According to the wafer appearance inspection apparatus 1 and the inspection method of the present invention, even if an incomplete chip Cb is formed on the wafer W over the inspection region Ri and the non-inspection region Rn, the inspection image Pk can be generated by performing the dynamic replacement processing according to the imaging position, and the inspection image Pk can be compared with the reference image Pf to perform the desired inspection. At this time, even for the incomplete chip Cb, the inspection region Ri of the wafer W can be inspected in correspondence with the complete chip Cn, and a desired inspection result can be obtained for the entire inspection region Ri of the wafer W. In addition, special treatment for suspected defects is not required. That is, regardless of whether the chip Cn is a complete chip or an incomplete chip Cb, a desired inspection result can be obtained for the entire inspection region Ri of the wafer W, and an increase in processing time can be prevented.
Modification example
In the above description, the structure and the step of detecting the defect X in which the foreign matter is attached to the circuit pattern are shown as specific examples of the inspection. However, in the case of embodying the present invention, the inspection object is not limited to the adhesion of foreign matter, and it is sufficient to appropriately determine whether or not there is no item such as a short circuit or a disconnection, or whether or not there is no defect, and to determine the imaging condition, the inspection condition, or the like.
In the above, fig. 6 is shown as a step for embodying the present invention, and the steps of performing registration/setting in the order of registration of the chip layout (step s 11), registration of the reference image Pf (step s 12), and setting of the inspection menu (step s 13) are exemplified, but may be performed in other orders than this. For example, the reference image Pf may be registered before the registration of the chip layout, or the setting of the inspection menu may be performed.
In the above description, the imaging range of the camera 35 of the imaging unit 3 is set to the imaging region F including the inspection target portion of 1 device chip C. However, the imaging range of the camera 35 may be divided for each inspection target portion of the device chip C, or may be set to a wide range including the inspection target portions of the plurality of device chips C.
Description of the reference numerals
1 Wafer appearance inspection device
2 Wafer holder
3 Shooting part
4 Relative movement part
5 Chip layout registration section
6 Reference image registration unit
7 Image processing section
1F device frame
20. Mounting table
30. Lens barrel
31. Lighting part
32. Half mirror
33A, 33b objective lens
34. Rotator mechanism
35. Video camera
41 X-axis slider
42 Y-axis slider
43. Rotary mechanism
71. Dynamic replacement processing unit
72. Comparison inspection part
CN control part
W wafer
C device chip
Cn complete chip
Cb incomplete chip
F shooting area (visual field)
Ri examination area
Rn non-examination region
Ps image
Pk inspection image
Pf reference image
L1 illumination light
L2 light incident from the wafer side (reflected light, scattered light)
T shooting path
Claims (2)
1. A wafer appearance inspection apparatus for inspecting a device chip formed on a wafer by photographing an inspection target portion of a repetitive appearance pattern of the device chip and comparing the inspection target portion with a reference image,
The wafer appearance inspection device comprises:
A wafer holding section that holds the wafer;
an imaging unit that images an image including the inspection target portion;
A relative movement unit that relatively moves the wafer holding unit and the imaging unit;
A chip layout registration unit that registers a chip layout that defines positional information of an inspection region and a non-inspection region of the wafer and arrangement information of device chips, the positional information corresponding to a reference posture and a reference position of the wafer;
a reference image registration unit that registers the reference image; and
An image processing unit that processes the image captured by the capturing unit,
The image processing unit includes:
A dynamic replacement processing unit that generates an inspection image by performing a replacement process of replacing a luminance value of a pixel corresponding to the non-inspection region among pixels constituting the image with a luminance value of the reference image, based on the chip layout and position information on the wafer where the image is captured, with respect to the image obtained by capturing the inspection target portion of the incomplete chip formed over the inspection region and the non-inspection region; and
And a comparison inspection unit that compares the inspection image generated by the dynamic displacement processing unit with the reference image, and inspects the inspection target portion.
2. A wafer appearance inspection method for inspecting a device chip by photographing an inspection target portion of a repetitive appearance pattern of the device chip formed on a wafer and comparing the inspection target portion with a reference image,
The wafer appearance inspection method has the steps of:
registering a chip layout in advance, the chip layout defining an inspection area and a non-inspection area of the wafer corresponding to a reference posture and a reference position of the wafer;
Registering the reference image in advance;
relatively moving the wafer and the photographing unit and photographing a first image including the inspection object part; and
The first image is processed and the second image is processed,
And, the method comprises the following steps:
Performing a replacement process of replacing a luminance value of a pixel corresponding to the non-inspection region among pixels constituting the first image with a luminance value of the reference image based on the chip layout and the positional information on the wafer where the first image is captured, with respect to the first image obtained by capturing the incomplete chip formed throughout the inspection region and the non-inspection region, thereby generating an inspection image; and
The inspection image is compared with the reference image, and the inspection target portion is inspected.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019152538A JP7293046B2 (en) | 2019-08-23 | 2019-08-23 | Wafer visual inspection apparatus and method |
| JP2019-152538 | 2019-08-23 | ||
| PCT/JP2020/022717 WO2021039019A1 (en) | 2019-08-23 | 2020-06-09 | Wafer appearance inspection device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114222913A CN114222913A (en) | 2022-03-22 |
| CN114222913B true CN114222913B (en) | 2024-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080057392.9A Active CN114222913B (en) | 2019-08-23 | 2020-06-09 | Wafer appearance inspection device and method |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP7293046B2 (en) |
| KR (1) | KR20220044742A (en) |
| CN (1) | CN114222913B (en) |
| WO (1) | WO2021039019A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP7293046B2 (en) | 2023-06-19 |
| KR20220044742A (en) | 2022-04-11 |
| WO2021039019A1 (en) | 2021-03-04 |
| CN114222913A (en) | 2022-03-22 |
| TW202109022A (en) | 2021-03-01 |
| JP2021032672A (en) | 2021-03-01 |
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