CN114218075B - Method for generating test implementation sample library of airborne equipment testability test - Google Patents
Method for generating test implementation sample library of airborne equipment testability test Download PDFInfo
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Abstract
The invention provides a method for generating a test implementation sample library of airborne equipment, which comprises the following steps: step S1, analyzing the lower-layer fault reasons according to the fault mode of a test sample to obtain a plurality of fault reasons, and taking the test sample as an alternative implementation sample; step S2, determining an implementation sample and the execution times thereof in a plurality of alternative implementation samples in step S1; s3, analyzing injection means and injection types which can be implemented in the implementation sample; s4, determining fault injection success criteria of the implementation samples; s5, determining a detection criterion/isolation criterion; and S6, establishing a sample library. The invention can provide a method for generating the sample for the test of the airborne equipment, thereby ensuring the accuracy of the test.
Description
Technical Field
The invention relates to the field of onboard equipment tests, in particular to a method for generating an implementation sample library of an onboard equipment testability test.
Background
The testability refers to a design characteristic that a product can timely and accurately determine its working state and effectively isolate its internal faults. In order to analyze, verify or evaluate the design level of the product, an in-field testability test under laboratory conditions can be performed, namely, faults with a certain number of samples are injected into the product, fault detection and isolation are performed by using a test method specified by the design level of the product, the design level of the product is evaluated by carrying out statistical analysis on the results, whether the design meets the requirements or not is analyzed, and design defects and problems are identified.
How to determine the number of samples and how to select reasonable test implementation samples and the execution times thereof under the number are the premise that test results can be effective. Therefore, in order to guide and restrict the development of the test and achieve the purpose of test evaluation, each implementation sample needs to be determined, the execution times of the test sample need to be calculated, and the implementation means and the implementation criteria of each implementation sample need to be designed, so that the fault injection is accurate and feasible, and the test sample judgment is reasonable and effective; and the orderly development of test implementation is promoted, and the test efficiency and the result are reliable. However, in the prior art, no good method is available for establishing a test implementation sample library, so that a testability test cannot be well carried out.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a method for generating a sample library for carrying out the test of the airborne equipment, which can provide a method for generating samples for the test of the airborne equipment, thereby ensuring the accuracy of the test, combining with the specific requirements of the test of the airborne equipment, better collecting relevant samples and providing reliable sample data for subsequent tests.
Specifically, the invention provides a method for generating a test implementation sample library of airborne equipment, which comprises the following steps:
S1, analyzing the lower-layer fault reasons according to the fault mode of a test sample to obtain a plurality of fault reasons, and taking the test sample as an alternative implementation sample;
S2, determining an implementation sample and the execution times thereof in a plurality of alternative implementation samples in the step S1, wherein the implementation sample comprises the following steps:
S21, assuming a certain test sample, namely a certain fault mode M 1, which has N fault reasons, namely N alternative implementation samples, and the test sample is sampled or distributed to obtain a sample size of N 1, meanwhile, assuming that N 1 implementation samples capable of executing fault injection exist in the N fault reasons of the test sample, and N 1 implementation samples need to execute at least N 1 fault injections altogether;
S22, assuming that the failure rates of n 1 implementation samples capable of executing failure injection in n failure reasons are respectively lambda i, calculating the execution times P i of each failure reason according to the following formula:
If the calculation result is not zero, the step S23 is entered, if the calculation result is zero, the alternative implementation sample associated with the fault cause is not selected to be implemented as the implementation sample, and the steps S21-S22 are repeated after the alternative implementation sample is replaced until the calculation result is not zero, and the alternative implementation sample associated with the fault cause is selected as the implementation sample;
S23, summing the calculation results of the P i to obtain sigma P i, comparing sigma P i with the total number of times N 1 of fault injection, if sigma P i=N1, directly entering step S25, otherwise, entering step S24;
S24, if Σp i<N1 is obtained and n 1>N1, sequentially adjusting the fault cause of P i =0 to P i =1 according to the size of λ i until Σp i=N1, and then proceeding to step S25;
If Σp i<N1 and n 1≤N1 are obtained, then P i is sequentially complemented by 1 according to the size of λ i until Σp i=N1, and then step S25 is entered;
S25, taking the fault mode M 1 as an execution implementation sample, and outputting the execution implementation sample and the fault injection execution times P i thereof;
S3, acquiring the number of the implementation samples determined in the step S2, and analyzing injection means and injection types which can be implemented in the implementation samples, wherein the number of the injection means is equal to the fault injection execution times P i of the implementation samples;
s4, determining fault injection success criteria of the implemented samples according to the fault characteristics of the fault modes of the samples and the measurable positions thereof, which are obtained in the step S1, so as to determine whether the faults are successfully injected and perform simulated injection in the test;
S5, determining a detection criterion/isolation criterion according to a detection method and parameter information of a fault mode to which a sample belongs, so that whether the fault is detected/isolated as an expected method can be determined in a test;
S6, analyzing all the candidate test samples according to the steps S1 to S5 to obtain a plurality of data, forming a test implementation fault database and injecting the test implementation fault database into a sample library.
Preferably, the parameter information in step S5 is detection report and display information.
Preferably, in step S4, the fault characteristic used for determining whether the fault injection is successful is an intuitively measurable fault characteristic corresponding to the fault mode to which the sample belongs.
Preferably, step S5 specifically comprises the following sub-steps:
S51, detecting phenomena under the laboratory condition are designed clearly, wherein the detecting phenomena comprise observation means and observation contents;
S52, designing and defining detection result fault information corresponding to the detection phenomenon in actual use, wherein the detection result fault information comprises detection equipment and detection results;
S53, for samples needing to verify fault isolation, corresponding isolation fuzzy groups are analyzed one by one from various possible detection phenomena and combinations thereof, and the detection phenomena are used as the basis for judging the isolation results.
Preferably, the five types of fault injection defined in step S3 include external bus fault injection, probe fault injection, software fault injection, patch panel fault injection, and plug-in fault injection.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention provides a method for generating an implementation sample library of an airborne equipment testability test, which can provide sample selection, implementation methods, criterion design and execution times calculation methods for the airborne equipment testability test, and can provide reasonable and engineering executable implementation samples for the testability test, thereby standardizing the implementation range and implementation modes of the test, guiding implementation operation and ensuring objective and accurate test results.
(2) The generation method of the sample library combines the specific requirements of the airborne equipment testability test, can better collect the relevant samples, and provides reliable sample data for the subsequent test.
Drawings
Fig. 1 is a schematic flow chart of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Specifically, the invention provides a method for generating a test implementation sample library of an onboard equipment, which comprises the following steps of:
S1, analyzing the lower-layer fault reasons according to the fault mode of a test sample to obtain a plurality of fault reasons, and taking the test sample as an alternative implementation sample;
S2, determining an implementation sample and the execution times thereof in a plurality of alternative implementation samples in the step S1, wherein the implementation sample comprises the following steps:
S21, assuming a certain test sample, namely a certain fault mode M 1, which has N fault reasons, namely N alternative implementation samples, and the test sample is sampled or distributed to obtain a sample size of N 1, meanwhile, assuming that N 1 implementation samples capable of executing fault injection exist in the N fault reasons of the test sample, and N 1 implementation samples need to execute at least N 1 fault injections altogether;
S22, assuming that the failure rates of n 1 implementation samples capable of executing failure injection in n failure reasons are respectively lambda i, calculating the execution times P i of each failure reason according to the following formula:
If the calculation result is not zero, the step S23 is entered, if the calculation result is zero, the alternative implementation sample associated with the fault cause is not selected to be implemented as the implementation sample, and the steps S21-S22 are repeated after the alternative implementation sample is replaced until the calculation result is not zero, and the alternative implementation sample associated with the fault cause is selected as the implementation sample;
S23, summing the calculation results of the P i to obtain sigma P i, comparing sigma P i with the total number of times N 1 of fault injection, if sigma P i=N1, directly entering step S25, otherwise, entering step S24;
S24, if Σp i<N1 is obtained and n 1>N1, sequentially adjusting the fault cause of P i =0 to P i =1 according to the size of λ i until Σp i=N1, and then proceeding to step S25;
If Σp i<N1 and n 1≤N1 are obtained, then P i is sequentially complemented by 1 according to the size of λ i until Σp i=N1, and then step S25 is entered;
S25, taking the fault mode M 1 as an execution implementation sample, and outputting the execution implementation sample and the fault injection execution times P i thereof;
S3, acquiring the number of the implementation sample determined in the step S2, and analyzing injection means and injection types which can be implemented in the implementation sample, wherein the number of the injection means is equal to the fault injection execution times P i of the implementation sample;
s4, determining fault injection success criteria of the implemented samples according to the fault characteristics of the fault modes of the samples and the measurable positions thereof, which are obtained in the step S1, so as to determine whether the faults are successfully injected and perform simulated injection in the test;
S5, determining a detection criterion/isolation criterion according to a detection method and parameter information of a fault mode to which a sample belongs, so that whether the fault is detected/isolated as an expected method can be determined in a test;
S6, analyzing all the candidate test samples according to the steps S1 to S5 to obtain a plurality of data, forming a test implementation fault database and injecting the test implementation fault database into a sample library.
Preferably, the parameter information in step S5 is detection report and display information.
Preferably, in step S4, the fault characteristic used for determining whether the fault injection is successful is an intuitively measurable fault characteristic corresponding to the fault mode to which the sample belongs.
Preferably, step S5 specifically comprises the following sub-steps:
S51, detecting phenomena under the laboratory condition are designed clearly, wherein the detecting phenomena comprise observation means and observation contents;
S52, designing and defining detection result fault information corresponding to the detection phenomenon in actual use, wherein the detection result fault information comprises detection equipment and detection results;
s53, for samples needing to verify fault isolation, corresponding isolation fuzzy groups are analyzed one by one from various possible detection phenomena such as fault codes and the like and combinations thereof, and the detection phenomena are used as the basis for judging the isolation results.
Preferably, the step S3 specifically includes the following steps:
s31, defining five types of fault injection types including external bus type fault injection, probe type fault injection, software type fault injection, transfer plate type fault injection and plug type fault injection;
s32, the product unit adopts fault modes such as open circuit, short circuit, error and the like of external communication lines, and adopts fault modes such as open circuit, short circuit, failure and the like of external power supply, and generally adopts an external bus type fault mode. The implementation mode is that the injection is generally carried out through an external electric connector of the product unit, when the product unit needs to work in cascade with other units or excitation equipment, a fault injector is arranged in a data transmission link between the product unit or the unit and the excitation equipment, and the injection of faults is realized by changing data, signals or physical structures of the link; when the product units can independently operate and the external excitation can influence the product functions, the fault injector is directly connected with an external electric connector of the product units, and the fault injection is realized by simulating the fault excitation.
S33, short circuit of resistor, capacitor, magnetic bead and inductor, parameter drift, error output of power supply, frequency and bus signal, and other fault modes of short circuit between certain pin/pins 2-more pins of the chip, and the like, and probe type fault injection is generally adopted. The method is mainly used for fault injection on the device, and the implementation mode generally enables a fault injection probe to be in contact with the pin or pin connecting line of the injected device, and injection fault stress changes the output of the device, so that fault injection is realized. Such as:
Shorting the two ends of the resistor, the capacitor, the resistor and the inductor;
Disconnecting the resistor, the capacitor, the magnetic beads and the inductor, and externally connecting corresponding programmable devices for adjustment;
disconnecting the power supply and the frequency output end, and performing output adjustment by external equipment;
Shorting, fixing high and fixing low internal bus signals of the board card;
And shorting, fixing high and fixing low the chips on the board card.
The large-scale integrated chips such as S34 and FPGA, DSP, ARM, and the related functional failure, address error, logic error and output data error fault modes of part of programming chips (such as registers, programmable oscillators and CPLDs) generally adopt software fault modes. The implementation simulates the chip failure by modifying the code in the programmable chip according to some failure model, thereby simulating the product functional failure resulting from its basic failure. Such as: modifying an i-th line in a program file of a chip using a type emulator/a type board/a type downloader/changing a code variable output to a certain error value. The method is specifically divided into compile-time fault injection and runtime fault injection according to fault injection time.
S35, a fault mode that a certain pin or pins on the board indirect plug-in are opened, short-circuited or at other pin levels is short-circuited, and the function of the pin signals of the plug-in is invalid, so that a transfer board type fault injection can be adopted. The implementation mode is that a signal transfer board which can be arranged between the board indirect plug-ins is designed and manufactured, signals are transferred out, and the functional failure of products is simulated on the transfer signals through the change of the board-to-board transmission data (signal) transmission interface in a physical layer, an electric layer and a protocol layer.
S36, fault modes such as resistance, capacitance, magnetic beads, open capacitor, open circuit of part of pins of an integrated chip, open circuit of a power input or output end and the like can be generally adopted for plug-in fault injection. The implementation mode can implement fault injection through modes of plugging components, circuit boards, wires and the like, and generally comprises the following steps:
removing the pins of the components and connecting the pins to a ground wire or a power supply;
removing the pins from the socket and then applying a power or ground signal at the empty jack;
Removing the pins from the socket to enable the pins to be in a disconnected state;
Completely removing the component from the socket;
shorting two pins of the component;
The circuit board is removed from the base plate.
The working process and principle of the invention are further described below with reference to specific embodiments:
the embodiment selects different types of fault mode samples of a certain system for explaining a design and calculation method of a test sample library, and the method flow steps comprise sample selection and execution times determination, fault injection type and test means design, fault injection success criteria and detection isolation criteria design. The procedure included 3 failure samples.
Failure sample one:
And determining that the fault sample loses one path of gesture information output function for a certain component. The sample library is calculated and designed based on the fault samples described above, see the sequence numbers 1-3 in table 1 below.
The specific method flow is as follows:
(1) Analyzing the lower-layer fault reasons according to the fault mode of the sample, and taking the fault reasons such as no output of an interface XS1-1, no clock input of a single board and invalid EEPROM read-write function as alternative implementation samples;
(2) According to the condition of the implementation sample, calculating the implementation sample and the execution times thereof:
The sample quantity N 1 =4 of the fault sample distribution, the fault rate data lambda i of three fault reasons are respectively '1.352830401 multiplied by 10 -6/h"、"0.833805301×10-6/h"、"0.880989401×10-6/h', and the execution times P i are respectively '2, 1 and 1' calculated according to the calculation method of the invention;
(3) Numbering the determined implementation samples, and analyzing the implementation injection means and injection types of the implementation samples: according to the method, according to the fault reasons, the 'adapter plate', 'plug' fault injection types are selected, and corresponding test means are provided;
(4) Determining fault injection success criteria of test samples according to fault characteristics of fault modes of the samples and measurable positions of the fault characteristics;
(5) And determining a detection criterion and an isolation criterion according to the detection method of the fault mode of the sample, detection report/display information and the like.
And a fault sample II:
The failure sample is determined to be 2.1V out of tolerance for the a-channel LVDT output. The sample libraries were calculated and formed as set forth in Table 1 below, numbered 4-6.
The specific method flow is as follows:
(1) Analyzing the lower-layer fault reasons according to the fault mode of the sample, and taking the fault reasons of incorrect stroke of the A channel motor, zero out-of-tolerance of the A channel sensor and out-of-tolerance of the A channel sensor as alternative implementation samples;
(2) According to the actual condition of sample selection, calculating the sample and the execution times:
The sample quantity N 1 =7 of the fault sample distribution, the fault rate data lambda i of three fault reasons are respectively '2.892830741 multiplied by 10 -6/h"、"1.398542562×10-6/h"、"0.795861358×10-6/h', and the execution times P i obtained by the calculation method are respectively '4, 2 and 1';
(3) To select the determined implementation sample number, and analyze the implementation injection means and injection type: according to the method, according to the fault reasons, the types of software and probe fault injection are selected, and corresponding test means are provided;
(4) Determining fault injection success criteria of test samples according to fault characteristics of fault modes of the samples and measurable positions of the fault characteristics;
(5) And determining a detection criterion and an isolation criterion according to the detection method of the fault mode of the sample, detection report/display information and the like.
And (3) a fault sample III:
the failure of the fault sample "CZ limit" signal output function is determined. A sample library is calculated and formed as shown in table 1 below, number 7.
The specific method flow is as follows:
(1) Analyzing the lower-layer fault cause according to the fault mode of the sample, and taking the fault cause ' CZ limit ' signal level functional failure ' as an alternative implementation sample;
(2) Because only one fault cause exists, calculation of sample execution times is not needed;
(3) To select the determined implementation sample number, and analyze the implementation injection means and injection type: according to the method, according to the fault reasons, the 'plug' type fault injection type is selected, and corresponding test means are designed;
(4) Determining fault injection success criteria of test samples according to fault characteristics of fault modes of the samples and measurable positions of the fault characteristics;
(5) And determining a detection criterion and an isolation criterion according to the detection method of the fault mode of the sample, detection report/display information and the like. The difference is that under the manual detection means of the external field, the criteria are filled out by the phenomena observed under the laboratory conditions and the corresponding external field phenomena.
The table templates of the test sample library calculated by the above steps are shown in table 2 below.
Each row represents an alternative sample, and the content corresponding to each column is respectively: sequence number, alternative sample code, failure mode, failure cause, failure injection type, failure injection method, failure injection success criterion, detection method, detection criterion, expected execution times and non-injectable cause. Each alternative sample code should fill in the corresponding content according to the characteristics of the own alternative sample.
The above examples are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the scope of protection defined by the claims of the present invention without departing from the spirit of the present invention.
Claims (5)
1. A method for generating a test implementation sample library of airborne equipment is characterized by comprising the following steps of: which comprises the following steps:
S1, analyzing the lower-layer fault reasons according to the fault mode of a test sample to obtain a plurality of fault reasons, and taking the test sample as an alternative implementation sample;
S2, determining an implementation sample and the execution times thereof in a plurality of alternative implementation samples in the step S1, wherein the implementation sample comprises the following steps:
S21, assuming a certain test sample, namely a certain fault mode M 1, which has N fault reasons, namely N alternative implementation samples, and the test sample is sampled or distributed to obtain a sample size of N 1, meanwhile, assuming that N 1 implementation samples capable of executing fault injection exist in the N fault reasons of the test sample, and N 1 implementation samples need to execute at least N 1 fault injections altogether;
S22, assuming that the failure rates of n 1 implementation samples capable of executing failure injection in n failure reasons are respectively lambda i, calculating the execution times P i of each failure reason according to the following formula:
If the calculation result is not zero, the step S23 is entered, if the calculation result is zero, the alternative implementation sample associated with the fault cause is not selected to be implemented as the implementation sample, and the steps S21-S22 are repeated after the alternative implementation sample is replaced until the calculation result is not zero, and the alternative implementation sample associated with the fault cause is selected as the implementation sample;
S23, summing the calculation results of the P i to obtain sigma P i, comparing sigma P i with the total number of times N 1 of fault injection, if sigma P i=N1, directly entering step S25, otherwise, entering step S24;
S24, if Σp i<N1 is obtained and n 1>N1, sequentially adjusting the fault cause of P i =0 to P i =1 according to the size of λ i until Σp i=N1, and then proceeding to step S25;
If Σp i<N1 and n 1≤N1 are obtained, then P i is sequentially complemented by 1 according to the size of λ i until Σp i=N1, and then step S25 is entered;
S25, taking the fault mode M 1 as an execution implementation sample, and outputting the execution implementation sample and the fault injection execution times P i thereof;
S3, acquiring the number of the implementation samples determined in the step S2, and analyzing injection means and injection types which can be implemented in the implementation samples, wherein the number of the injection means is equal to the fault injection execution times P i of the implementation samples;
s4, determining fault injection success criteria of the implemented samples according to the fault characteristics of the fault modes of the samples and the measurable positions thereof, which are obtained in the step S1, so as to determine whether the faults are successfully injected and perform simulated injection in the test;
S5, determining a detection criterion/isolation criterion according to a detection method and parameter information of a fault mode to which a sample belongs, so that whether the fault is detected/isolated as an expected method can be determined in a test;
S6, analyzing all the candidate test samples according to the steps S1 to S5 to obtain a plurality of data, forming a test implementation fault database and injecting the test implementation fault database into a sample library.
2. The method for generating the test implementation sample library for the on-board equipment according to claim 1, wherein: the parameter information in step S5 is detection report and display information.
3. The method for generating the test implementation sample library for the on-board equipment according to claim 1, wherein: in step S4, the fault feature used for judging whether the fault injection is successful is an intuitive and measurable fault feature corresponding to the fault mode to which the sample belongs.
4. The method for generating the test implementation sample library for the on-board equipment according to claim 2, wherein: the step S5 specifically includes the following substeps:
S51, detecting phenomena under the laboratory condition are designed clearly, wherein the detecting phenomena comprise observation means and observation contents;
S52, designing and defining detection result fault information corresponding to the detection phenomenon in actual use, wherein the detection result fault information comprises detection equipment and detection results;
S53, for samples needing to verify fault isolation, corresponding isolation fuzzy groups are analyzed one by one from various possible detection phenomena and combinations thereof, and the detection phenomena are used as the basis for judging the isolation results.
5. The method for generating the test implementation sample library for the on-board equipment according to claim 1, wherein: in step S3, five types of fault injection types are defined, including external bus fault injection, probe fault injection, software fault injection, patch panel fault injection, and plug-in fault injection.
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