CN114203791A - Display panel and display device - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The application provides a display panel and a display device. The display panel comprises a first display area and a second display area, wherein the sub-pixel density of the first display area is less than that of the second display area; the first display area comprises a wiring area and a pixel row extending along a first direction, the pixel row comprises a plurality of pixel areas, one pixel area comprises n sub-pixels and n pixel circuits, and the first wiring area is positioned between two adjacent pixel areas in a second direction; the signal line extending along the second direction comprises a first line segment positioned in the first wiring area and a second line segment positioned in the pixel area, and the second line segment is electrically connected with the pixel circuit; the pixel array comprises a first pixel row and a second pixel row which are adjacent, wherein the first pixel row comprises N sub-pixels, the second pixel row comprises M sub-pixels, and N is less than or equal to M; the total number of first line segments between the first pixel row and the second pixel row is less than N. The area of the light-transmitting area of the first display area can be increased, and the diffraction phenomenon when light penetrates through the first display area is improved.
Description
The application is a divisional application with application date of 2019, 11, 29 and application number of 201911207034.7, and the name of 'display panel and display device'.
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, people not only require smooth use experience for electronic products, but also increasingly require visual experience, and the high screen ratio becomes the direction of current research. For electronic products, the arrangement of optical devices such as a front camera inevitably occupies a certain space, thereby affecting the screen ratio. In order to improve the screen occupation ratio and realize a full screen, researchers consider the implementation scheme of the optical device under the screen.
The optical device is arranged below the film layer of the display panel where the light-emitting device is located, namely the optical device is arranged in the display area. When the display is needed, the position of the optical device can be displayed normally; when the optical device is needed, light penetrates through the display panel to reach the optical device and is finally utilized by the optical device. The optical device is arranged under the screen, light rays can be utilized by the optical device only by penetrating through a film layer structure of the display panel, and the imaging quality of the optical device under the screen is poor and the requirements of users are difficult to meet when the current scheme for arranging the optical device under the screen is evaluated and found.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for solving the technical problems that an optical device under a screen in the prior art is poor in imaging quality and cannot meet user requirements easily.
In order to solve the above technical problem, in a first aspect, the present invention provides a display panel, a display area of the display panel includes a first display area and a second display area, the display area includes a plurality of sub-pixels, and a density of the plurality of sub-pixels of the first display area is less than a density of the plurality of sub-pixels of the second display area;
the first display area comprises a plurality of wiring areas and a plurality of pixel rows extending along a first direction, one pixel row comprises a plurality of pixel areas arranged in the first direction, one pixel area comprises n sub-pixels and n pixel circuits, n is a positive integer, the sub-pixels are electrically connected with the pixel circuits, the plurality of wiring areas comprises a plurality of first wiring areas, one first wiring area is positioned between two adjacent pixel areas in a second direction, and the second direction is crossed with the first direction;
the first display area further comprises a plurality of signal lines extending along the second direction, when the display panel is driven to display, constant voltage signals are provided for the signal lines, the signal lines comprise a first line segment and a second line segment, the first line segment is located in the first wiring area, the second line segment is located in the pixel area, and the second line segment is electrically connected with the pixel circuit in the pixel area; wherein the content of the first and second substances,
the pixel rows comprise a first pixel row and a second pixel row which are adjacent, the first pixel row comprises N sub-pixels, the second pixel row comprises M sub-pixels, N and M are positive integers, and N is less than or equal to M; the total number of first line segments in the plurality of first routing areas between the first pixel rows and the second pixel rows is less than N.
Based on the same inventive concept, in a second aspect, the invention further provides a display device comprising any one of the display panels provided by the invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects:
this application design has reduced the number of signal line between adjacent first pixel row and the second pixel row, can reduce the area of non-printing opacity district in the first display area, also can the area of the printing opacity district of the first display area of corresponding increase to promote the luminousness of first display area, use in optical device's under the screen scheme, can increase optical device's under the screen received light volume, promote optical device's optical property. In addition, when light penetrates through the first display area, various routing lines arranged in the first display area can form a diffraction grating, and a diffraction effect can be generated on the light, for example, when the optical device under the screen is a camera, the imaging quality of the camera can be influenced by the diffraction phenomenon. The embodiment of the application can also improve the diffraction phenomenon when light penetrates through the first display area to a certain extent by reducing the number of signal lines between two adjacent pixel rows, thereby further improving the optical performance of the optical device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of an alternative implementation of a display panel provided in an embodiment of the present application;
FIG. 2 is an enlarged view of FIG. 1 at the location of region Q;
fig. 3 is a partial schematic view of a first display region of a display panel according to an embodiment of the present disclosure;
FIG. 4 is a partial schematic view of a display panel according to the related art;
FIG. 5 is a partial schematic view of an alternative embodiment of a first display area of a display panel according to an embodiment of the present disclosure;
fig. 6 is a partial schematic view of another alternative implementation of the first display area of the display panel provided in the embodiment of the present application;
fig. 7 is a partial schematic view of another alternative implementation of a first display region of a display panel provided in an embodiment of the present application;
fig. 8 is a partial schematic view of another alternative implementation of the first display area of the display panel according to the embodiment of the present application;
fig. 9 is a partial schematic view of another alternative implementation of a first display region of a display panel provided in an embodiment of the present application;
FIG. 10 is a schematic illustration of a portion of another alternative implementation of a first display area provided by an embodiment of the present application;
FIG. 11 is a schematic illustration of a portion of another alternative implementation of a first display area provided by an embodiment of the present application;
fig. 12 is a partial schematic view of another alternative implementation of the first display area of the display panel according to the embodiment of the present application;
fig. 13 is a partial schematic view of another alternative implementation of the first display region of the display panel according to the embodiment of the present application;
fig. 14 is a schematic diagram of another alternative implementation of the first display area of the display panel according to the embodiment of the present application;
fig. 15 is a schematic view of a display device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Based on the technical problem that exists among the correlation technique, this application embodiment provides a display panel and display device, through in the display area that optical device corresponds (first display area in this application), reduce the line segment number between two adjacent pixel rows to can increase the area of the light transmission zone in the first display area, promote the luminousness of first display area, also when using the optical device scheme under the screen, can increase the light volume that optical device received. Meanwhile, the diffraction phenomenon that light penetrates through the first display area can be improved, and the optical performance of the optical device under the screen is improved.
Fig. 1 is a schematic diagram of an alternative implementation of a display panel provided in an embodiment of the present application. Fig. 2 is an enlarged view of fig. 1 at the position of region Q. As shown in fig. 1, the display area AA of the display panel includes a first display area AA1 and a second display area AA2, the display area includes a plurality of sub-pixels sp, and as shown in fig. 2, the density of the plurality of sub-pixels sp in the first display area AA1 is less than that of the plurality of sub-pixels sp in the second display area AA 2; only the second display area AA2 is schematically shown in fig. 1 surrounding the first display area AA 1. Alternatively, the second display area AA2 may also semi-surround the first display area AA 1. The shape of the first display area AA1 in the embodiment of the present invention is not limited, and may be any one of a circle, an ellipse, a triangle, and a polygon. The display panel provided by the embodiment of the application can be an organic light-emitting display panel, and the organic light-emitting display panel comprises an array layer and a light-emitting layer positioned on the array layer. Wherein the light emitting layer comprises a plurality of light emitting devices and one sub-pixel sp comprises one light emitting device. The density of the plurality of sub-pixels sp of the first display area AA1 is less than that of the plurality of sub-pixels sp of the second display area AA2, that is, the density of the plurality of light emitting devices of the first display area AA1 is less than that of the plurality of light emitting devices of the second display area AA 2. The light transmittance per unit area of the first display region AA1 is greater than that per unit area of the second display region AA 2. In the case of an off-screen optics solution, optics may be disposed below first display area AA1 to ensure that the optics receive a sufficient amount of light when activated. When displayed, the first display area AA1 may be used to display information such as a notification symbol, a power symbol, a network symbol, and time.
Fig. 3 is a partial schematic view of a first display area of a display panel according to an embodiment of the present disclosure, and as shown in fig. 3, the first display area AA1 includes a plurality of routing areas ZQ and a plurality of pixel rows PH extending along a first direction x, one pixel row PH includes a plurality of pixel areas PQ arranged in the first direction x, one pixel area includes n sub-pixels sp and n pixel circuits DL, and n is a positive integer. n may be an integer of 1, 2, 3, or 4, and the sub-pixel sp is electrically connected to the pixel circuit DL. Only one pixel region including 3 sub-pixels sp and 3 pixel circuits DL is illustrated in fig. 3. Alternatively, one pixel region may include 1 subpixel and 1 pixel circuit, or one pixel region may include 4 subpixels and 4 pixel circuits. The division of the pixel region is related to the arrangement of the sub-pixels in the first display region, which may be related to the display method of the display panel. The embodiment of the invention is suitable for the display panel which is designed by adopting any sub-pixel arrangement mode.
The plurality of routing areas ZQ include a plurality of first routing areas ZQ1, one first routing area ZQ being located between two pixel areas PQ adjacent in the second direction y, the second direction y crossing the first direction x; the routing area ZQ is also an area for routing, and can concentrate the routing between two adjacent pixel areas PQ in the second direction y in the routing area ZQ.
The first display area AA1 further includes a plurality of signal lines X extending in the second direction y, and a constant voltage signal is supplied to the signal lines X when the display panel is driven to display. In one embodiment, the signal line X is a positive power supply signal line that supplies a constant voltage signal to the pixel circuit when driving the sub-pixels for display. In one embodiment, the signal line X is a reset signal line that supplies a constant reset signal to the pixel circuit when driving the sub-pixel for display.
The signal line X includes a first line segment D1 and a second line segment D2, the first line segment D1 is located in the first routing area ZQ1, the second line segment D2 is located in the pixel area PQ, the second line segment D2 is electrically connected to the pixel circuit DL in the pixel area PQ, and the second line segment D2 is illustrated as a black solid dot in the figure and is electrically connected to the pixel circuit DL; wherein the content of the first and second substances,
the pixel row PH comprises a first pixel row PH1 and a second pixel row PH2 which are adjacent to each other, the first pixel row PH1 comprises N sub-pixels, the second pixel row PH2 comprises M sub-pixels, N and M are positive integers, and N is not more than M; the total number of the first line segments D1 of the ZQ1 in the plurality of first routing regions between the first pixel row PH1 and the second pixel row PH2 is less than N. According to the shape of the first display area, the number of sub-pixels in two adjacent pixel rows in the first display area may be the same or different. In the embodiment of the present invention, when the number of sub-pixels in the first pixel row PH1 is equal to the number of sub-pixels in the second pixel row PH2, the total number of the first segments D1 between two pixel rows is smaller than the number of sub-pixels in one pixel row; when the number of sub-pixels in the first pixel row PH1 is less than the number of sub-pixels in the second pixel row PH2, the total number of the first segments D1 between two pixel rows is less than the number of sub-pixels in the first pixel row PH 1. The entire first pixel row PH1 and the entire second pixel row PH2 in the first display area AA1 are not shown in fig. 3. Only at the local position illustrated in the figure, the local region illustrates 12 sub-pixels sp in the first pixel row PH1 and 12 sub-pixels sp in the second pixel row PH2, and there are 8 first line segments D1 between the first pixel row PH1 and the second pixel row PH2 in the local region, that is, the design in the embodiment of the present application reduces the number of the first line segments D1 between two adjacent pixel rows.
In one embodiment, the signal line X is a positive power supply signal line that supplies a constant voltage signal to the pixel circuit when driving the sub-pixels for display. The first display region further includes data lines extending in the same direction as the signal lines X, and when the sub-pixels are driven to display, the data lines provide data signals to the pixel circuits, and the data lines are further included in the ZQ1 in the first routing region, which is not shown in the figure.
In another embodiment, the signal line X is a reset signal line which supplies a constant reset signal to the pixel circuit when the sub-pixel is driven to perform display. The first display region further includes a gate scanning line and a light emission control signal line in the same direction as the signal line X, and the first routing region ZQ1 further includes a gate scanning line and a light emission control signal line, which are not shown in the drawing.
Fig. 4 is a partial schematic view of a display panel in the related art. As shown in fig. 4, a signal line X 'extending in the second direction y and a pixel row PH' extending in the first direction X are illustrated, the pixel row PH 'including a plurality of sub-pixels sp' arranged in the first direction X and a pixel circuit DL 'electrically connected to the sub-pixels sp'. It is a conventional design of those skilled in the art that a plurality of pixel circuits DL 'arranged in the second direction y are electrically connected to the same signal line X'. The signal line X ' includes a first line segment D1 ' and a second line segment D2 '. The second line segment D2 'is electrically connected to the pixel circuit DL', and the first line segment D1 'is located between two adjacent pixel rows PH'. In the local region illustrated in the figure, two adjacent pixels and a region each including 12 sub-pixels sp 'include 12 first line segments D1' between corresponding two pixel rows.
When applied to a display panel in which the display regions include a first display region and a second display region (i.e., a scheme of an off-screen optical device), as illustrated in the embodiments of the present application, a design scheme that is easily conceived by those skilled in the art is to still adopt the design scheme as shown in fig. 4 above in the first display region in which the sub-pixel density is small, without creative efforts. The inventor of the present application improves the design in the related art through creative work, and the design reduces the number of signal lines (i.e., the first line segments in the present application) between two adjacent pixel rows. This application embodiment can reduce the area of non-printing opacity district in the first display area, the area of the printing opacity district (being the region that light can pierce through) of the first display area of increase that also can be corresponding (when understanding, printing opacity district and non-printing opacity district are two relative concepts, the luminousness of printing opacity district is greater than the luminousness of non-printing opacity district), thereby promote the luminousness of first display area, use in the scheme of optical device under the screen, can increase optical device's the received light volume under the screen, optical device's optical property is promoted. In addition, when light penetrates through the first display area, various routing lines arranged in the first display area can form a diffraction grating, and a diffraction effect can be generated on the light, for example, when the optical device under the screen is a camera, the imaging quality of the camera can be influenced by the diffraction phenomenon. The embodiment of the application can also improve the diffraction phenomenon when light penetrates through the first display area to a certain extent by reducing the number of signal lines between two adjacent pixel rows, thereby further improving the optical performance of the optical device.
In the first display area of the display panel provided by the embodiment of the application, the area of the light-transmitting area of the first display area can be increased by reducing the number of the first line segments between the two adjacent pixel areas, and meanwhile, the diffraction phenomenon generated by light penetrating through the first display area can be improved. After the number of the first line segments (the partial line segments of the signal lines) in the first routing region is reduced, as illustrated in fig. 3, the second line segment D2 in the pixel region PQ is electrically connected to the same first line segment D1, so that a signal is input to the second line segment D2 to drive the corresponding sub-pixels to perform display, thereby ensuring that each sub-pixel in the first display region can perform normal display. The following examples will illustrate the technical solutions provided in the present application in detail.
In some optional embodiments, the plurality of first routing regions between the first pixel row and the second pixel row comprises: a first wiring area; in the first pixel row and the second pixel row, comprising: the first pixel area is adjacent to the first wiring area and comprises n second line segments; the first routing area comprises p first line segments, p is an integer, and n > p is more than or equal to 0. That is, the number of first line segments in the first routing area adjacent to the first pixel area is smaller than the number of second line segments in the first pixel area. The first pixel region may be located in the first pixel row, or may also be located in the second pixel row, or may also include the first pixel region in both the first pixel row and the second pixel row, and when p is equal to 0, that is, the first line segment is not disposed in the first routing line region. The number of the first line segments in the first wiring area adjacent to the pixel area is smaller than the number of the second line segments in the pixel area, namely the number of the sub-pixels in the pixel area, so that the number of the first line segments between two adjacent pixel rows is reduced, the area of the light-transmitting area of the first display area is increased, and the diffraction phenomenon caused by light penetrating through the first display area is improved.
In one embodiment, one pixel region includes 1 subpixel and 1 pixel circuit, that is, n is 1, and a plurality of first routing regions in the first display region include a first routing region in which a first line segment is not disposed, that is, p is 0. Fig. 5 is a partial schematic view of an alternative implementation manner of a first display area of a display panel according to an embodiment of the present application. As shown in fig. 5, one pixel region PQ includes 1 sub-pixel sp and 1 pixel circuit DL, and 1 second segment D2 is included in the pixel region PQ. The figure illustrates a first trace ZX in the first display area, the extending direction of which is the same as that of the signal line X, wherein, when the signal line X is a positive power line, the first trace ZX is a data line; when the signal line X is a reset signal line, the first trace ZX is a gate scan line or a light emission control signal line. In the figure, the signal line X is a thick line, and the first trace ZX is a thin line, which is only for distinguishing the two lines and is not used as a limitation to the line width in the actual product. The first routing area ZQ1 extending in the second direction y includes a first routing area ZQ1a, the first routing area ZQ1 is not provided with a first line segment D1, the first pixel area PQa adjacent to the first routing area ZQ1a includes 1 second line segment D2, that is, at least a part of the signal lines X is cut off at the position of the first routing area ZQ1a, the number of the signal lines X (i.e., the first line segments D1) between two adjacent pixel rows is reduced, the area of the light-transmitting area of the first display area can be increased, and the diffraction phenomenon generated when light penetrates through the first display area is improved.
In the embodiment shown in fig. 5, the signal line X for supplying signals to the pixel circuits in the first pixel region PQa is turned off at the position of the first line-a-travel region ZQ1a, and then, in the display phase, signals are input to the second line segment D2 in the first pixel region PQa. The present application further proposes a solution to ensure that the sub-pixels in the a-pixel region PQa can still normally display. With continued reference to fig. 5, the routing region further includes a plurality of second routing regions ZQ2, one second routing region ZQ2 being located between two pixel regions PQ adjacent in the first direction x; the first display area further includes a plurality of auxiliary signal lines FX extending in the first direction x, and a partial line segment of the auxiliary signal lines FX is located in the second routing area ZQ 2. The pixel row PH further includes: a second pixel region PQb adjacent to the first pixel region PQa, and the first pixel region PQa and the second pixel region PQb are located in the same pixel row PH; the second line segment D2 located in the a pixel region PQa and the b pixel region PQb, respectively, is electrically connected through the auxiliary signal line FX. Two second line segments D2 are indicated by solid black dots in the figure as being electrically connected by the auxiliary signal line FX. The extending direction of the auxiliary signal line FX and the extending direction of the signal line X cross each other, and the auxiliary signal line FX and the signal line X are electrically connected at a position where they overlap (i.e., with the second segment D2 defined in this application), so that the auxiliary signal line FX and the signal line X transmit the same voltage signal. The auxiliary signal line FX is connected in parallel to the signal line X, and the overall resistance can be reduced, thereby reducing power loss. Meanwhile, when the sub-pixels are driven to display, the auxiliary signal line FX can input a voltage signal to the second line segment D2 in the a-pixel region PQa, so that the sub-pixels in the a-pixel region PQa can normally display.
In some optional embodiments, p ≠ 0, and at least two second line segments in the first pixel region are electrically connected to the same first line segment in the first routing region. When the number of the sub-pixels in the pixel area is greater than or equal to 2, two or more second line segments need to be arranged in the pixel area. At least two second line segments in the A pixel region are electrically connected with the same first line segment, so that the number of the first line segments arranged between two adjacent pixel rows can be reduced.
In one embodiment, n is 3, that is, the first pixel region includes 3 second line segments, and 2 second line segments in the first pixel region are electrically connected to the same first line segment in the first wiring region, and then 2 first line segments are included in the first wiring region adjacent to the first pixel region, that is, p is 2.
Specifically, taking fig. 6 as an example, fig. 6 is a partial schematic view of an alternative implementation manner of the first display region of the display panel provided in the embodiment of the present application. As shown in fig. 6, the a pixel region PQa includes 3 second line segments D2, that is, n is 3, two adjacent pixel rows (i.e., the first pixel row and the second pixel row) in the figure each include an a pixel region PQa, and only the pixel circuits DL are illustrated in the pixel region for clarity of various routing lines in the diagram. The 2 second line segments D2 in the first pixel region are electrically connected with the same first line segment D1 in the first line region ZQ1a, the other second line segment D2 in the first pixel region PQa is electrically connected with the other first line segment D1 in the first line region ZQ1a, and the first line region ZQ1a includes 2 first line segments. The figure shows the first routing lines ZX in the first display area, which have the same extending direction as the signal lines X, and the number of the first routing lines ZX in one pixel area is the same as the number of the sub-pixels in the pixel area, corresponding to the embodiment, one pixel area includes 3 first routing lines ZX. In this embodiment, two second line segments in the first pixel region are arranged to connect the same first line segment, so that the number of the first line segments in the first wiring region adjacent to the first pixel region is reduced, that is, the area of the non-display region of the first display region is also reduced, the area of the light-transmitting region of the first display region is correspondingly increased, and meanwhile, the number of the first line segments in the first wiring region is reduced, which is also beneficial to improving the diffraction phenomenon generated when light penetrates through the first display region.
The partial area of the first display area illustrated in fig. 6 includes a conventional pixel area and a conventional first routing area, where the number of the second line segments in the conventional pixel area, that is, the pixel area, is the same as the number of the first line segments in the corresponding conventional first routing area, that is, only a part of the number of the first line segments in the first routing area is reduced. Optionally, in an embodiment, all the pixel areas in the first display area may be first pixel areas, and all the first routing areas are first routing areas, which is not illustrated in the drawings.
In one embodiment, n is 3, that is, the first pixel region includes 3 second line segments, and 3 second line segments in the first pixel region are electrically connected to the same first line segment in the first wiring region, and then 1 first line segment is included in the first wiring region adjacent to the first pixel region, that is, p is 1.
Specifically, taking fig. 7 as an example, fig. 7 is a partial schematic view of another alternative implementation of the first display region of the display panel provided in this application embodiment. As shown in fig. 7, the a pixel region PQa includes 3 second line segments D2, i.e., n is 3, which is the same as the embodiment corresponding to fig. 6, and the first trace ZX in the first display region is shown in the same extending direction as the signal line X. The 3 second line segments D2 in the first pixel region are electrically connected to the same first line segment D1 in the first line region ZQ1a, and the first line region ZQ1a includes 1 first line segment D1. In this embodiment, 3 second line segments in the first pixel region are arranged to connect the same first line segment, so that the number of first line segments in the first wiring region adjacent to the first pixel region is reduced, that is, the area of the non-display region of the first display region is also reduced, the area of the light-transmitting region of the first display region is correspondingly increased, and meanwhile, the number of first line segments in the first wiring region is reduced, which is also beneficial to improving the diffraction phenomenon generated by light penetrating through the first display region.
The partial area of the first display area illustrated in fig. 7 includes a conventional pixel area and a conventional first routing area, where the number of the second line segments in the conventional pixel area, that is, the pixel area, is the same as the number of the first line segments in the corresponding conventional first routing area, that is, only a part of the number of the first line segments in the first routing area is reduced. Optionally, in an embodiment, all the pixel areas in the first display area may be first pixel areas, and all the first routing areas are first routing areas, which is not illustrated in the drawings.
Furthermore, the pixel region further comprises a connecting line, and the connecting line comprises a first connecting line; the first connecting line is located the first pixel district, and two at least second line sections in the first pixel district are connected with first connecting line electricity through the via hole respectively, and with this two at least same first line sections that second line section electricity is connected, through the via hole with first connecting line electricity. Therefore, at least two second line segments in the A pixel region are electrically connected with the same first line segment. Reference may be made to fig. 6 or fig. 7 as described above. As shown in fig. 6, the connection lines include a first connection line L1, the first connection line L1 is located in the a-pixel region PQa, two second line segments D2 in the a-pixel region PQa are electrically connected to the first connection line L1 through vias, respectively, and the same first line segment D1 electrically connected to the two second line segments D2 is electrically connected to the first connection line L1 through vias, where the vias are illustrated as black and solid dots. As shown in fig. 7, the connection lines include a first connection line L1, the first connection line L1 is located in the a-pixel region PQa, 3 second line segments D2 in the a-pixel region PQa are electrically connected to the first connection line L1 through vias, respectively, and the same first line segment D1 electrically connected to the 3 second line segments D2 is electrically connected to the first connection line L1 through vias, where the vias are illustrated as black solid dots. Through the setting of first connecting wire, realize two at least second line sections and same first line section electricity in the first pixel district and be connected, and then reduced the number of setting up of the first line section in the first walking line district adjacent with first pixel district.
In some embodiments, 4 sub-pixels sp and 4 pixel circuits are included in one pixel region. Optionally, 4 second line segments in the first pixel area are all electrically connected to the same first line segment in the first wiring area, and only 1 first line segment needs to be set in the first wiring area. Optionally, 3 second line segments in the first pixel region are electrically connected to the same first line segment in the first wiring region, and then 2 first line segments may be disposed in the first wiring region. Optionally, 2 second line segments in the first pixel region are electrically connected to the same first line segment in the first wiring region, and then 2 first line segments may be disposed in the first wiring region. In the above embodiment, the principle of the connection between the second line segment in the first pixel region and the first line segment in the first routing region is the same as that in fig. 6 or fig. 7, which can be understood with reference to the above embodiment and will not be described herein again.
In some alternative embodiments, p ═ 0; that is, the first line segment is not provided in the first wiring region adjacent to the first pixel region. It is still illustrated that one pixel region includes 3 sub-pixels and 3 pixel circuits, that is, n is 3. Fig. 8 is a partial schematic view of another alternative implementation of the first display area of the display panel according to the embodiment of the present application. As shown in fig. 8, the pixel region PQ further includes connection lines including a second connection line L2, the second connection line L2 is located in the a-pixel region PQa, and all of the 3 second line segments D2 in the a-pixel region PQa are electrically connected to the second connection line L2. In the arrangement of this embodiment, the first line segment is not arranged in the first routing area adjacent to the first pixel area, so that the number of the first line segments (i.e., signal lines) in the two adjacent pixel areas can be reduced to a greater extent.
Further, in this embodiment, the first line segment is not provided in the first routing area adjacent to the first pixel, and a voltage signal may be input to the second line segment in the first pixel area through the auxiliary signal line in the display panel, so that the second line segment can supply the voltage signal to the pixel circuit to drive the sub-pixel to perform display when displaying. With continued reference to fig. 8, the routing region further includes a plurality of second routing regions ZQ2, one second routing region ZQ2 being located between two pixel regions PQ adjacent in the first direction x; the first display area further includes a plurality of auxiliary signal lines FX extending in the first direction x, and a partial line segment of the auxiliary signal lines FX is located in the second routing area ZQ 2; the pixel structure further includes, in the first pixel row and the second pixel row (not shown in the figure, that is, two adjacent pixel rows): a b pixel region PQb adjacent to the a pixel region PQa, and the a pixel region PQa and the b pixel region PQb are located in the same pixel row; the second line segment D2 located at the a pixel region PQa and the b pixel region PQab, respectively, is electrically connected through the auxiliary signal line FX. The extending direction of the auxiliary signal line FX and the extending direction of the signal line X cross each other, the auxiliary signal line FX is electrically connected to the second line segment D2 at a position where the auxiliary signal line FX and the signal line X overlap, that is, at a position where the auxiliary signal line FX and the second line segment D2 overlap, and a voltage signal is transmitted to the second line segment D2 through the auxiliary signal line FX in a process of driving the display panel to display, so that normal display of the sub-pixels in the first pixel region can be realized. Meanwhile, the auxiliary signal line FX is equivalently connected in parallel with the signal line X, so that the overall resistance can be reduced, and the power loss can be reduced.
In some optional embodiments, the plurality of first routing regions between the first pixel row and the second pixel row comprises: a first second routing area adjacent to the first routing area; further included in the first pixel row and the second pixel row are: the second pixel area is adjacent to the first pixel area, and the second pixel area is adjacent to the first second wiring area; the second pixel area comprises n second line segments, the first second wiring area comprises q first line segments, q is an integer, and n is more than or equal to q and is more than p. When q is equal to n, the number of the first line segments in the first second wiring area is the same as that of the second line segments in the second pixel area, namely, the number of the first line segments in the first second wiring area is not reduced. When n is greater than q, the number of the first line segments in the first second wiring area is smaller than the number of the second line segments in the second pixel area, namely, the area of the non-light-transmitting area in the first display area is further reduced by reducing the number of the first line segments in the first second wiring area, so that the area of the light-transmitting area in the first display area can be correspondingly increased. Meanwhile, the diffraction phenomenon generated by the light transmitting first display area can be further improved.
In one embodiment, q ═ n; and the n second line segments in the pixel area B are correspondingly and electrically connected with the q first line segments in the first wiring area B respectively. It is still illustrated that one pixel region includes 3 sub-pixels and 3 pixel circuits, that is, n is 3. As illustrated with continued reference to fig. 6, 3 second line segments are included in the b pixel region PQb adjacent to the a pixel region PQa, and 3 first line segments are included in the first b routing region ZQ1b adjacent to the b pixel region PQb, i.e., q ═ n. Referring also to the illustration in fig. 7 described above, 3 second line segments are included in the b pixel region PQb adjacent to the a pixel region PQa, and 3 first line segments are included in the first b routing region ZQ1b adjacent to the b pixel region PQb, that is, q ═ n. In the embodiment, the area of the non-light-transmitting area of the first display area is reduced by reducing the number of the first line segments in the partial first wiring area in the first display area, the area of the light-transmitting area of the first display area is correspondingly increased, and the light receiving capacity of the optical device under the screen can be improved when the scheme is applied to the optical device under the screen. Meanwhile, the number of the first line segments is reduced, and the diffraction phenomenon generated when light penetrates through the first display area can be improved to a certain extent.
In one embodiment, q < n; at least two second line segments in the second pixel area are electrically connected with the same first line segment in the first second wiring area. It is still illustrated that one pixel region includes 3 sub-pixels and 3 pixel circuits, that is, n is 3. Fig. 9 is a partial schematic view of another alternative implementation manner of the first display area of the display panel provided in this application example. As shown in fig. 9, 3 second line segments D2 in the a-pixel region PQa are electrically connected to the same first line segment D1 in the first a-wiring region ZQ1a, and the first a-wiring region ZQ1a includes 1 first line segment D1. Two second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second routing region ZQ1b, another second line segment D2 in the second pixel region PQb is electrically connected to another first line segment D1 in the first second routing region ZQ1b, and the first second routing region ZQ1b includes 2 first line segments D1. In the embodiment, the number of the first line segments in the first wiring areas corresponding to the two adjacent pixel areas is reduced, so that the area of the non-light-transmitting area in the first display area is reduced, and the area of the light-transmitting area in the first display area is correspondingly increased. Meanwhile, the diffraction phenomenon generated when light penetrates through the first display area can be improved.
Fig. 9 shows that the arrangement of the second line segment in the second pixel area and the first line segment in the first second routing area is different from the arrangement of the second line segment in the first pixel area and the first line segment in the first routing area. Optionally, 3 second line segments D2 in the a pixel region PQa may be electrically connected to the same first line segment D1 in the first a route region ZQ1a, and the first a route region ZQ1a includes 1 first line segment D1. Meanwhile, 3 second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second wiring region ZQ1b, and the first second wiring region ZQ1b includes 1 first line segment D1.
Further, as can be seen with continued reference to fig. 9, the pixel region further includes a connection line, which includes a third connection line L3; the third connecting line L3 is located in the second pixel region PQb, at least two second line segments D2 in the second pixel region PQb are electrically connected with the third connecting line L3 through via holes respectively, and the same first line segment D21 electrically connected with the at least two second line segments D2 is electrically connected with the third connecting line L3 through via holes, only the via holes are indicated with black solid dots in the drawing for connection, through the arrangement of the third connecting line, at least two second line segments in the second pixel region are electrically connected with the same first line segment, in the display region, it is ensured that signals can be normally provided for the second line segments, and further, it is ensured that each sub-pixel in the second pixel region can normally display.
Further, on the basis of the above embodiment corresponding to fig. 6, an auxiliary signal line may be disposed in the first display region. Fig. 10 is a partial schematic view of another alternative implementation of the first display area provided in an example of the present application. As shown in fig. 10, the routing region further includes a plurality of second routing regions ZQ2, one second routing region ZQ2 being located between two pixel regions PQ adjacent in the first direction x; the first display area further includes a plurality of auxiliary signal lines FX extending in the first direction x, and a partial line segment of the auxiliary signal lines FX is located in the second routing area ZQ 2; the first pixel region PQa and the second pixel region PQb are located in the same pixel row, and the second line segment D2 located in the first pixel PQa and the second pixel region PQb are electrically connected by the auxiliary signal line FX. The extending direction of the auxiliary signal line FX and the extending direction of the signal line X cross each other, the auxiliary signal line FX is electrically connected to the second line segment D2 at a position where the auxiliary signal line FX and the signal line X overlap, that is, at a position where the auxiliary signal line FX and the second line segment D2 overlap, and the auxiliary signal line FX is equivalently connected in parallel to the signal line X, so that the overall resistance can be reduced, and the power loss can be reduced.
In one embodiment, q is 1 and p is 0. Namely, two first routing areas corresponding to two adjacent pixel areas respectively: one first wiring area is provided with a first line segment, and the other first wiring area is not provided with the first line segment. Still take the case where one pixel region includes 3 sub-pixels and 3 pixel circuits, that is, n-3 as an example. Fig. 11 is a partial schematic view of another alternative implementation of the first display area provided in an embodiment of the present application. As shown in fig. 11, 3 second line segments D2 in the first pixel region PQa are electrically connected by second connection lines L2, and the first connection lines D1 are not provided in the first wiring region. In the b pixel region adjacent to the a pixel region PQa: the 3 second line segments D2 are electrically connected to the same 1 first line segment D21 through a third connecting line L3, and 1 first line segment D21 is disposed in the first second routing area. The first line segments which are more than 80% can be reduced in two adjacent first routing areas, the area of the non-light-transmitting area in the first display area can be reduced to a large extent, and the area of the light-transmitting area is correspondingly increased. Meanwhile, the diffraction phenomenon generated when light penetrates through the first display area can be effectively improved.
In the display panel provided by the embodiment of the application, the display area further comprises a plurality of scanning lines and a plurality of data lines; the pixel circuit further includes a pixel capacitance. The display panel comprises a substrate base plate, a first metal layer, a capacitor metal layer and a second metal layer, wherein the first metal layer, the capacitor metal layer and the second metal layer are positioned on the substrate base plate, a scanning line is positioned on the first metal layer, one polar plate of a pixel capacitor is positioned on the capacitor metal layer, and a data line is positioned on the second metal layer. The signal line can be an anode power line or a reset signal line, and the positions of the signal lines on the film layers of the panel are different under different conditions. When the connecting lines (i.e. the first connecting lines, the second connecting lines, and the third connecting lines in the above embodiments) are disposed, the positions of the film layers where the connecting lines are disposed are also required to be correspondingly disposed.
In an embodiment, the signal line is a positive power line, the signal line is located in the second metal layer, and the connection line is located in the first metal layer, as an example, fig. 12 is a partial schematic view of another optional implementation manner of the first display region of the display panel provided in this embodiment of the present application, as shown in fig. 12, 3 pixel circuits in one pixel region are illustrated, and 3 second line segments D2 in the pixel region are electrically connected through the connection line L as an example. The scanning lines S are located in the first metal layer M1, wherein the scanning lines include gate scanning lines and light-emitting control signal lines, which are shown and distinguished; one polar plate C of the pixel capacitor is positioned on the capacitor metal layer MC; the data lines D are located in the second metal layer M2, and a reset signal line Ref is also illustrated, which extends in the first direction x and is located in the capacitor metal layer MC. The signal line X (i.e., the second segment D2) is located in the second metal layer M2, the connection line L is located in the first metal layer M1, and the second segment D2 is electrically connected to the connection line L through the via O1. The connection line L is electrically connected to the second segments D2 arranged in the first direction x, and the connection line L extends in the first direction x. The connection line L is disposed in the first metal layer M1, and the connection line L is disposed to electrically connect at least two second line segments D2 in the pixel region, and the connection line L does not cause a short circuit between the connection line L and the data line D extending in the second direction y.
In another embodiment, the connecting line L may also be located on the capacitor metal layer MC; it can also be ensured that the connecting lines L extending in the first direction x are not short-circuited with the data lines D extending in the second direction y.
Furthermore, the signal line is a positive power line, and when the signal line is located on the second metal layer, the first display area is further provided with an auxiliary signal line, and the auxiliary signal line is located on the capacitor metal layer. Fig. 13 is a partial schematic view of another alternative embodiment of the first display area of the display panel according to the embodiment of the present application, and as shown in fig. 13, 3 pixel circuits in one pixel area are illustrated, an auxiliary signal line FX is electrically connected to the signal line X through the second via O2, and the auxiliary signal line FX is located in the capacitor metal layer MC. The extending direction of the auxiliary signal line FX and the extending direction of the signal line X are intersected with each other, the capacitor metal layer MC is usually used for setting one plate of the pixel capacitor and the reset signal line Ref, and the auxiliary signal line FX is set on the capacitor metal layer MC, which does not affect the original routing arrangement in the display panel. Meanwhile, the auxiliary signal line FX and the signal line X form a parallel circuit structure, so that resistance is reduced, and power loss is reduced. In addition, in the embodiment that the first line segment is not disposed in the corresponding first routing area adjacent to the first pixel area, the auxiliary signal line FX can be electrically connected to the corresponding second line segment in the first pixel area, and in the display area, a voltage signal is provided to the second line segment, so that each sub-pixel in the first pixel area can be normally displayed.
In another embodiment, the signal line is a reset signal line, the signal line is located on the capacitor metal layer, and the connection line is located on the second metal layer. In this embodiment, when connecting at least two second line segments in the same pixel region, the connecting line overlaps with the scan line in the pixel region, and through reasonable design, the connecting line is disposed on the second metal layer, thereby avoiding short circuit between the connecting line and the scan line.
In the embodiment where the signal line is a reset signal line and the signal line is located in the capacitor metal layer, further, an auxiliary signal line may be provided in the display panel and the auxiliary signal line may be provided in the second metal layer. The auxiliary signal line is electrically connected with the signal line through the via hole. The extension direction of the auxiliary signal line and the extension direction of the signal line are mutually crossed, and the auxiliary signal line and the signal line can form a parallel circuit structure, so that the resistance is favorably reduced, and the power loss is further reduced. In addition, in the corresponding implementation mode that the first line segment is not arranged in the first wiring area adjacent to the first pixel area, the auxiliary signal line can be electrically connected with the corresponding second line segment in the first pixel area, and in the display area, the voltage signal is provided for the second line segment, so that the normal display of each sub-pixel in the first pixel area is ensured.
Further, the first display region in the display panel provided in this embodiment of the present application further includes a light shielding layer, fig. 14 is a schematic diagram of another optional implementation manner of the first display region of the display panel provided in this embodiment of the present application, as shown in fig. 14, in a direction perpendicular to the display panel, the light shielding layer covers a routing region (not labeled in the drawing), a second routing region is actually included between two adjacent pixel regions PQ in the first direction x, and a first routing region is included between two adjacent pixel regions PQ in the second direction y. The illustrated light-shielding layer includes a first light-shielding layer SD1 covering the first wiring region and a second light-shielding layer SD2 covering the second wiring region. When the scheme is applied to the optical device under the screen, gaps are formed among the wires in the wire routing area, and when light penetrates through the first display area, the wire routing gaps can perform a light diffraction effect to influence the optical performance of the optical device. The light shield layer that this application embodiment set up can shelter from the region of walking the line to can improve the diffraction effect when light pierces through first display area, promote optical device's optical property. In addition, in the embodiment of the application, the total number of the first line segments between two adjacent pixel rows is reduced, so that the area of at least part of the first wiring area is reduced, and when the light shielding layer is arranged, the area of the light shielding layer can be correspondingly reduced, so that the area of the light transmitting area of the first display area can be correspondingly increased, and the light quantity received by the optical device can be increased when the light shielding layer is applied to the scheme of the optical device under the screen.
In one embodiment, only the first light-shielding layer may be disposed to shield the first routing region. In another embodiment, only the second light-shielding layer may be disposed to shield the second routing region.
The display panel provided by the embodiment of the application comprises a substrate base plate, an array layer and a display layer, wherein the array layer is arranged on the substrate base plate, and the display layer is arranged on the array layer. Wherein the pixel circuit is located at the array layer. The light shielding layer may be located on a side of the array layer away from the substrate. Alternatively, the light-shielding layer may be positioned in a display layer including an anode, a light-emitting layer, and a cathode. The shading layer and the anode can be positioned on the same film layer, and the shading layer and the anode can be manufactured in the same etching process during manufacturing. Alternatively, a metal film layer may be added to the display panel film layer structure to separately form the light-shielding layer.
It should be noted that, the display panel provided in any of the embodiments of the present application may apply a scheme for disposing the light shielding layer, and details are not described herein again.
Based on the same inventive concept, the present application further provides a display device, and fig. 15 is a schematic view of the display device provided in the embodiment of the present application, and as shown in fig. 15, the display device includes the display panel 100 provided in any of the embodiments described above. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 15 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A display panel is characterized in that a display area of the display panel comprises a first display area and a second display area, the display area comprises a plurality of sub-pixels, and the density of the plurality of sub-pixels of the first display area is smaller than that of the plurality of sub-pixels of the second display area;
the first display region includes a plurality of routing regions and a plurality of pixel rows extending in a first direction, one of the pixel rows includes a plurality of pixel regions arranged in the first direction, one of the pixel regions includes n sub-pixels and n pixel circuits, n is a positive integer, the sub-pixels are electrically connected to the pixel circuits, the plurality of routing regions includes a plurality of first routing regions, one of the first routing regions is located between two of the pixel regions adjacent in a second direction, and the second direction crosses the first direction;
the first display area further comprises a plurality of signal lines extending along the second direction, when the display panel is driven to display, constant voltage signals are provided for the signal lines, the signal lines comprise a first line segment and a second line segment, the first line segment is located in the first routing area, the second line segment is located in the pixel area, and the second line segment is electrically connected with the pixel circuit in the pixel area; wherein the content of the first and second substances,
the pixel rows comprise a first pixel row and a second pixel row which are adjacent, the first pixel row comprises N sub-pixels, the second pixel row comprises M sub-pixels, N and M are positive integers, and N is less than or equal to M; the total number of the first line segments in the first routing areas between the first pixel row and the second pixel row is less than N;
in a plurality of the first routing regions between the first pixel row and the second pixel row, including: a first wiring area;
in the first pixel row and the second pixel row, comprising: an A pixel region adjacent to the first routing region, the A pixel region including n second line segments; wherein the content of the first and second substances,
the first routing area comprises p first line segments, p is an integer, and n > p is more than or equal to 0;
p＝0；
the pixel region further comprises a connecting line, the connecting line comprises a second connecting line, the second connecting line is located in the A pixel region, and the n second lines in the A pixel region are electrically connected with the second connecting line;
the wiring area further comprises a plurality of second wiring areas, and one second wiring area is positioned between two adjacent pixel areas in the first direction;
the first display area further comprises a plurality of auxiliary signal lines extending along the first direction, and partial line segments of the auxiliary signal lines are located in the second wiring area;
further comprising in the first pixel row and the second pixel row: the second pixel area is adjacent to the first pixel area, and the first pixel area and the second pixel area are positioned in the same pixel row;
the second line segments respectively located in the first pixel region and the second pixel region are electrically connected through the auxiliary signal line.
2. The display panel according to claim 1,
in a plurality of the first routing regions between the first pixel row and the second pixel row, including: a first second routing area adjacent to the first routing area;
further comprising in the first pixel row and the second pixel row: a second pixel region adjacent to the first pixel region, the second pixel region being adjacent to the first second routing line region;
the second pixel area comprises n second line segments, the first second routing area comprises q first line segments, q is an integer, and n is more than or equal to q and is more than p.
3. The display panel according to claim 2,
q＝n；
the n second line segments in the pixel B area are correspondingly and electrically connected with the q first line segments in the first wiring B area respectively.
4. The display panel according to claim 2,
q<n；
and at least two second line segments in the pixel region B are electrically connected with the same first line segment in the first wiring region B.
5. The display panel according to claim 4,
the pixel region further comprises a connecting line, and the connecting line comprises a third connecting line;
the third connecting line is located in the second pixel area, at least two second line segments in the second pixel area are electrically connected with the third connecting line through via holes respectively, and the same first line segment electrically connected with the at least two second line segments is electrically connected with the third connecting line through via holes.
6. The display panel according to any one of claims 5,
the display area also comprises a plurality of scanning lines and a plurality of data lines;
the pixel circuit further comprises a pixel capacitor;
the display panel comprises a substrate, a first metal layer, a capacitor metal layer and a second metal layer, wherein the first metal layer, the capacitor metal layer and the second metal layer are positioned on the substrate; wherein the content of the first and second substances,
the signal line is positioned on the second metal layer, and the connecting line is positioned on the first metal layer or the capacitor metal layer; or;
the signal line is located on the capacitor metal layer, and the connecting line is located on the second metal layer.
7. The display panel according to claim 2,
the wiring area further comprises a plurality of second wiring areas, and one second wiring area is positioned between two adjacent pixel areas in the first direction;
the first display area further comprises a plurality of auxiliary signal lines extending along the first direction, and partial line segments of the auxiliary signal lines are located in the second wiring area;
the first pixel area and the second pixel area are located on the same pixel row, and the second line segments respectively located in the first pixel area and the second pixel area are electrically connected through the auxiliary signal line.
8. The display panel according to claim 7,
the display area also comprises a plurality of scanning lines and a plurality of data lines;
the pixel circuit further comprises a pixel capacitor;
the display panel comprises a substrate, a first metal layer, a capacitor metal layer and a second metal layer, wherein the first metal layer, the capacitor metal layer and the second metal layer are positioned on the substrate; wherein the content of the first and second substances,
the signal line is positioned on the second metal layer, and the auxiliary signal line is positioned on the capacitor metal layer; or, the signal line is located in the capacitance metal layer, and the auxiliary signal line is located in the second metal layer.
9. The display panel according to claim 2,
q＝1，p＝0。
10. the display panel according to claim 1,
the first display area further comprises a light shielding layer, and the light shielding layer covers the wiring area in the direction perpendicular to the display panel.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.
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| CN111314517B (en) * | 2020-03-03 | 2022-03-01 | 惠州Tcl移动通信有限公司 | Display panel and mobile terminal |
| CN111402743A (en) * | 2020-03-24 | 2020-07-10 | 昆山国显光电有限公司 | Display panel and display device |
| WO2021227023A1 (en) * | 2020-05-15 | 2021-11-18 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display apparatus |
| CN117396032A (en) * | 2020-06-04 | 2024-01-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN111681565B (en) * | 2020-06-22 | 2022-03-22 | Oppo广东移动通信有限公司 | Display screen and electronic equipment |
| CN111627339B (en) * | 2020-06-29 | 2022-01-11 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113871418A (en) * | 2020-06-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113161404B (en) * | 2021-04-23 | 2023-04-18 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113539161B (en) * | 2021-06-30 | 2022-05-31 | 武汉天马微电子有限公司 | Display panel and display device |
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| JP5958055B2 (en) * | 2011-07-29 | 2016-07-27 | セイコーエプソン株式会社 | Electro-optical device, driving method of electro-optical device, and electronic apparatus |
| CN203882586U (en) * | 2014-06-13 | 2014-10-15 | 京东方科技集团股份有限公司 | Pixel circuit and display device |
| KR102546985B1 (en) * | 2016-11-21 | 2023-06-27 | 엘지디스플레이 주식회사 | Large Area Ultra High Density Flat Display Having High Aperture Ratio |
| CN108509899B (en) * | 2018-03-29 | 2021-03-09 | 上海天马微电子有限公司 | Display panel and display device |
| CN113707028B (en) * | 2019-06-28 | 2023-04-07 | 武汉天马微电子有限公司 | Display panel and display device |
| CN110767097B (en) * | 2019-11-27 | 2021-12-31 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN114203792A (en) | 2022-03-18 |
| CN114203793A (en) | 2022-03-18 |
| CN110854178B (en) | 2022-01-28 |
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