CN115953968A - Display panel and display device - Google Patents

Abstract

The embodiment of the invention discloses a display panel and a display device. The light transmittance of the first display area of the display panel is greater than that of the second display area. The first sub-pixel in the display panel is located in the first display area, and the second sub-pixel is located in the second display area. The first pixel circuit and the second pixel circuit in the display panel are both located in the second display area, the first pixel circuit is used for driving the first sub-pixel, and the second pixel circuit is used for driving the second sub-pixel. The second display area comprises a first area adjacent to the first display area, the first area is divided into a first sub-area and a second sub-area, at least part of the first pixel circuits are arranged in the first sub-area, and the second pixel circuits corresponding to the second sub-pixels in the first sub-area and the second sub-area are arranged in the second sub-area. The technical scheme of the embodiment of the invention is beneficial to improving the light transmittance of the first display area and simultaneously improving the screen occupation ratio of the display panel so as to realize full-screen display.

Description

Display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.

Background

With the continuous development of display technology, people have higher and higher requirements on the screen ratio of display devices. The screen area ratio refers to the ratio of the screen area of the display device to the whole area. At present, the requirements of functional components such as a camera in a display device are limited, and a certain area needs to be reserved above the display screen to set the components, so that the screen of the display device is low in occupancy ratio, poor in user experience is caused, and the user requirements are difficult to meet.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for improving the light transmittance of a first display area and improving the screen ratio of the display panel, and are beneficial to realizing full-screen display.

In a first aspect, an embodiment of the present invention provides a display panel, where the display panel has a first display area and a second display area, and a light transmittance of the first display area is greater than a light transmittance of the second display area, and the display panel includes:

the sub-pixels comprise first sub-pixels and second sub-pixels, the first sub-pixels are positioned in the first display area, and the second sub-pixels are positioned in the second display area;

the pixel circuit comprises a first pixel circuit and a second pixel circuit, is positioned in the second display area, and is used for driving the first sub-pixel and the second sub-pixel;

the second display area comprises a first area adjacent to the first display area, the first area is divided into a first sub-area and a second sub-area, at least part of the first pixel circuits are arranged in the first sub-area, and the second pixel circuits corresponding to the second sub-pixels in the first sub-area and the second sub-area are arranged in the second sub-area.

Optionally, the display panel has a frame region, and the frame region is located at the periphery of the first display region and the second display region;

the second display area surrounds the first display area, the first display area comprises at least one row of the first sub-pixels, an area from the row of the first sub-pixels closest to the frame area in the first display area is a second area, and the first pixel circuit is located outside the second area;

or the second display area semi-surrounds the first display area, and the first display area is adjacent to the frame area.

Optionally, the display panel further comprises a dummy pixel circuit in the second display area, at least a part of the dummy pixel circuit in the first area being multiplexed into the first pixel circuit and/or the second pixel circuit.

Optionally, at least a portion of the first pixel circuits are located between adjacent second pixel circuits;

preferably, the display panel further includes a dummy pixel circuit located between adjacent second pixel circuits, at least a part of the dummy pixel circuit being multiplexed into the first pixel circuit.

Optionally, the first display area includes a first sub-display area and a second sub-display area, the second display area includes a third sub-display area and a fourth sub-display area, the third sub-display area is adjacent to the first sub-display area, and the fourth sub-display area is adjacent to the second sub-display area;

the first pixel circuit corresponding to the first sub-pixel in the first sub-display area is located in the third sub-display area, and the first pixel circuit corresponding to the sub-pixel in the second sub-display area is located in the fourth sub-display area;

the third sub-display region serves as the first region, and the first pixel circuits in the fourth sub-display region are located between the adjacent second pixel circuits.

Optionally, the first sub-display area includes a fifth sub-display area and a sixth sub-display area, the third sub-display area includes a seventh sub-display area and an eighth sub-display area, the seventh sub-display area is adjacent to the fifth sub-display area, and the eighth sub-display area is adjacent to the sixth sub-display area;

the seventh sub-display area comprises the first sub-area and the second sub-area, the first pixel circuit corresponding to the first sub-pixel in the fifth sub-display area is located in the first sub-area of the seventh sub-display area, and the second pixel circuit corresponding to the second sub-pixel in the seventh sub-display area is located in the second sub-area of the seventh sub-display area;

the eighth sub-display area comprises the first sub-area and the second sub-area, the first pixel circuit corresponding to the first sub-pixel in the sixth sub-display area is located in the first sub-area of the eighth sub-display area, and the second pixel circuit corresponding to the second sub-pixel in the eighth sub-display area is located in the second sub-area of the eighth sub-display area;

preferably, the display panel further comprises a dummy pixel circuit, at least a portion of the dummy pixel circuit in the first sub-region is multiplexed as the first pixel circuit, and at least a portion of the dummy pixel circuit in the second sub-region is multiplexed as the second pixel circuit;

preferably, at least a part of the dummy pixel circuits in the fourth sub-display area are multiplexed as the first pixel circuits;

preferably, the first sub-display area and the second sub-display area are arranged along a first direction, and along the first direction, the fourth sub-display area is located on one side of the second sub-display area, which is far away from the first sub-display area;

the fifth sub-display area and the sixth sub-display area are arranged along a second direction, the seventh sub-display area is located on one side, away from the sixth sub-display area, of the fifth sub-display area along the second direction, the eighth sub-display area is located on one side, away from the fifth sub-display area, of the sixth sub-display area, and the second direction is perpendicular to the first direction.

Optionally, the display panel further includes scan lines and data lines connecting the pixel circuits;

the scanning line connected with the first pixel circuit is positioned outside the first display area; or the scanning line connected with the first pixel circuit passes through the first display area, and the scanning line positioned in the first display area is a transparent metal line;

the data line connected with the first pixel circuit is positioned outside the first display area; or the data line connected with the first pixel circuit penetrates through the first display area, and the data line positioned in the first display area is a transparent metal line.

Optionally, the display panel further comprises scan lines, the scan lines comprising a first scan line;

the plurality of first sub-pixels are arranged in an array in the first display area, the plurality of second sub-pixels are arranged in an array in the second display area, at least part of the second sub-pixels are arranged in the same row as the first sub-pixels, the row direction of the arrangement of the first sub-pixels and the second sub-pixels is a first direction, and the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels which are positioned in the same row are connected with the same first scanning line;

the first scanning line comprises a first routing segment and a second routing segment, and the first routing segment is connected with the second routing segment; the first routing section is connected with the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel which are positioned in the same row in the first display area and the fourth sub-display area, and the second routing section is connected with the second pixel circuit corresponding to the second sub-pixel which is positioned in the same row in an area except the fourth sub-display area in the second display area;

the first routing section is positioned outside the first display area; or the first routing segment passes through the first display area, and the first routing segment in the first display area is a transparent metal wire.

Optionally, the display panel further comprises data lines, wherein the data lines comprise a first data line and a second data line;

the plurality of first sub-pixels are arranged in an array in the first display area, the plurality of second sub-pixels are arranged in an array in the second display area, at least part of the second sub-pixels are arranged in the same column as the first sub-pixels, the column direction in which the first sub-pixels and the second sub-pixels are arranged is a second direction, the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels which are positioned in the same column in the first display area and the second display area are connected with the same first data line, and the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels which are positioned in the same column in the second display area and the second display area are connected with the same second data line;

the first data line comprises a third line segment, a fourth line segment, a fifth line segment, a sixth line segment and a seventh line segment; the third routing segment and the fourth routing segment are connected through the seventh routing segment, and the fifth routing segment and the sixth routing segment are connected through the seventh routing segment; the third routing segment is connected with the first sub-area of the seventh sub-display area and the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel in the same column in the second display area adjacent to the first sub-area of the seventh sub-display area along the second direction; the fifth routing section is connected with the second pixel circuits corresponding to the second sub-pixels in the same column in a second sub-area of the seventh sub-display area; the fourth routing segment is connected with the first sub-area of the eighth sub-display area and the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel in the same column in the second display area adjacent to the first sub-area of the eighth sub-display area along the second direction; the sixth routing segment is connected with the second pixel circuits corresponding to the second sub-pixels in the same column in a second sub-area of the eighth sub-display area;

the seventh routing section is located outside the first display area; or the seventh routing segment passes through the first display area, and the seventh routing segment in the first display area is a transparent metal wire;

the second data line comprises an eighth routing segment, a ninth routing segment and a tenth routing segment, and the eighth routing segment is connected with the ninth routing segment through the tenth routing segment; the eighth routing segment is connected with the second pixel circuits corresponding to the second sub-pixels in the same row in the second display area on one side of the second sub-display area along the second direction; the ninth routing section is connected to the second pixel circuits corresponding to the second sub-pixels in the same column in the second display area on the other side of the second sub-display area along the second direction; the tenth routing section is connected with the first pixel circuits corresponding to the first sub-pixels in the same column in the fourth sub-display area;

the tenth routing section is located outside the first display area; or, the tenth routing segment passes through the first display area, and the tenth routing segment in the first display area is a transparent metal wire.

In a second aspect, an embodiment of the present invention provides a display device, including the display panel described in the first aspect.

According to the display panel and the display device provided by the embodiment of the invention, the first pixel circuit corresponding to the first sub-pixel and the second pixel circuit corresponding to the second sub-pixel are arranged in the second display area, so that the first pixel circuit is not required to be arranged in the first display area, the second display area comprises the first area adjacent to the first display area, at least part of the first pixel circuit corresponding to the first sub-pixel in the first display area is arranged in the first sub-area of the first area, at least part of the first pixel circuit corresponding to the second sub-pixel in the first sub-area and the second pixel circuit corresponding to the second sub-pixel in the second sub-area of the first area are arranged in the second sub-area of the first area, so that the second pixel circuit corresponding to all the second sub-pixels in the area can be arranged in the first area, at least part of the first pixel circuit can be arranged, and the first pixel circuit is not required to be arranged in a transition area between the first display area and the second display area separately, thereby improving the light transmittance of the first display area and realizing the full display panel.

In addition, since the first region is adjacent to the first display region, the distance between the first pixel circuit in the first sub-region and the corresponding first sub-pixel is reduced, so that the length of the connection line between the first pixel circuit and the light emitting device in the corresponding first sub-pixel is reduced, and the difference in length of the connection line between each first pixel circuit and the light emitting device in the corresponding first sub-pixel is reduced.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is an enlarged view of a portion of the area M of FIG. 1;

FIG. 3 is another enlarged partial view of the area M in FIG. 1;

FIG. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present invention;

FIG. 5 is an enlarged view of a portion of the area N of FIG. 1;

FIG. 6 is another enlarged partial view of the area N in FIG. 1;

FIG. 7 is an enlarged view of a portion of the area P in FIG. 1;

FIG. 8 is another enlarged partial view of the area P in FIG. 1;

fig. 9 is another partial enlarged view of the region P in fig. 1.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the invention provides a display panel. Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention; FIG. 2 is an enlarged view of a portion of the area M of FIG. 1; fig. 3 is another partially enlarged view of the region M in fig. 1. Fig. 2 shows an arrangement of sub-pixels of the M region, and fig. 3 shows an arrangement of pixel circuits of the M region.

Referring to fig. 1 to 3, the display panel has a display area AA and a frame area (i.e., a non-display area) NAA, where the display area AA includes a first display area AA1 and a second display area AA2, and a light transmittance of the first display area AA1 is greater than a light transmittance of the second display area AA2.

The display panel comprises sub-pixels and a pixel circuit, wherein the sub-pixels comprise a first sub-pixel 110 and a second sub-pixel 120, the first sub-pixel 110 is located in a first display area AA1, and the second sub-pixel 120 is located in a second display area AA2. The pixel circuit includes a first pixel circuit 210 and a second pixel circuit 220, the first pixel circuit 210 and the second pixel circuit 220 are both located in the second display area AA2, the first pixel circuit 210 is used for driving the first sub-pixel 110, and the second pixel circuit 220 is used for driving the second sub-pixel 120.

The second display area AA2 includes a first area D1 adjacent to the first display area AA1, the first area D1 is divided into a first sub-area D11 and a second sub-area D12, at least a portion of the first pixel circuits 210 is disposed in the first sub-area D11, and the second pixel circuits 220 corresponding to the second sub-pixels 120 in the first sub-area D11 and the second sub-area D12 are disposed in the second sub-area D12.

Specifically, the display panel provided in the embodiment of the present invention may be an Organic Light-Emitting Diode (OLED) display panel, an Active-Matrix Organic Light-Emitting Diode (OLED) display panel, a Micro-LED (Micro-LED) display panel, and the like. The sub-pixels may specifically be constituted by light emitting devices, such as organic light emitting diodes OLED or Micro-LEDs, etc. The pixel circuit may include a switching transistor, a driving transistor, and a storage capacitor, and the driving transistor in the pixel circuit may generate a driving current to drive the corresponding light emitting device to emit light, so that the display panel may implement a display function.

The second display area AA2 may be a normal display area, which is also called a main screen area, the first display area AA1 may be a transparent display area, which is also called a sub-screen area, and a photosensitive element may be disposed in an area of the non-display side of the display panel corresponding to the first display area AA 1. Illustratively, the light sensing element may be an under-screen camera. Under the display mode, first display area AA1 and second display area AA2 all carry out normal luminous demonstration, under the mode of making a video recording, because first display area AA 1's luminousness is higher for light can see through first display area AA1 and incide to camera under the screen, thereby make under the screen camera can the sensitization make a video recording.

The first area D1 in the second display area AA2 is adjacent to the first display area AA1, for example, the first area D1 is located on one side of the first display area AA1 along the second direction Y, and in other embodiments, the first area D1 is located on the other side of the first display area AA1 along the second direction Y, or the first area D1 is located on two sides of the first display area AA1 along the second direction Y, or the first area D1 is located on at least one side of the first display area AA1 along the first direction X. The areas of the first and second sub-regions D11 and D12 may be equal or may not be equal.

According to the technical scheme of the embodiment of the invention, the first pixel circuit corresponding to the first sub-pixel and the second pixel circuit corresponding to the second sub-pixel are arranged in the second display area, so that the first pixel circuit does not need to be arranged in the first display area, the second display area comprises the first area adjacent to the first display area, the first pixel circuit corresponding to at least part of the first sub-pixel in the first display area is arranged in the first sub-area of the first area, the second pixel circuit corresponding to the second sub-pixel in the first sub-area and the second sub-area of the second area is arranged in the second sub-area of the first area, so that the second pixel circuit corresponding to all the second sub-pixels in the first area can be arranged in the first area, at least part of the first pixel circuit can be arranged, the first pixel circuit does not need to be arranged in a transition area between the first display area and the second display area, the light transmittance of the first display area is improved, and the full-screen ratio of the display panel is improved.

In addition, since the first region is adjacent to the first display region, the distance between the first pixel circuit in the first sub-region and the corresponding first sub-pixel is reduced, so that the length of the connection line between the first pixel circuit and the light emitting device in the corresponding first sub-pixel is reduced, and the difference in length of the connection line between each first pixel circuit and the light emitting device in the corresponding first sub-pixel is reduced.

On the basis of the above embodiment, optionally, the frame area NAA is located at the periphery of the first display area AA1 and the second display area AA2, the second display area AA2 surrounds the first display area AA1 by half, and the first display area AA1 is adjacent to the frame area NAA. Specifically, a part of the edge of the first display area AA1 is surrounded by the second display area AA2, and another part of the edge is adjacent to the bezel area NAA. For example, along the second direction Y, two opposite sides of the first display area AA1, and along the first direction X, a side of the first display area AA1 away from the border area NAA is surrounded by the second display area AA2, and a side of the first display area AA1 not surrounded by the second display area AA2 is adjacent to the border area NAA. In this way, the first area D1 in the second display area AA2 may be located on three sides of the first display area AA1 that are not adjacent to the frame area NAA, that is, the first pixel circuit 210 may be disposed on three sides of the first display area AA1 that are not adjacent to the frame area NAA, so that the distance between the first display area AA1 and the frame area NAA is relatively small or not, which is helpful for improving the aesthetic property of the display panel, thereby meeting the user requirement and improving the user experience.

On the basis of the above embodiments, the display panel in the embodiments of the present invention may be a flexible display panel, the display panel has a bending region B for bending at the bending region B, and the first display area AA1 is located at one side of the bending region B. This display panel is collapsible display panel, in collapsible display panel, through setting up one side that first display area AA1 is located buckle area B, second display area AA2 is half encirclement with first display area AA1, and first display area AA1 is adjacent with frame district NAA, can make the distance of first display area AA1 and frame district NAA less or no distance, help promoting collapsible display panel's aesthetic property, thereby satisfy user's demand, promote user experience.

Fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 4, in another embodiment, the second display area AA2 may further surround the first display area AA1, the first display area AA1 includes at least one row of first sub-pixels, an area between a row of first sub-pixels closest to the frame area NAA in the first display area AA1 and the frame area NAA is a second area Q, and the first pixel circuit is located outside the second area Q.

In the prior art, a transition area is usually arranged between the first display area AA1 and the second display area AA2, and the first pixel circuits corresponding to the first sub-pixels in the first display area AA1 are all arranged in the transition area, so that the area of the transition area is relatively large, and the distance between the first display area AA1 and the frame area NAA is relatively long, which results in poor user experience. Compared with the prior art, according to the technical scheme of the embodiment, the first pixel circuit 210 is arranged outside the second region Q, so that the size of the second region Q is not limited by the first pixel circuit 210, and under the condition that the area of the second region Q is smaller, the distance between the first display area AA1 and the frame area NAA is favorably reduced, and the user experience is improved.

FIG. 5 is an enlarged view of a portion of the area N of FIG. 1; fig. 6 is another partially enlarged view of the region N in fig. 1. Fig. 5 shows an arrangement of N-region sub-pixels, and fig. 6 shows an arrangement of N-region pixel circuits.

With reference to fig. 1, 5 and 6, optionally, at least a portion of the first pixel circuits 210 is located between adjacent second pixel circuits 220. By disposing the first pixel circuits 210 using the area between the adjacent second pixel circuits 220, the portion of the first pixel circuits 210 is disposed without occupying additional space in the second display area AA2, and the portion of the first pixel circuits 210 is disposed without separately adding a transition area between the first display area AA1 and the second display area AA2.

Further, the first display area AA1 includes a first sub-display area AA11 and a second sub-display area AA12, and the second display area AA2 includes a third sub-display area AA13 and a fourth sub-display area AA14, where the third sub-display area AA13 is adjacent to the first sub-display area AA11, and the fourth sub-display area AA14 is adjacent to the second sub-display area AA 12. The first pixel circuit 210 corresponding to the first sub-pixel 110 in the first sub-display area AA11 is located in the third sub-display area AA13, and the first pixel circuit 210 corresponding to the sub-pixel in the second sub-display area AA12 is located in the fourth sub-display area AA14. The third sub-display area AA13 serves as the first area D1, and the first pixel circuits 210 in the fourth sub-display area AA14 are located between the adjacent second pixel circuits 220.

Illustratively, the first display area AA1 may be divided into a first sub-display area AA11 and a second sub-display area AA12, and the third sub-display area AA13 and the fourth sub-display area AA14 may be located in different directions adjacent to the first display area AA 1. The third sub-display area AA13 includes a first sub-area D11 and a second sub-area D12, the first pixel circuits 210 corresponding to the first sub-pixels 110 in the first sub-display area AA11 may be disposed in the first sub-area D11 of the third sub-display area AA13, and the second pixel circuits 220 corresponding to the second sub-pixels 120 in the first sub-area D11 and the second sub-area D12 of the third sub-display area AA13 may be disposed in the second sub-area D12 of the third sub-display area AA 13. The fourth sub-display area AA14 includes the second sub-pixels 120 and the corresponding second pixel circuits 220, and the first pixel circuits 210 may be disposed by using an area between the adjacent second pixel circuits 220. In this embodiment, the third sub-display area AA13 may be configured with the second pixel circuits 220 corresponding to all the second sub-pixels 120 in the area, or may be configured with the first pixel circuits 210 corresponding to the first sub-pixels 110 in the first sub-display area AA11, and the fourth sub-display area AA14 may be configured with the second pixel circuits 220 corresponding to all the second sub-pixels 120 in the area, or may be configured with the first pixel circuits 210 corresponding to the first sub-pixels 110 in the second sub-display area AA12, so that the first pixel circuits 210 corresponding to all the first sub-pixels 110 in the first display area AA1 may be respectively configured in the third sub-display area AA13 and the fourth sub-display area AA14, and it is not necessary to separately add a transition area between the first display area AA1 and the second display area AA2 to place the first pixel circuits 210.

Alternatively, the first sub-pixel 110 may be composed of only one sub-pixel, or may also be composed of a plurality of sub-pixels with different colors, fig. 5 schematically illustrates a case where the first sub-pixel 110 is composed of two red sub-pixels R, two green sub-pixels G, and two blue sub-pixels B, in other embodiments, the first sub-pixel 110 may also be configured to include one or more sub-pixels according to the pixel arrangement requirement, which is not limited in this embodiment.

Optionally, the first sub-area D11 of the third sub-display area AA13 includes a plurality of first pixel circuit units 21, the second sub-area D12 of the third sub-display area AA13 includes a plurality of second pixel circuit units 22, and the fourth sub-display area AA14 includes a plurality of third pixel circuit units 23. The first pixel circuit unit 21 includes at least one first pixel circuit 210, the second pixel circuit unit 22 includes at least one second pixel circuit 220, the third pixel circuit unit 23 includes at least one first pixel circuit 210 and includes at least one second pixel circuit 220, and the first pixel circuit 210 is located between two adjacent second pixel circuits 220. Alternatively, an area of the second display area AA2 excluding the third sub-display area AA13 and the fourth sub-display area AA14 includes a plurality of second pixel circuit units 22.

With reference to fig. 1, 5 and 6, further, the first sub-display area AA11 includes a fifth sub-display area AA15 and a sixth sub-display area AA16, the third sub-display area AA13 includes a seventh sub-display area AA17 and an eighth sub-display area AA18, the seventh sub-display area AA17 is adjacent to the fifth sub-display area AA15, and the eighth sub-display area AA18 is adjacent to the sixth sub-display area AA 16.

The seventh sub-display area AA17 includes a first sub-area D11 and a second sub-area D12, the first pixel circuit 210 corresponding to the first sub-pixel 110 in the fifth sub-display area AA15 is located in the first sub-area D11 of the seventh sub-display area AA17, and the second pixel circuit 220 corresponding to each second sub-pixel 120 in the first sub-area D11 and the second sub-area D12 of the seventh sub-display area AA17 is located in the second sub-area D12 of the seventh sub-display area AA 17.

The eighth sub-display area AA18 includes a first sub-area D11 and a second sub-area D12, the first pixel circuit 210 corresponding to the first sub-pixel 110 in the sixth sub-display area AA16 is located in the first sub-area D11 of the eighth sub-display area AA18, and the second pixel circuit 220 corresponding to each second sub-pixel 120 in the first sub-area D11 and the second sub-area D12 of the eighth sub-display area AA18 is located in the second sub-area D12 of the eighth sub-display area AA 18.

With reference to fig. 1, 5 and 6, on the basis of the above embodiments, the display panel optionally further includes dummy pixel circuits 230 located in the second display area AA2, and at least a part of the dummy pixel circuits 230 in the first area D1 are multiplexed into the first pixel circuits 210 and/or the second pixel circuits 220.

The dummy pixel circuit 230 is a dummy pixel circuit, and the structure of the dummy pixel circuit 230 may be the same as the structures of the first pixel circuit 210 and the second pixel circuit 220 to ensure the electrical uniformity of each area of the display panel.

Further, at least a part of the dummy pixel circuits 230 in the first sub-area D11 of the seventh sub-display area AA17 and the eighth sub-display area AA18 are multiplexed as the first pixel circuits 210, and at least a part of the dummy pixel circuits 230 in the second sub-area D12 of the seventh sub-display area AA17 and the eighth sub-display area AA18 are multiplexed as the second pixel circuits 220.

For example, each of the first pixel circuit units 21 in the first sub-region D11 of the seventh and eighth sub-display areas AA17 and AA18 may include four first pixel circuits 210 and two dummy pixel circuits 230, and the dummy pixel circuits 230 in the first pixel circuit units 21 may be multiplexed as the first pixel circuits 210 to drive the corresponding first sub-pixels 110 in the fifth sub-display area AA15 through the dummy pixel circuits 230. Each of the second pixel circuit units 22 in the second sub-area D12 of the seventh and eighth sub-display areas AA17 and AA18 may include four second pixel circuits 220 and two dummy pixel circuits 230, and the dummy pixel circuits 230 in the second pixel circuit units 22 of the second sub-area D12 may be multiplexed into the second pixel circuit unit 22. The first pixel circuit 210 and the second pixel circuit 220 in the fifth sub-display area AA15, the sixth sub-display area AA16, the seventh sub-display area AA17 and the eighth sub-display area AA18 are disposed without additionally occupying the space outside the seventh sub-display area AA17 and the eighth sub-display area AA18 by multiplexing the dummy pixel circuit 230 in the first sub-area D11 of the seventh sub-display area AA17 and the eighth sub-display area AA18 as the first pixel circuit 210 and multiplexing the dummy pixel circuit 230 in the second sub-area D12 as the second pixel circuit 220.

With reference to fig. 1, 5 and 6, on the basis of the foregoing embodiments, the display panel optionally further includes dummy pixel circuits 230 located between the adjacent second pixel circuits 220, and at least a part of the dummy pixel circuits 230 located between the adjacent second pixel circuits 220 are multiplexed into the first pixel circuit 210. Further, at least a part of the dummy pixel circuits 230 in the fourth sub-display area AA14 is multiplexed as the first pixel circuits 210. Each of the third pixel circuit units 23 in the fourth sub-display area AA14 may include four second pixel circuits 220 and two dummy pixel circuits 230, and the dummy pixel circuits 230 in the third pixel circuit units 23 may be multiplexed as the first pixel circuits 210 to drive the first sub-pixels 110 in the second sub-display area AA 12.

With reference to fig. 1, fig. 5 and fig. 6, on the basis of the foregoing embodiments, optionally, the first sub-display area AA11 and the second sub-display area AA12 are arranged along the first direction X, and along the first direction X, the fourth sub-display area AA14 is located on a side of the second sub-display area AA12 away from the first sub-display area AA 11. The fifth sub-display area AA15 and the sixth sub-display area AA16 are arranged along the second direction Y, and along the second direction Y, the seventh sub-display area AA17 is located on a side of the fifth sub-display area AA15 away from the sixth sub-display area AA16, the eighth sub-display area AA18 is located on a side of the sixth sub-display area AA16 away from the fifth sub-display area AA15, and the second direction Y is perpendicular to the first direction X.

For example, in a case where the second display area AA2 semi-surrounds the first display area AA1 and the first display area AA1 is adjacent to the border area NAA, the first sub-display area AA11 may be disposed adjacent to the border area NAA, and the second sub-display area AA12 is located on a side of the first sub-display area AA11 away from the border area NAA along the first direction X. In this way, the first pixel circuit 210 corresponding to each first sub-pixel 110 in the first display area AA1 is respectively disposed in the fourth sub-display area AA14, the seventh sub-display area AA17, and the eighth sub-display area AA18, the fourth sub-display area AA14, the seventh sub-display area AA17, and the eighth sub-display area AA18 are all adjacent to the first display area AA1, and the fourth sub-display area AA14, the seventh sub-display area AA17, and the eighth sub-display area AA18 are respectively disposed in three directions of the first display area AA1, along the first direction X, the fourth sub-display area AA14 is located on a side of the first display area AA1 away from the bezel area NAA, along the second direction Y, the seventh sub-display area AA17, and the eighth sub-display area AA18 are respectively disposed on two sides of the first display area AA1, the first display area AA1 is adjacent to the bezel area a, and no pixel circuit is disposed between the first display area AA1 and the bezel area a, so that the first sub-display area AA17, and the eighth sub-display area AA18 are disposed on two sides of the first display area AA1 AA, which is adjacent to the bezel area AA, thereby enabling a distance between the first display area AA1 to be increased, which is not necessary for a user to be favorable for a user to experience.

With reference to fig. 1, fig. 5 and fig. 6, on the basis of the above embodiments, a plurality of first sub-pixels 110 may be arranged in an array in the first display area AA1, a plurality of second sub-pixels 120 may be arranged in an array in the second display area AA2, a row direction in which the first sub-pixels 110 and the second sub-pixels 120 are arranged is a first direction X, and a column direction in which the first sub-pixels 110 and the second sub-pixels 120 are arranged is a second direction Y.

Illustratively, the first display area AA1 includes 2m rows and 2n columns of first sub-pixels 110, a column of first sub-pixels 110 near the frame area NAA is a first column of first sub-pixels 110, and a row of first sub-pixels 110 near the eighth sub-display area AA18 is a first row of first sub-pixels 110. The first m rows of the first n columns of the first sub-pixels 110 may be located in the sixth sub-display area AA16, the second m rows of the first n columns of the first sub-pixels 110 may be located in the fifth sub-display area AA15, and the second n columns of the first sub-pixels 110 may be located in the second sub-display area AA 12. The first pixel circuits 210 corresponding to the first m rows of the first n columns of the first sub-pixels 110 may be disposed in the first sub-area D11 of the eighth sub-display area AA18, the first pixel circuits 210 corresponding to the second m rows of the first n columns of the first sub-pixels 110 may be disposed in the first sub-area D11 of the seventh sub-display area AA17, and the first pixel circuits 210 corresponding to the second n columns of the first sub-pixels 110 may be disposed in the fourth sub-display area AA14. Where m and n may be equal or may not be equal, fig. 5 shows a case where m = n =4, and in other embodiments, m and n may be set to other values according to actual requirements.

FIG. 7 is an enlarged view of a portion of the area P in FIG. 1; fig. 8 is another partial enlarged view of the region P in fig. 1. Fig. 7 and 8 each show a division of the display area of the P region and a part of the scanning line.

With reference to fig. 5 to 8, the display panel optionally further includes a scan line 30 connected to the pixel circuit. A part of the sub-pixel rows in the display panel only include the second sub-pixels 120, then the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same row are connected to the same scan line 30, another part of the sub-pixel rows in the display panel include the first sub-pixels 110 and the second sub-pixels 120, and then the first pixel circuits 210 and the second pixel circuits 220 corresponding to the first sub-pixels 110 and the second sub-pixels 120 in the same row are connected to the same scan line 30. Each of the first pixel circuit 210 and the second pixel circuit 220 includes a switching transistor, and the scan line 30 is connected to a gate of the switching transistor in the corresponding pixel circuit to provide a scan signal to the gate of the switching transistor to control the switching transistor to be turned on or off.

In one embodiment, the scan line 30 to which the first pixel circuit 210 is connected may be disposed outside the first display area AA 1. For example, the scan line 30 connected to the first pixel circuit 210 corresponding to the first sub-pixel 110 in the first sub-display area AA1 may be disposed along the periphery of the first sub-display area AA1 (e.g., the first scan line 310 in fig. 7) to prevent the scan line 30 from penetrating through the first display area AA1 to affect the display effect of the first display area AA 1.

In another embodiment, the scan line 30 connected to the first pixel circuit 210 may pass through the first display area AA1, and the scan line 30 in the first display area AA1 is a transparent metal line. For example, each of the scan lines 30 may extend along a row direction (i.e., the first direction X) in which the first sub-pixel 110 and the second sub-pixel 120 are arranged, the scan line 30 connected to the first pixel circuit 210 includes a portion (e.g., the first scan line 310 in fig. 8) located in the first display area AA1, and the portion of the scan line 30 is a transparent metal line. The advantage of this configuration is that the scan lines 30 can extend along the same direction, which is beneficial to simplify the structure of the scan lines 30, and the scan lines 30 in the first display area AA1 are transparent metal lines, so that the display effect of the first display area AA1 is not affected by the scan lines 30 in the first display area AA 1.

With reference to fig. 5-8, optionally, scan line 30 includes a first scan line 310. At least part of the second sub-pixels 120 are arranged in the same row as the first sub-pixels 110, and the first pixel circuits 210 and the second pixel circuits 220 corresponding to the first sub-pixels 110 and the second sub-pixels 120 in the same row are connected to the same first scanning line 310. The first scanning line 310 includes a first line segment 311 and a second line segment 312, and the first line segment 311 connects the second line segment 312. The first routing segment 311 connects the first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 in the same row in the first display area AA1 and the fourth sub-display area AA14, and the second routing segment 312 connects the second pixel circuit 220 corresponding to the second sub-pixel 120 in the same row in the area other than the fourth sub-display area AA14 in the second display area AA2.

Illustratively, for the first sub-pixel 110 and the second sub-pixel 120 located in the same row as the first sub-pixel 110 in the first display area AA1, the first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 located in the same row are connected to the same first scan line 310. The frame area NAA of the display panel further includes a scan circuit (not shown) for supplying a scan signal to the scan line 30. A first end of the first wire segment 311 may be connected to the corresponding scan circuit, and a second end of the first wire segment 311 is connected to the second wire segment 312. The first line segment 311 connects the first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 in the same row in the first display area AA1 and the fourth sub-display area AA14, that is, the first line segment 311 connects the first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 in the same row in the third sub-display area AA13 and the fourth sub-display area AA14. The second trace 312 connects the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same row in the area of the second display area AA2 except for the fourth sub-display area AA14, that is, the second trace 312 connects the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same row in the area of the second display area AA2 except for the fourth sub-display area AA14. The first and second routing segments 311 and 312 in the same first scan line 310 connect the first and second pixel circuits 210 and 220 corresponding to the first and second sub-pixels 110 and 120 in the same row.

Further, referring to fig. 7, the first route segment 311 may be disposed outside the first display area AA 1. The first line segment 311 may be disposed along the periphery of the first display area AA1, for example, the second display area AA2 may further include a ninth sub-display area AA19, a tenth sub-display area AA110, an eleventh sub-display area AA111, a twelfth sub-display area AA112, and a thirteenth sub-display area AA113, the first line segment 311 may be located in the third sub-display area AA13 and the tenth sub-display area AA110, and the second line segment 312 may be located in the eleventh sub-display area AA 111. By disposing the first route segment 311 outside the first display area AA1, it is helpful to avoid that the first route segment 311 passes through the first display area AA1 to affect the display effect of the first display area AA 1.

In another embodiment, referring to fig. 8, the first routing segment 311 may be disposed to pass through the first display area AA1, and the first routing segment 311 in the first display area AA1 is a transparent metal line. For example, the first line segment 311 may be located in the first display area AA1 and the fourth sub-display area AA14, the first line segment 311 in the first display area AA1 is a transparent metal line, and the second line segment 312 may be located in the eleventh sub-display area AA 111. The first routing segment 311 is arranged to penetrate through the first display area AA1, and the first routing segment 311 in the first display area AA1 is a transparent metal wire, so that the structure of the scanning line is simplified, and the scanning line in the first display area AA1 does not affect the display effect of the first display area AA1 because the first routing segment 311 in the first display area AA1 is the transparent metal wire.

Optionally, the second wire segment 312 in each first scan line 310 may be connected to the corresponding scan circuit through the first wire segment 311 to provide scan signals to the first wire segment 311 and the second wire segment 312 through the same scan circuit, so that the scan signals received by the first pixel circuit 210 and the second pixel circuit 220 connected to the first wire segment 311 and the second wire segment 312 in the same first scan line 310 are the same, which helps to ensure the consistency of the scan signals received by the first pixel circuit 210 and the second pixel circuit 220. Alternatively, the first routing segment 311 and the second routing segment 312 in each first scanning line 310 may be respectively connected to different scanning circuits to provide scanning signals to the first routing segment 311 and the second routing segment 312 through different scanning circuits, so that the scanning signals received by the first pixel circuits 210 connected to the first routing segment 311 are provided by separate scanning circuits, which helps to ensure the consistency of the scanning signals received by the respective first pixel circuits 210 and ensure the consistency of the scanning signals received by the respective second pixel circuits 220.

With reference to fig. 5 to 8, optionally, the scan line 30 further includes a second scan line 320, and for a sub-pixel row including only the second sub-pixels 120, the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same row are connected to the same second scan line 320.

Fig. 9 is another partial enlarged view of the region P in fig. 1. Fig. 9 shows a division of the display area of the P region and a part of the data lines. With reference to fig. 5, 6 and 9, the display panel further includes a data line 40 connecting the pixel circuits. A part of the sub-pixel columns in the display panel only include the second sub-pixels 120, then the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same column are connected to the same data line 40, another part of the sub-pixel columns in the display panel include the first sub-pixels 110 and the second sub-pixels 120, then the first pixel circuits 210 and the second pixel circuits 220 corresponding to the first sub-pixels 110 and the second sub-pixels 120 in the same column are connected to the same data line 40. The data line 40 is used for transmitting a data voltage to the corresponding pixel circuit, so that the driving transistor in the pixel circuit emits light according to the sub-pixel corresponding to the data voltage region.

In one embodiment, the data line 40 to which the first pixel circuit 210 is connected may be located outside the first display area AA 1. For example, the data line 40 connected to the first pixel circuit 210 corresponding to the first sub-pixel 110 in the first sub-display area AA1 may be disposed along the periphery of the first sub-display area AA1 (e.g., the first data line 410 in fig. 9) to prevent the display effect of the first sub-display area AA1 from being affected by the data line 40 passing through the first sub-display area AA 1.

In another embodiment, the data line 40 connected to the first pixel circuit 210 may pass through the first display area AA1, and the data line 40 in the first display area AA1 is a transparent metal line. For example, each data line 40 may extend along the column direction (i.e., the second direction Y) in which the first and second sub-pixels 110 and 120 are arranged, the data line 40 connected to the first pixel circuit 210 includes a portion located in the first display area AA1 (this case is not shown in fig. 9), and the portion of the data line 40 is a transparent metal line. The advantage of this configuration is that the data lines 40 can extend in the same direction, which is beneficial to simplify the structure of the data lines 40, and the data lines 40 in the first display area AA1 are transparent metal lines, so that the display effect of the first display area AA1 is not affected by the data lines 40 in the first display area AA 1.

In conjunction with fig. 5, 6, and 9, optionally, the data line 40 includes a first data line 410 and a second data line 420. The first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 in the same column in the first sub-display area AA11 and the second sub-display area AA2 are connected to the same first data line 410.

The first data line 410 includes a third route segment 413, a fourth route segment 414, a fifth route segment 415, a sixth route segment 416, and a seventh route segment 417. The third line segment 413 and the fourth line segment 414 are connected by a seventh line segment 417, and the fifth line segment 415 and the sixth line segment 416 are connected by a seventh line segment 417. The third trace segment 413 connects the first sub-region D11 of the seventh sub-display region AA17 and the first pixel circuit 210 and the second pixel circuit 220 corresponding to the same column of the first sub-pixel 110 and the second sub-pixel 120 in the second display region AA2 adjacent to the first sub-region D11 of the seventh sub-display region AA17 along the second direction Y. The fifth wire segment 415 connects the second pixel circuits 220 in the second sub-area D12 of the seventh sub-display area AA17 corresponding to the second sub-pixels 120 in the same column. The fourth line segment 414 connects the first sub-region D11 of the eighth sub-display region AA18 and the first pixel circuit 210 and the second pixel circuit 220 corresponding to the same column of the first sub-pixel 110 and the second sub-pixel 120 in the second display region AA2 adjacent to the first sub-region D11 of the eighth sub-display region AA18 along the second direction Y. The sixth wire segment 416 connects the second pixel circuits 220 in the second sub-area D12 of the eighth sub-display area AA18 corresponding to the second sub-pixels 120 in the same column.

Illustratively, a first end of the third running line segment 413 or the fourth running line segment 414 can be connected to a data voltage, second ends of the third running line segment 413 and the fourth running line segment 414 are both connected to a seventh running line segment 417, and first ends of the fifth running line segment 415 and the sixth running line segment 416 are both connected to the seventh running line segment 417, so that the third running line segment 413, the fourth running line segment 414, the fifth running line segment 415, the sixth running line segment 416 and the seventh running line segment 417 are connected to each other, so that the data voltage can be transmitted in the third running line segment 413, the fourth running line segment 414, the fifth running line segment 415, the sixth running line segment 416 and the seventh running line segment 417 in the same first data line 410. The third trace segment 413 may transmit the data voltage to the first pixel circuit 210 in the first sub-area D11 of the seventh sub-display area AA17 and the second pixel circuit 220 in the second display area AA2 (e.g., the twelfth sub-display area AA 112) adjacent to the first sub-area D11 of the seventh sub-display area AA17 along the second direction Y. The fifth routing segment 415 may transfer the data voltage to the second pixel circuit 220 in the second sub-area D12 of the seventh sub-display area AA 17. The fourth line segment 414 may transmit the data voltage to the first pixel circuit 210 in the first sub-area D11 of the eighth sub-display area AA18 and the second pixel circuit 220 in the second display area AA2 (e.g., the thirteenth sub-display area AA 113) adjacent to the first sub-area D11 of the eighth sub-display area AA18 along the second direction Y. The sixth wire segment 416 may transmit the data voltage to the second pixel circuits 220 in the second sub-region D12 of the eighth sub-display area AA 18.

Further, a seventh route segment 417 may be disposed outside the first display area AA 1. The seventh line segment 417 may be disposed along the periphery of the first display area AA1, for example, the third line segment 413, the fourth line segment 414, the fifth line segment 415, and the sixth line segment 416 all extend along the second direction Y, the seventh line segment 417 is located on a side of the first display area AA1 close to the border area NAA, the third line segment 413 is located in the first sub-area D11 of the seventh sub-display area AA17 and the second display area AA2 adjacent to the first sub-area D11 of the seventh sub-display area AA17 along the second direction Y, the fifth line segment 415 is located in the second sub-area D12 of the seventh sub-display area AA17, the fourth line segment 414 is located in the first sub-area D11 of the eighth sub-display area AA18 and the second display area AA2 adjacent to the first sub-area D11 of the eighth sub-display area AA18 along the second direction Y, and the sixth line segment 416 is located in the second sub-area D12 of the eighth sub-display area AA 18. By disposing the seventh route segment 417 outside the first display area AA1, it is helpful to avoid that the seventh route segment 417 passes through the first display area AA1 to affect the display effect of the first display area AA 1.

In another embodiment, the seventh wire segment 417 may also be disposed to pass through the first display area AA1 (not shown in fig. 9), and the seventh wire segment 417 in the first display area AA1 is a transparent metal wire. For example, the seventh routing segment 417 may be located in the first sub-display area AA11, and the seventh routing segment 417 is a transparent metal line, which is beneficial to simplifying the structure of the data line, and since the seventh routing segment 417 is a transparent metal line, the display effect of the first display area AA1 is not affected by the data line in the first display area AA 1.

With reference to fig. 5, 6 and 9, optionally, the data line 40 further includes a second data line 420. The first pixel circuit 210 and the second pixel circuit 220 corresponding to the first sub-pixel 110 and the second sub-pixel 120 in the same column in the first sub-display area AA11 and the second sub-display area AA2 are connected to the same first data line 410. The first pixel circuits 210 and the second pixel circuits 220 of the first sub-pixels 110 and the second sub-pixels 120 in the same column in the second sub-display area AA12 and the second display area AA2 are connected to the same second data line 420.

The second data line 420 includes an eighth trace segment 428, a ninth trace segment 429 and a tenth trace segment 4210, and the eighth trace segment 428 and the ninth trace segment 429 are connected by the tenth trace segment 4210. The eighth line segment 428 connects the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same column in the second display area AA2 located at one side of the second sub-display area AA12 along the second direction Y. The ninth wire segment 429 connects the second pixel circuits 220 corresponding to the second sub-pixels 120 in the same column in the second display area AA2 on the other side of the second sub-display area AA12 along the second direction Y. The tenth routing segment 4210 connects the first pixel circuits 210 corresponding to the first sub-pixels 110 in the same column in the fourth sub-display area AA14.

Illustratively, a first end of the eighth wire segment 428 or the ninth wire segment 429 can be connected to a data voltage, a second end of the eighth wire segment 428 is connected to a first end of the tenth wire segment 4210, and a second end of the tenth wire segment 4210 is connected to a second end of the ninth wire segment 429, so that the eighth wire segment 428, the ninth wire segment 429 and the tenth wire segment 4210 are connected to each other, so that the data voltage can be transmitted in the eighth wire segment 428, the ninth wire segment 429 and the tenth wire segment 4210 in the same second data line 420. The eighth line segment 428 may transmit the data voltage to the second pixel circuits 220 in the second display area AA2 (e.g., the ninth sub-display area AA19 and the twelfth sub-display area AA 112) located at one side of the second sub-display area AA12 along the second direction Y. The ninth wire segment 429 may transmit the data voltage to the second pixel circuit 220 in the second display area AA2 (e.g., the tenth sub-display area AA110 and the thirteenth sub-display area AA 113) located at the other side of the second sub-display area AA12 along the second direction Y. The tenth routing segment 4210 may transmit a data voltage to the first pixel circuit 210 in the fourth sub-display area AA14.

Further, the tenth routing segment 4210 may be disposed outside the first display area AA 1. The tenth routing segment 4210 may be disposed along the periphery of the first display area AA1, for example, the eighth routing segment 428, the ninth routing segment 429 and the tenth routing segment 4210 all extend along the second direction Y, the tenth routing segment 4210 is located on a side of the first display area AA1 away from the border area NAA along the first direction X, the eighth routing segment 428 is located in the ninth sub-display area AA19 and the twelfth sub-display area AA112 along the second direction Y, and the ninth routing segment 429 is located in the tenth sub-display area AA110 and the thirteenth sub-display area AA 113. By arranging the tenth routing segment 4210 outside the first display area AA1, it is helpful to prevent the tenth routing segment 4210 from penetrating through the first display area AA1 to affect the display effect of the first display area AA 1.

In another embodiment, the tenth routing segment 4210 may also be disposed to pass through the first display area AA1 (not shown in fig. 9), and the tenth routing segment 4210 in the first display area AA1 is a transparent metal line. For example, the tenth routing segment 4210 may be located in the second sub-display area AA12, and the tenth routing segment 4210 is a transparent metal line, which is beneficial to simplifying the structure of the data line, and the data line in the first display area AA1 does not affect the display effect of the first display area AA1 because the tenth routing segment 4210 is a transparent metal line.

Alternatively, the material of the transparent metal line in each of the above embodiments may include Indium Tin Oxide (ITO) and/or Indium Zinc Oxide (IZO).

With reference to fig. 5, 6 and 9, optionally, the data line 40 further includes a third data line 430. For a sub-pixel column including only the second sub-pixels 120, the second pixel circuits 220 corresponding to the second sub-pixels 120 located in the same column are connected to the same third data line 430.

It should be noted that, in fig. 1 and fig. 2 to fig. 9, the shape of the first display area AA1 is illustrated as a rectangle, in other embodiments, the shape of the first display area AA1 is not limited to a rectangle, the shape of the first display area AA1 may also be a circle, a drop, a "U" shape, and the like, and the first display area AA1 may also be disposed at other positions in the display area AA, and the shape and the position of the first display area AA1 are not particularly limited in the embodiments of the present invention.

The embodiment of the present invention further provides a display device, where the display device includes the display panel in any of the above embodiments, and the display device may be a device with a display function, such as a mobile phone, a desktop computer, a notebook computer, and a tablet computer. The display device provided by the embodiment of the invention comprises the display panel in any embodiment, so that the display device has a corresponding functional structure and beneficial effects of the display panel, and the description is omitted.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A display panel having a first display region and a second display region, a light transmittance of the first display region being greater than a light transmittance of the second display region, the display panel comprising:

the sub-pixels comprise first sub-pixels and second sub-pixels, the first sub-pixels are positioned in the first display area, and the second sub-pixels are positioned in the second display area;

the pixel circuit comprises a first pixel circuit and a second pixel circuit, is positioned in the second display area, and is used for driving the first sub-pixel and the second sub-pixel;

the second display area comprises a first area adjacent to the first display area, the first area is divided into a first sub-area and a second sub-area, at least part of the first pixel circuits are arranged in the first sub-area, and the second pixel circuits corresponding to the second sub-pixels in the first sub-area and the second sub-area are arranged in the second sub-area.

2. The display panel according to claim 1, wherein the display panel has a frame region, the frame region being located at a periphery of the first display region and the second display region;

the second display area surrounds the first display area, the first display area comprises at least one row of the first sub-pixels, an area from the row of the first sub-pixels closest to the frame area in the first display area is a second area, and the first pixel circuit is located outside the second area;

or the second display area semi-surrounds the first display area, and the first display area is adjacent to the frame area.

3. The display panel according to claim 1, further comprising a dummy pixel circuit in the second display region, at least a part of the dummy pixel circuit in the first region being multiplexed into the first pixel circuit and/or the second pixel circuit.

4. The display panel according to claim 1, wherein at least part of the first pixel circuits are located between adjacent second pixel circuits;

preferably, the display panel further includes a dummy pixel circuit located between adjacent second pixel circuits, at least a part of the dummy pixel circuit being multiplexed into the first pixel circuit.

5. The display panel according to claim 1, wherein the first display region comprises a first sub-display region and a second sub-display region, and the second display region comprises a third sub-display region and a fourth sub-display region, the third sub-display region being adjacent to the first sub-display region, and the fourth sub-display region being adjacent to the second sub-display region;

the first pixel circuit corresponding to the first sub-pixel in the first sub-display area is located in the third sub-display area, and the first pixel circuit corresponding to the sub-pixel in the second sub-display area is located in the fourth sub-display area;

the third sub-display region serves as the first region, and the first pixel circuits in the fourth sub-display region are located between the adjacent second pixel circuits.

6. The display panel according to claim 5, wherein the first sub-display region comprises a fifth sub-display region and a sixth sub-display region, the third sub-display region comprises a seventh sub-display region and an eighth sub-display region, the seventh sub-display region is adjacent to the fifth sub-display region, and the eighth sub-display region is adjacent to the sixth sub-display region;

the seventh sub-display region comprises the first sub-region and the second sub-region, the first pixel circuit corresponding to the first sub-pixel in the fifth sub-display region is located in the first sub-region of the seventh sub-display region, and the second pixel circuit corresponding to the second sub-pixel in the seventh sub-display region is located in the second sub-region of the seventh sub-display region;

the eighth sub-display area comprises the first sub-area and the second sub-area, the first pixel circuit corresponding to the first sub-pixel in the sixth sub-display area is located in the first sub-area of the eighth sub-display area, and the second pixel circuit corresponding to the second sub-pixel in the eighth sub-display area is located in the second sub-area of the eighth sub-display area;

preferably, the display panel further comprises a dummy pixel circuit, at least a portion of the dummy pixel circuit in the first sub-region is multiplexed as the first pixel circuit, and at least a portion of the dummy pixel circuit in the second sub-region is multiplexed as the second pixel circuit;

preferably, at least a part of the dummy pixel circuits in the fourth sub-display area are multiplexed as the first pixel circuits;

preferably, the first sub-display area and the second sub-display area are arranged along a first direction, and along the first direction, the fourth sub-display area is located on one side of the second sub-display area, which is far away from the first sub-display area;

the fifth sub-display area and the sixth sub-display area are arranged along a second direction, the seventh sub-display area is located on one side, away from the sixth sub-display area, of the fifth sub-display area along the second direction, the eighth sub-display area is located on one side, away from the fifth sub-display area, of the sixth sub-display area, and the second direction is perpendicular to the first direction.

7. The display panel according to claim 1, further comprising a scan line and a data line which connect the pixel circuits;

the scanning line connected with the first pixel circuit is positioned outside the first display area; or the scanning line connected with the first pixel circuit passes through the first display area, and the scanning line positioned in the first display area is a transparent metal line;

the data line connected with the first pixel circuit is positioned outside the first display area; or the data line connected with the first pixel circuit penetrates through the first display area, and the data line positioned in the first display area is a transparent metal line.

8. The display panel according to claim 5, wherein the display panel further comprises a scan line, the scan line comprising a first scan line;

the plurality of first sub-pixels are arranged in an array in the first display area, the plurality of second sub-pixels are arranged in an array in the second display area, at least part of the second sub-pixels are arranged in the same row as the first sub-pixels, the row direction of the arrangement of the first sub-pixels and the second sub-pixels is a first direction, and the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels in the same row are connected with the same first scanning line;

the first scanning line comprises a first routing segment and a second routing segment, and the first routing segment is connected with the second routing segment; the first routing section is connected with the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel which are positioned in the same row in the first display area and the fourth sub-display area, and the second routing section is connected with the second pixel circuit corresponding to the second sub-pixel which is positioned in the same row in the second display area except the fourth sub-display area;

the first routing section is positioned outside the first display area; or the first routing segment passes through the first display area, and the first routing segment in the first display area is a transparent metal wire.

9. The display panel according to claim 6, wherein the display panel further comprises data lines including a first data line and a second data line;

the plurality of first sub-pixels are arranged in an array in the first display area, the plurality of second sub-pixels are arranged in an array in the second display area, at least part of the second sub-pixels are arranged in the same column as the first sub-pixels, the column direction in which the first sub-pixels and the second sub-pixels are arranged is a second direction, the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels which are positioned in the same column in the first display area and the second display area are connected with the same first data line, and the first pixel circuits and the second pixel circuits corresponding to the first sub-pixels and the second sub-pixels which are positioned in the same column in the second display area and the second display area are connected with the same second data line;

the first data line comprises a third line segment, a fourth line segment, a fifth line segment, a sixth line segment and a seventh line segment; the third routing section and the fourth routing section are connected through the seventh routing section, and the fifth routing section and the sixth routing section are connected through the seventh routing section; the third routing segment is connected with the first sub-area of the seventh sub-display area and the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel in the same column in the second display area adjacent to the first sub-area of the seventh sub-display area along the second direction; the fifth routing section is connected with the second pixel circuits corresponding to the second sub-pixels in the same column in a second sub-area of the seventh sub-display area; the fourth routing segment is connected with the first sub-area of the eighth sub-display area and the first pixel circuit and the second pixel circuit corresponding to the first sub-pixel and the second sub-pixel in the same column in the second display area adjacent to the first sub-area of the eighth sub-display area along the second direction; the sixth routing segment is connected with the second pixel circuits corresponding to the second sub-pixels in the same column in a second sub-area of the eighth sub-display area;

the seventh routing section is located outside the first display area; or the seventh routing segment passes through the first display area, and the seventh routing segment in the first display area is a transparent metal wire;

the second data line comprises an eighth routing segment, a ninth routing segment and a tenth routing segment, and the eighth routing segment is connected with the ninth routing segment through the tenth routing segment; the eighth routing segment is connected with the second pixel circuits corresponding to the second sub-pixels in the same row in the second display area on one side of the second sub-display area along the second direction; the ninth routing section is connected with the second pixel circuits which are positioned in the second display area on the other side of the second sub-display area along the second direction and correspond to the second sub-pixels in the same column; the tenth routing section is connected with the first pixel circuits corresponding to the first sub-pixels in the same column in the fourth sub-display area;

the tenth routing section is located outside the first display area; or, the tenth routing segment passes through the first display area, and the tenth routing segment in the first display area is a transparent metal wire.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.

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