CN114171606A - Schottky barrier diode with intrinsic GaN cap layer and multiple channels and preparation method thereof - Google Patents

Schottky barrier diode with intrinsic GaN cap layer and multiple channels and preparation method thereof Download PDF

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CN114171606A
CN114171606A CN202111276721.1A CN202111276721A CN114171606A CN 114171606 A CN114171606 A CN 114171606A CN 202111276721 A CN202111276721 A CN 202111276721A CN 114171606 A CN114171606 A CN 114171606A
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layer
cap layer
gan cap
intrinsic gan
channel structure
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张涛
李若晗
段小玲
张进成
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]

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Abstract

The invention relates to a Schottky barrier diode with an intrinsic GaN cap layer and multiple channels and a preparation method thereof, wherein the Schottky barrier diode comprises the following components: the device comprises a substrate layer, a nucleating layer, a buffer layer, a heterojunction multi-channel structure, an intrinsic GaN cap layer, an anode electrode, a cathode electrode and an anode field plate, wherein the substrate layer, the nucleating layer, the buffer layer, the heterojunction multi-channel structure and the intrinsic GaN cap layer are sequentially stacked; the anode electrode is arranged at one end of the intrinsic GaN cap layer and one end of the heterojunction multi-channel structure; the cathode electrode is positioned at the intrinsic GaN cap layer and the other end of the heterojunction multi-channel structure; the anode field plate is positioned on the anode electrode and the intrinsic GaN cap layer. In the Schottky diode, the intrinsic thick GaN cap layer structure can effectively relieve the surface state of the barrier layer to inhibit current collapse and improve the reliability of the device; the heterojunction multi-channel structure can improve electron mobility, increase the total two-dimensional electron gas density of the device, reduce material sheet resistance, reduce series resistance, and realize the utilization rate of the device in the high-frequency high-voltage application field.

Description

Schottky barrier diode with intrinsic GaN cap layer and multiple channels and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a Schottky barrier diode with an intrinsic GaN cap layer and multiple channels and a preparation method thereof.
Background
With the development of semiconductor technology, group III nitride semiconductor materials represented by GaN, AlN, InN, and the like have outstanding characteristics and are widely used in the fields of microwave communication, power application, and the like. The GaN material has high critical field intensity, high electron saturation rate, high ultimate operating temperature and wide forbidden band width, so that the GaN material is an ideal material for manufacturing high-frequency, high-voltage, high-temperature and high-power devices. In the application of the GaN power device, the GaN power device conducts electricity by forming a high-concentration two-dimensional electron gas (2DEG) at a heterojunction interface through heterojunction contact, and the reverse recovery of minority carriers does not exist, so that the switching speed is higher. Therefore, the improvement of the efficiency of the circuit system due to the low turn-on voltage drop and the extremely short reverse recovery time of the GaN-based Schottky Barrier Diode (SBD) has attracted high attention and is widely used.
However, in the development process of GaN-based schottky barrier diodes, due to the deficiencies in theory and process, the performance of the devices is far from reaching an ideal level, and in AlGaN/GaN heterojunction schottky diodes, the materials themselves have certain defects, which are mainly due to the fact that in general GaN materials are formed through heteroepitaxy, so that an extra leakage path is generated, the leakage current is increased, and the breakdown voltage of the devices is affected. On the other hand, as the conducting path of the AlGaN/GaN transverse Schottky diode is close to the surface of the device, the surface state has non-negligible influence on the device in a high-voltage state, when the critical breakdown electric field of the GaN material is not reached, the high electric field effect can perform field emission tunneling on electrons of the anode electrode to enter a surface passivation layer, the tunneled electrons can neutralize the surface polarization positive charges of the AlGaN layer, the surface polarization positive charges are directly related to the concentration of 2DEG at the heterojunction interface, and partial surface positive charges are neutralized to reduce the high-density 2DEG concentration, so that the output current of the transverse AlGaN/GaN Schottky diode is obviously reduced.
In summary, buffer layer defects and surface defects can cause current collapse effects, reducing the output power of the device. If the GaN-based Schottky diode is used in a rectifying circuit, high-frequency and high-efficiency rectification is easily realized although many photons are conducted without minority carrier accumulation, but the voltage resistance is not high, so that the GaN-based Schottky diode cannot be applied to a high-voltage scene. Therefore, research and development of a GaN-based schottky barrier diode at a higher level become one of the key directions of domestic and foreign research, and realization of a high-voltage resistant GaN-based schottky barrier diode with small series resistance, which is not affected by a charge storage effect, as an excellent high-voltage rectifying device becomes a problem to be solved at present.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a schottky barrier diode having an intrinsic GaN cap layer and multiple channels and a method for manufacturing the same. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a Schottky barrier diode with an intrinsic GaN cap layer and multiple channels, which comprises: a substrate layer, a nucleation layer, a buffer layer, a heterojunction multi-channel structure, an intrinsic GaN cap layer, an anode electrode, a cathode electrode and an anode field plate, wherein,
the substrate layer, the nucleation layer, the buffer layer, the heterojunction multi-channel structure and the intrinsic GaN cap layer are sequentially stacked;
the anode electrode is arranged at one end of the intrinsic GaN cap layer and one end of the heterojunction multi-channel structure and is in contact with multiple channels in the heterojunction multi-channel structure; (the places marked with red are confirmed)
The cathode electrode is positioned at the intrinsic GaN cap layer and the other end of the heterojunction multi-channel structure and is in contact with multiple channels in the heterojunction multi-channel structure;
the anode field plate is positioned on the anode electrode and the intrinsic GaN cap layer.
In one embodiment of the present invention, the heterojunction multi-channel structure includes channel layers and barrier layers alternately stacked in this order, wherein an underlying channel layer is located on the buffer layer.
In one embodiment of the invention, the heterojunction multi-channel structure adopts an AlGaN/GaN superlattice structure, and the superlattice structure has 2-6 periods.
In one embodiment of the invention, the thickness of the AlGaN layer in each period of the heterojunction multi-channel structure is 10-20 nm, and the thickness of the GaN layer is 10-100 nm.
In one embodiment of the present invention, the intrinsic GaN cap layer has a thickness greater than or equal to 10 nm.
In one embodiment of the present invention, the bottom of the anode electrode is located below the upper surface of the bottom channel layer in the heterojunction multi-channel structure, and the distance between the bottom of the anode electrode and the upper surface of the bottom channel layer in the heterojunction multi-channel structure is 10-40 nm.
In one embodiment of the invention, the length of the anode field plate on the intrinsic GaN cap layer is 1-4 μm.
Another embodiment of the present invention provides a method for fabricating a schottky barrier diode having an intrinsic GaN cap layer and a multi-channel, including the steps of:
s1, obtaining an epitaxial wafer comprising a substrate layer, a nucleation layer, a buffer layer, a heterojunction multi-channel structure and an intrinsic GaN cap layer which are sequentially stacked, and carrying out mesa isolation on the epitaxial wafer;
s2, etching the intrinsic GaN cap layer at one end of the epitaxial wafer and the heterojunction multi-channel structure to form a cathode groove, and depositing a metal layer in the cathode groove to form a cathode electrode;
s3, etching the intrinsic GaN cap layer at the other end of the epitaxial wafer and the heterojunction multi-channel structure to form an anode groove;
and S4, depositing a metal material in the anode groove and on the intrinsic GaN cap layer on one side of the anode groove to form an anode electrode and an anode field plate.
In one embodiment of the invention, the heterojunction multi-channel structure adopts an AlGaN/GaN superlattice structure, and the superlattice structure has 2-6 periods.
In one embodiment of the present invention, the intrinsic GaN cap layer has a thickness greater than or equal to 10 nm.
Compared with the prior art, the invention has the beneficial effects that:
1. in the Schottky barrier diode, the intrinsic GaN cap layer forms two-dimensional hole gas (2DGH) at the GaN/AlGaN interface, the electric field peak value is improved, the voltage endurance capability of the device is improved, the two-dimensional electron gas (2DEG) channel is far away from the influence of surface potential energy fluctuation, the current collapse inhibition effect is obvious, and the dynamic on-resistance degradation phenomenon of the device is obviously improved compared with that of the traditional transverse AlGaN/GaN Schottky diode.
2. In the Schottky barrier diode, a heterojunction multi-channel structure is adopted, so that a plurality of layers of two-dimensional electron gas channels can be introduced, the electron mobility is improved, the total two-dimensional electron gas density of the device is increased, the series resistance is reduced, the sheet resistance of the material is reduced, the electrical characteristics of the device are greatly improved, the breakdown voltage is improved, and the utilization rate of the device in the high-frequency high-voltage application field is realized.
Drawings
Fig. 1 is a schematic structural diagram of a schottky barrier diode having an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for fabricating a schottky barrier diode with an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention;
fig. 3a to fig. 3e are schematic views illustrating a manufacturing process of a schottky barrier diode having an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a schottky barrier diode having an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention. The Schottky barrier diode is of a transverse structure and comprises a substrate layer 1, a nucleating layer 2, a buffer layer 3, a heterojunction multi-channel structure 4, an intrinsic GaN cap layer 5, an anode electrode 6, a cathode electrode 7 and an anode field plate 8.
The substrate layer 1, the nucleation layer 2, the buffer layer 3, the heterojunction multi-channel structure 4 and the intrinsic GaN cap layer 5 are sequentially stacked. Etching the intrinsic GaN cap layer 5 and the heterojunction multi-channel structure 4 to form an anode groove and a cathode groove, and arranging an anode electrode 6 and a cathode electrode 7 in the anode groove and the cathode groove; the anode electrode 6 is arranged at one end of the intrinsic GaN cap layer 5 and one end of the heterojunction multi-channel structure 4, is in contact with multiple channels in the heterojunction multi-channel structure 4, and forms Schottky contact at the contact surface; and the cathode electrode 7 is positioned at the intrinsic GaN cap layer 5 and the other end of the heterojunction multi-channel structure 4, is in contact with the multi-channel in the heterojunction multi-channel structure 4, and forms ohmic contact with the contact surface. An anode field plate 8 is located on the anode electrode 6 and the intrinsic GaN cap layer 5.
Specifically, the material of the substrate layer 1 comprises one or more of sapphire, Si, SiC, and GaN. The material of the nucleation layer 2 comprises one or more of AlN and GaN, and the thickness of the nucleation layer is 30-90 nm. The buffer layer 3 is made of GaN and has a thickness of 0.5-5 μm.
Specifically, the heterojunction multi-channel structure 4 includes channel layers and barrier layers alternately stacked in this order, wherein the bottom channel layer is located on the buffer layer 3. Furthermore, the heterojunction multi-channel structure 4 adopts an AlGaN/GaN superlattice structure, and the superlattice structure has 2-6 periods, namely the heterojunction multi-channel structure 4 adopts a structure in which GaN channel layers and AlGaN barrier layers are alternately laminated in sequence, and the number of the alternately laminated layers is 2-6; in each period, the thickness of the AlGaN layer is 10-20 nm, and the thickness of the GaN layer is 10-100 nm.
In this embodiment, adopt heterojunction multichannel structure can introduce multilayer two-dimensional electron gas channel, improve electron mobility, increase the total two-dimensional electron gas density of device, reduce series resistance, reduce the material square resistance, improve breakdown voltage simultaneously to promote the electricity special type of device greatly, realize the utilization ratio of device in high frequency high voltage application.
Specifically, the intrinsic GaN cap layer 5 is an intrinsic thick GaN cap layer, and the thickness thereof is greater than or equal to 10 nm.
In the embodiment, due to the polarization effect between GaN/AlGaN, the intrinsic GaN cap layer forms the two-dimensional hole gas 2DGH at the GaN/AlGaN interface, so that the electric field peak value is improved, the voltage endurance capability of the device is improved, the two-dimensional electron gas 2DEG channel is far away from the influence of surface potential energy fluctuation, the current collapse inhibition effect is remarkable, and the dynamic on-resistance degradation phenomenon of the device is obviously improved compared with that of the traditional transverse AlGaN/GaN Schottky diode.
In addition, the intrinsic GaN cap layer 5 is arranged in the device, which causes the resistance of the material to be increased and the electrical performance of the device to be deteriorated, so that the embodiment simultaneously arranges the heterojunction multi-channel structure to improve the defects caused by the intrinsic GaN cap layer 5, and the heterojunction multi-channel structure can reduce the resistance of the material, reduce the sheet resistance and improve the electrical characteristics of the device.
The anode electrode 6 and the cathode electrode 7 can be in contact with the side faces of the heterojunction multi-channel structure 4 and the intrinsic GaN cap layer 5, namely, the anode groove is etched to the bottom-layer channel layer in the heterojunction multi-channel structure 4, and the bottoms of the anode electrode 6 and the cathode electrode 7 are in contact with the bottom-layer channel layer; or contacting with the buffer layer 3, the heterojunction multi-channel structure 4 and the side face of the intrinsic GaN cap layer 5, namely etching the anode groove to the buffer layer 3, and contacting the bottom of the anode electrode 6 and the cathode electrode 7 with the buffer layer 3; the present embodiment does not further limit the thickness of the anode electrode 6 and the cathode electrode 7 as long as they are in contact with the multi-channel in the heterojunction multi-channel structure 4. Specifically, the bottom of the anode electrode 6 is located below the upper surface of the bottom channel layer in the heterojunction multi-channel structure 4, and the distance between the bottom of the anode electrode 6 and the upper surface of the bottom channel layer in the heterojunction multi-channel structure 4 is 10-40 nm, namely the bottom of the anode electrode 6 is located 10-40 nm below the interface of the bottom GaN channel layer in the heterojunction multi-channel structure 4.
Specifically, the anode electrode 6 and the anode field plate 8 can be made of Ni/Au/Ni, Ni/Au, W/Au or Mo/Au, and the thickness of the anode electrode 6 and the anode field plate 8 depends on the material used; the material of the cathode 7 may be Ti/Al, Ti/Al/Ni/Au or Ti/Al/Mo/Au, the thickness of the cathode 7 depending on the material used.
Specifically, the length of the anode field plate 8 on the intrinsic GaN cap layer 5 is 1 μm to 4 μm.
In conclusion, the intrinsic thick GaN cap layer structure can effectively improve the breakdown voltage of the device, can inhibit the influence of surface potential fluctuation on a two-dimensional electronic air channel, relieves the action of the surface state of the barrier layer to inhibit current collapse, and improves the reliability of the device; meanwhile, the heterojunction multi-channel structure utilizes the polarization effect to generate a plurality of layers of two-dimensional electron gas channels, so that the electron mobility is improved, the total two-dimensional electron gas density of the device is increased, the material sheet resistance is reduced, and the series resistance is reduced, so that the Schottky diode device made of the GaN material is developed more recently in the field of ultrahigh frequency high-power application.
Example two
On the basis of the first embodiment, please refer to fig. 2 and fig. 3a to fig. 3e, fig. 2 is a flowchart of a method for manufacturing a schottky barrier diode having an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention, and fig. 3a to fig. 3e are schematic diagrams of a manufacturing process of a schottky barrier diode having an intrinsic GaN cap layer and multiple channels according to an embodiment of the present invention.
The preparation method comprises the following steps:
and S1, obtaining an epitaxial wafer comprising a substrate layer 1, a nucleation layer 2, a buffer layer 3, a heterojunction multi-channel structure 4 and an intrinsic GaN cap layer 5 which are sequentially stacked, and carrying out mesa isolation on the epitaxial wafer. In this embodiment, the epitaxial wafer may be obtained by MOCVD epitaxial growth.
First, the epitaxial wafer is cleaned, and the structure of the epitaxial wafer is shown in fig. 3 a.
Specifically, the epitaxial material is placed in an acetone solution for 5 minutes by ultrasonic treatment, and organic pollution on the surface layer of the epitaxial wafer is washed away; secondly, placing the epitaxial wafer cleaned by the acetone into an isopropanol solution for ultrasonic cleaning for 5 minutes to remove the acetone solution remained on the surface; then placing the epitaxial wafer in deionized water for washing, and washing off isopropanol attached to the surface of the material; and finally, blowing the surface of the wafer by using high-purity nitrogen. After the organic cleaning of the epitaxial wafer is finished, the material is placed in a BOE solution with the concentration of 1:7 for 30s, an oxide layer on the surface is removed, a large amount of deionized water is used for washing, finally, the deionized water on the surface of the wafer is dried by high-purity nitrogen, and the inorganic cleaning of the epitaxial wafer is finished.
Mesa isolation is then performed on the epitaxial wafer to avoid mutual interference between devices, see fig. 3 b.
Specifically, firstly, spin coating, baking, photoetching and developing are carried out on the cleaned epitaxial wafer; then, etching the area outside the table top of the intrinsic GaN cap layer 5 by a plasma etching ICP method, removing two-dimensional electron gas of the heterojunction multi-channel structure 4, and realizing the effect of mutual separation between devices; and then, carrying out organic cleaning on the etched epitaxial wafer, and then blowing the epitaxial wafer by using nitrogen.
S2, etching the intrinsic GaN cap layer 5 at one end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form a cathode groove, and depositing a metal layer in the cathode groove to form a cathode electrode 7, as shown in FIG. 3 c.
Specifically, the epitaxial wafer with the mesa isolation is subjected to spin coating, baking, photoetching and developing; then, etching the intrinsic GaN cap layer 5 and the heterojunction multi-channel structure 4 by a plasma etching ICP method to form a cathode groove; then growing a Ti/Al/Ni/Au metal layer on the surface of the sample by adopting an electron beam evaporation technology; then soaking the epitaxial wafer on which the metal layer is deposited in an acetone solution, an NMP solution and the like, heating and ultrasonically carrying out a photoresist stripping process, and only leaving metal in a cathode ohmic contact electrode area, namely a cathode groove area; and finally, carrying out organic cleaning on the stripped epitaxial wafer, then carrying out blow-drying by using nitrogen, and carrying out high-temperature annealing at 870 ℃ for 35s in the nitrogen atmosphere to form the cathode 7.
S3, etching the intrinsic GaN cap layer 5 at the other end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form an anode groove, as shown in FIG. 3 d.
Specifically, the epitaxial wafer with the ohmic contact cathode is subjected to spin coating, baking, photoetching and developing; then, etching the intrinsic GaN cap layer 5 and the heterojunction multi-channel structure 4 of the epitaxial wafer by using a slow-speed low-damage etching technology to form an anode groove, wherein the depth of the groove can reach the bottom channel layer of the multi-channel structure; then, carrying out organic cleaning on the etched epitaxial wafer, and then drying the epitaxial wafer by using nitrogen; and finally, annealing the etched epitaxial wafer at 450 ℃ for 5min in a nitrogen atmosphere to repair etching damage.
S4, depositing a metal material in the anode groove and on the intrinsic GaN cap layer 5 at one side of the anode groove to form the anode electrode 6 and the anode field plate 8, see fig. 3 e.
Specifically, the epitaxial wafer subjected to the anode groove etching is subjected to spin coating, baking, photoetching and developing; then, removing residual glue of the epitaxial wafer after the photoetching by using a glue applicator; then, depositing Ni/Au metal or W/Au metal as Schottky anode metal and anode field plate metal of the device on the surfaces of the intrinsic GaN cap layer 5 in the anode groove and near the anode groove by adopting electron beam evaporation equipment; then, carrying out photoresist stripping process on the epitaxial wafer after the metal layer is deposited, and only leaving the metal of the anode electrode and the anode field plate region; and finally, carrying out organic cleaning on the stripped epitaxial wafer, and then drying the epitaxial wafer by using nitrogen to form the anode electrode 6 and the anode field plate 8, wherein the anode electrode 6 and the anode field plate 8 jointly form Schottky anode contact.
For the parameters of each layer of structure and the prepared device structure, please refer to embodiment one, which is not described in detail in this embodiment.
The preparation method of the embodiment can improve the withstand voltage capability of the electric field peak value boosting device by adopting the intrinsic thick GaN cap layer, enables the 2DEG channel to be far away from the influence of surface potential energy fluctuation, has a remarkable effect on inhibiting current collapse, and obviously improves the dynamic on-resistance degradation phenomenon of the device compared with the traditional transverse AlGaN/GaN Schottky diode. By adopting a heterojunction multi-channel structure and introducing a multi-layer two-dimensional electron gas (2DEG) channel, the electron mobility is improved, the total two-dimensional electron gas density of the device is increased, the series resistance is reduced, the material sheet resistance is reduced, the electrical characteristics of the device are greatly improved, and the breakdown voltage is improved.
EXAMPLE III
On the basis of the second embodiment, referring to fig. 3a to fig. 3e, this embodiment takes the preparation of a sapphire substrate layer 1, a 45nm AlN nucleation layer 2, a 2.4 μm GaN buffer layer 3, a multi-channel structure with 4 cycles (in each cycle, a single-layer GaN channel layer is 20nm, and an AlGaN barrier layer is 20nm), and an 80nm intrinsic GaN cap layer 5 as an example to explain the preparation method thereof.
The preparation method comprises the following steps:
and S1, obtaining an epitaxial wafer comprising a substrate layer 1, a nucleation layer 2, a buffer layer 3, a heterojunction multi-channel structure 4 and an intrinsic GaN cap layer 5 which are sequentially stacked, and carrying out mesa isolation on the epitaxial wafer.
First, the epitaxial wafer is cleaned, and the structure of the epitaxial wafer is shown in fig. 3 a.
Specifically, the epitaxial material is placed in an acetone solution for 5 minutes by ultrasonic treatment, and organic pollution on the surface layer of the epitaxial wafer is washed away; secondly, placing the epitaxial wafer cleaned by the acetone into an isopropanol solution for ultrasonic cleaning for 5 minutes to remove the acetone solution remained on the surface; then placing the epitaxial wafer in deionized water for washing, and washing off isopropanol attached to the surface of the material; and finally, blowing the surface of the wafer by using high-purity nitrogen. After the organic cleaning of the epitaxial wafer is finished, the material is placed in a BOE solution with the concentration of 1:7 for 30s, an oxide layer on the surface is removed, a large amount of deionized water is used for washing, finally, the deionized water on the surface of the wafer is dried by high-purity nitrogen, and the inorganic cleaning of the epitaxial wafer is finished.
Mesa isolation is then performed on the epitaxial wafer to avoid mutual interference between devices, see fig. 3 b.
Specifically, spin coating, baking, photoetching and developing are carried out on the cleaned epitaxial wafer; etching the region outside the table top of the intrinsic GaN cap layer 5 by a plasma etching ICP method, removing two-dimensional electron gas of the heterojunction multi-channel structure 4, and realizing the effect of mutually separating the devices, wherein Cl is adopted2/BCl3The mixed gas of (1) etching the material, wherein Cl2Flow rate of 10sccm, BCl3The flow is 25sccm, the ICP power is 150W, the RF power is 50W, and the material etching rate is about 55 nm/min; and finally, carrying out organic cleaning on the etched epitaxial wafer, and then blowing the epitaxial wafer to dry by using nitrogen.
S2, etching the intrinsic GaN cap layer 5 at one end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form a cathode groove, and depositing a metal layer in the cathode groove to form a cathode electrode 7, as shown in FIG. 3 c.
Specifically, the epitaxial wafer with the mesa isolation is subjected to spin coating, baking, photoetching and developing; and etching the intrinsic thick GaN cap layer 5 and the heterojunction multi-channel structure 4 of the epitaxial wafer by plasma etching ICP to form a cathode groove, wherein the etching conditions are as follows:by Cl2/BCl3Etching the material with the mixed gas of (1), Cl2Flow rate of 10sccm, BCl3The flow is 25sccm, the ICP power is 150W, the RF power is 50W, and the material etching rate is about 55 nm/min; then, growing a Ti/Al/Ni/Au (22/140/55/45nm) metal layer on the surface of the epitaxial wafer by adopting an electron beam evaporation technology; then, carrying out a photoresist stripping process on the epitaxial wafer on which the metal layer is deposited, and only leaving the metal in the cathode ohmic contact electrode area; and finally, carrying out organic cleaning on the stripped epitaxial wafer, then carrying out blow-drying by using nitrogen, and carrying out high-temperature annealing at 870 ℃ for 35s in the nitrogen atmosphere to form a cathode electrode 7.
S3, etching the intrinsic GaN cap layer 5 at the other end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form an anode groove, as shown in FIG. 3 d.
Specifically, the epitaxial wafer with the ohmic contact cathode is subjected to spin coating, baking, photoetching and developing; then, etching the intrinsic GaN cap layer 5 and the heterojunction multi-channel structure 4 of the epitaxial wafer by using a slow-speed low-damage etching technology to form an anode groove, wherein in the slow-speed etching process, only BCl3 is used as etching gas, the flow rate is set to be 25sccm, the ICP power is biased to be 0W, the RF power is biased to be 55W, the AlGaN material is bombarded by mainly B ions to realize a smaller etching rate and a better etching surface, and the etching rate less than 2nm/min is realized by optimizing the gas flow rate and the power bias; then, carrying out organic cleaning on the etched epitaxial wafer, and then drying the epitaxial wafer by using nitrogen; and finally, annealing the etched epitaxial wafer at 450 ℃ for 5min in a nitrogen atmosphere to repair etching damage.
S4, depositing a metal material in the anode groove and on the intrinsic GaN cap layer 5 at one side of the anode groove to form the anode electrode 6 and the anode field plate 8, see fig. 3 e.
Specifically, the epitaxial wafer subjected to the anode groove etching is subjected to spin coating, baking, photoetching and developing; then, removing residual glue of the epitaxial wafer after the photoetching by using a glue applicator; then, depositing Ni/Au (30/150nm) metal on the epitaxial wafer with the anode groove in the groove and on the surface of the intrinsic GaN cap layer 5 near the groove by adopting electron beam evaporation equipment to serve as a Schottky anode and anode field plate metal of the device; then, carrying out photoresist stripping process on the epitaxial wafer deposited with the metal layer, and only leaving the metal of the anode electrode and the anode field plate region; and finally, carrying out organic cleaning on the stripped epitaxial wafer, and then blow-drying the epitaxial wafer by using nitrogen to form the anode electrode 6 and the anode field plate 8.
Example four
On the basis of the second embodiment, referring to fig. 3a to fig. 3e, this embodiment takes the preparation of a Si substrate layer, a 45nm AlN nucleation layer, a 2.4 μm GaN buffer layer, a 6-period multi-channel structure (in each period, a single-layer GaN channel layer is 20nm, and an AlGaN barrier layer is 20nm), and an 80nm intrinsic GaN cap layer 5 as an example to explain the preparation method.
The preparation method comprises the following steps:
and S1, obtaining an epitaxial wafer comprising a substrate layer 1, a nucleation layer 2, a buffer layer 3, a heterojunction multi-channel structure 4 and an intrinsic GaN cap layer 5 which are sequentially stacked, and carrying out mesa isolation on the epitaxial wafer.
First, the epitaxial wafer is cleaned, and the structure of the epitaxial wafer is shown in fig. 3 a.
Specifically, the epitaxial material is placed in an acetone solution for 5 minutes by ultrasonic treatment, and organic pollution on the surface layer of the epitaxial wafer is washed away; secondly, placing the epitaxial wafer cleaned by the acetone into an isopropanol solution for ultrasonic cleaning for 5 minutes to remove the acetone solution remained on the surface; then placing the epitaxial wafer in deionized water for washing, and washing off isopropanol attached to the surface of the material; and finally, blowing the surface of the wafer by using high-purity nitrogen. After the organic cleaning of the epitaxial wafer is finished, the material is placed in a BOE solution with the concentration of 1:7 for 30s, an oxide layer on the surface is removed, a large amount of deionized water is used for washing, finally, the deionized water on the surface of the wafer is dried by high-purity nitrogen, and the inorganic cleaning of the epitaxial wafer is finished.
Mesa isolation is then performed on the epitaxial wafer to avoid mutual interference between devices, see fig. 3 b.
Specifically, spin coating, baking, photoetching and developing are carried out on the cleaned epitaxial wafer; etching the region outside the table top of the intrinsic GaN cap layer 5 by a plasma etching ICP method, removing two-dimensional electron gas of the heterojunction multi-channel structure 4, and realizing mutual interaction among all devicesSeparate effects, wherein Cl is used2/BCl3The mixed gas of (1) etching the material, wherein Cl2Flow rate of 10sccm, BCl3The flow is 25sccm, the ICP power is 150W, the RF power is 50W, and the material etching rate is about 55 nm/min; and finally, carrying out organic cleaning on the etched epitaxial wafer, and then blowing the epitaxial wafer to dry by using nitrogen.
S2, etching the intrinsic GaN cap layer 5 at one end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form a cathode groove, and depositing a metal layer in the cathode groove to form a cathode electrode 7, as shown in FIG. 3 c.
Specifically, the epitaxial wafer with the mesa isolation is subjected to spin coating, baking, photoetching and developing; and etching the intrinsic thick GaN cap layer 5 and the heterojunction multi-channel structure 4 of the epitaxial wafer by plasma etching ICP to form a cathode groove, wherein the etching conditions are as follows: by Cl2/BCl3Etching the material with the mixed gas of (1), Cl2Flow rate of 10sccm, BCl3The flow is 25sccm, the ICP power is 150W, the RF power is 50W, and the material etching rate is about 55 nm/min; then, growing a Ti/Al/Ni/Au (22/140/55/45nm) metal layer on the surface of the epitaxial wafer by adopting an electron beam evaporation technology; then, carrying out a photoresist stripping process on the epitaxial wafer on which the metal layer is deposited, and only leaving the metal in the cathode ohmic contact electrode area; and finally, carrying out organic cleaning on the stripped epitaxial wafer, drying the epitaxial wafer by using nitrogen, and annealing the epitaxial wafer at the high temperature of 860 ℃ for 30s in the nitrogen atmosphere at the nitrogen flow rate of 3L/min to form the cathode 7.
S3, etching the intrinsic GaN cap layer 5 at the other end of the epitaxial wafer and the heterojunction multi-channel structure 4 to form an anode groove, as shown in FIG. 3 d.
Specifically, the epitaxial wafer with the ohmic contact cathode is subjected to spin coating, baking, photoetching and developing; then, etching the intrinsic GaN cap layer 5 and the heterojunction multi-channel structure 4 of the epitaxial wafer by using a slow-speed low-damage etching technology to form an anode groove, wherein in the slow-speed etching process, only BCl3 is used as etching gas, Ar is used as process gas, the flow rate of the process gas is set to be 25sccm, the ICP power is biased to be 0W, the RF power is biased to be 55W, the AlGaN material is bombarded by B ions to realize a smaller etching rate and a better etching surface, and the etching rate smaller than 2nm/min is realized by optimizing the gas flow rate and the power bias; then, carrying out organic cleaning on the etched epitaxial wafer, and then drying the epitaxial wafer by using nitrogen; and finally, annealing the etched epitaxial wafer at 450 ℃ for 5min in a nitrogen atmosphere to repair etching damage.
S4, depositing a metal material in the anode groove and on the intrinsic GaN cap layer 5 at one side of the anode groove to form the anode electrode 6 and the anode field plate 8, see fig. 3 e.
Specifically, the epitaxial wafer subjected to the anode groove etching is subjected to spin coating, baking, photoetching and developing; then, removing residual glue of the epitaxial wafer after the photoetching by using a glue applicator; then, growing W/Au (50/150nm) metal on the epitaxial wafer with the anode groove in the groove and on the surface of the intrinsic GaN cap layer 5 near the groove by adopting magnetron sputtering equipment to serve as a Schottky anode and anode field plate metal of the device; then, carrying out photoresist stripping process on the epitaxial wafer with the sputtered metal layer, and only leaving the metal of the anode electrode and the anode field plate region; and finally, carrying out organic cleaning on the stripped epitaxial wafer, then drying the epitaxial wafer by using nitrogen, and annealing the epitaxial wafer for 300s at the high temperature of 450 ℃ in the nitrogen atmosphere to form the anode electrode 6 and the anode field plate 8.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A schottky barrier diode having an intrinsic GaN cap layer and a multi-channel, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a heterojunction multi-channel structure (4), an intrinsic GaN cap layer (5), an anode electrode (6), a cathode electrode (7) and an anode field plate (8), wherein,
the substrate layer (1), the nucleation layer (2), the buffer layer (3), the heterojunction multi-channel structure (4) and the intrinsic GaN cap layer (5) are sequentially stacked;
the anode electrode (6) is arranged at one end of the intrinsic GaN cap layer (5) and the heterojunction multi-channel structure (4) and is in contact with a multi-channel in the heterojunction multi-channel structure (4);
the cathode electrode (7) is positioned at the intrinsic GaN cap layer (5) and the other end of the heterojunction multi-channel structure (4) and is in contact with multiple channels in the heterojunction multi-channel structure (4);
the anode field plate (8) is located on the anode electrode (6) and the intrinsic GaN cap layer (5).
2. The schottky barrier diode with intrinsic GaN cap layer and multi-channel as claimed in claim 1, wherein the heterojunction multi-channel structure (4) comprises a channel layer and a barrier layer alternately stacked in sequence, wherein the bottom channel layer is on the buffer layer (3).
3. The Schottky barrier diode with an intrinsic GaN cap layer and multiple channels according to claim 1, wherein the heterojunction multiple channel structure (4) is an AlGaN/GaN superlattice structure having 2-6 periods.
4. The Schottky barrier diode with the intrinsic GaN cap layer and the multi-channel according to claim 3, wherein the thickness of the AlGaN layer and the thickness of the GaN layer in each period in the heterojunction multi-channel structure (4) are 10-20 nm and 10-100 nm respectively.
5. The schottky barrier diode with the intrinsic GaN cap layer and the multi-channel as claimed in claim 1, wherein the thickness of the intrinsic GaN cap layer (5) is greater than or equal to 10 nm.
6. The Schottky barrier diode with an intrinsic GaN cap layer and a multi-channel of claim 1, wherein the bottom of the anode electrode (6) is located below the upper surface of the bottom channel layer in the heterojunction multi-channel structure (4), and the distance between the bottom of the anode electrode (6) and the upper surface of the bottom channel layer in the heterojunction multi-channel structure (4) is 10-40 nm.
7. The schottky barrier diode with intrinsic GaN cap layer and multi-channel as claimed in claim 1, wherein the length of the anode field plate (8) on the intrinsic GaN cap layer (5) is 1 μm to 4 μm.
8. A method for preparing a Schottky barrier diode with an intrinsic GaN cap layer and multiple channels is characterized by comprising the following steps:
s1, obtaining an epitaxial wafer comprising a substrate layer (1), a nucleation layer (2), a buffer layer (3), a heterojunction multi-channel structure (4) and an intrinsic GaN cap layer (5) which are sequentially stacked, and carrying out mesa isolation on the epitaxial wafer;
s2, etching the intrinsic GaN cap layer (5) at one end of the epitaxial wafer and the heterojunction multi-channel structure (4) to form a cathode groove, and depositing a metal layer in the cathode groove to form a cathode electrode (7);
s3, etching the intrinsic GaN cap layer (5) at the other end of the epitaxial wafer and the heterojunction multi-channel structure (4) to form an anode groove;
s4, depositing metal material in the anode groove and on the intrinsic GaN cap layer (5) at one side of the anode groove to form an anode electrode (6) and an anode field plate (8).
9. The method for preparing a schottky barrier diode with an intrinsic GaN cap layer and multiple channels according to claim 8, wherein the heterojunction multiple channel structure (4) adopts an AlGaN/GaN superlattice structure, and the superlattice structure has 2-6 periods.
10. The method for fabricating a schottky barrier diode with an intrinsic GaN cap layer and a multi-channel as claimed in claim 8, wherein the thickness of the intrinsic GaN cap layer (5) is greater than or equal to 10 nm.
CN202111276721.1A 2021-10-29 2021-10-29 Schottky barrier diode with intrinsic GaN cap layer and multiple channels and preparation method thereof Pending CN114171606A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274865A (en) * 2022-09-26 2022-11-01 晶通半导体(深圳)有限公司 Schottky diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274865A (en) * 2022-09-26 2022-11-01 晶通半导体(深圳)有限公司 Schottky diode

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