CN114171598B - SiC MOSFET device based on boron nitride masking layer and preparation method thereof - Google Patents
SiC MOSFET device based on boron nitride masking layer and preparation method thereof Download PDFInfo
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- 229910052582 BN Inorganic materials 0.000 title claims abstract description 106
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 title claims abstract description 106
- 230000000873 masking effect Effects 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 82
- 239000007924 injection Substances 0.000 claims abstract description 82
- 238000002513 implantation Methods 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910001423 beryllium ion Inorganic materials 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 18
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 98
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 89
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005566 electron beam evaporation Methods 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
The invention discloses a SiC MOSFET device based on a boron nitride masking layer and a preparation method thereof, wherein a P-type boron nitride masking layer is introduced into an epitaxial layer below a P-well injection region and a P + injection region, so that the electric field concentration phenomenon of the bottom corner of a SiC P-well can be relieved, the voltage withstanding characteristic of the device is improved, the reverse electric leakage of the device is reduced, and the effect of the device in switch application is reduced; meanwhile, the existence of the P-type boron nitride masking layer is equivalent to the expansion of the region of the source electrode P +, so that the P-type region of the body diode is enlarged, and the follow current capability when the P-type boron nitride masking layer is used as a parasitic body diode is also enhanced; in addition, the heterojunction formed by the P-type boron nitride masking layer and the N-type epitaxial layer has a carrier injection phenomenon, so that the conduction current of the parasitic body diode can be further improved, and the follow current capability is improved.
Description
Technical Field
The invention belongs to the technical field of MOSFET devices, and particularly relates to a SiC MOSFET device based on a boron nitride masking layer and a preparation method thereof.
Background
In a traditional SiC MOSFET device structure, a drain electrode of the device is generally required to be applied with high voltage, usually hundreds of kilovolts or even thousands of kilovolts, so that an electric field gradually extends and increases towards the inside of the device, and if the inside of the device is flat, the electric field distribution is relatively uniform; when the electric field distribution reaches the bottom angle of the P well, because the angle of the position is approximately 90 degrees, electric field lines can preferentially extend to the position, so that the electric field is concentrated, the electric field peak value of the position can be higher, and when the electric field exceeds the critical breakdown electric field of the material, the phenomenon of early breakdown can occur; that is to say, the bottom corner of the P-well in the active region of the conventional device is prone to generate an electric field concentration phenomenon, which causes the voltage withstanding characteristic of the device to be poor, and reverse leakage to be improved, thereby causing the power consumption of the device in the application of the switch to be large.
In addition, in the structure of the traditional SiC MOSFET device, the area of a PiN diode formed by a source electrode and a drain electrode is small, and the follow current capability of the part serving as a parasitic body diode is weakened, so that the current level of the MOSFET device cannot be matched.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a SiC MOSFET device based on a boron nitride masking layer and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
a boron nitride masking layer based SiC MOSFET device, comprising:
a SiC substrate;
the first N-type SiC epitaxial layer is formed on the SiC substrate;
the P-type boron nitride masking layers are formed in etching regions at two ends of the upper surface of the first N-type SiC epitaxial layer, and the upper surface of each P-type boron nitride masking layer is flush with the upper surface of the first N-type SiC epitaxial layer;
the second N-type SiC epitaxial layer is formed on the first N-type SiC epitaxial layer and the P-type boron nitride masking layer;
a P-well implantation region formed by first ion implantation from the second N-type SiC epitaxial layer on the P-type boron nitride masking layer; the length of the P well injection region is smaller than that of the P type boron nitride masking layer;
an N + implantation region formed by second ion implantation in an upper region of the P-well implantation region, wherein the length of the N + implantation region is smaller than that of the P-well implantation region;
the P + injection region penetrates through the two end parts of the P trap injection region and the N + injection region from top to bottom and is formed by third ion injection;
the source electrode is formed on the N + injection region and a part of the P + injection region;
the gate oxide layer is formed on part of the P + injection region, the P well injection region and the second N-type SiC epitaxial layer;
the grid electrode is formed on the grid oxide layer;
and the drain electrode is formed on the bottom surface of the SiC substrate.
In one embodiment of the invention, the thickness of the P-type boron nitride masking layer is 0.5-1 μm.
In one embodiment of the present invention, the boron nitride is cubic boron nitride.
In one embodiment of the invention, the SiC is 4H-SiC.
In one embodiment of the present invention, the first ions and the third ions are both Al ions, and the second ions are N ions.
A preparation method of a SiC MOSFET device based on a boron nitride masking layer comprises the following steps:
epitaxially growing a first N-type SiC epitaxial layer on the SiC substrate;
etching two end parts of the upper surface of the first N-type SiC epitaxial layer to form a SiC etching area, and depositing a P-type boron nitride masking layer in the SiC etching area;
epitaxially growing a second N-type SiC epitaxial layer on the first N-type SiC epitaxial layer and the P-type boron nitride masking layer;
injecting Al ions into a region, located above the P-type boron nitride masking layer, of the second N-type SiC epitaxial layer to form a P-well injection region; the length of the P well injection region is smaller than that of the P type boron nitride masking layer;
injecting N ions into the upper region of the P well injection region to form an N + injection region, wherein the length of the N + injection region is smaller than that of the P well injection region;
injecting Al ions into two end parts penetrating the P trap injection region and the N + injection region from top to bottom to form a P + injection region;
forming a gate oxide layer on the partial P + injection region, the P well injection region and the second N-type SiC epitaxial layer through thermal oxidation;
forming a source electrode on the N + injection region and a part of the P + injection region;
forming a drain on a bottom surface of the SiC substrate;
and forming a grid electrode on the grid oxide layer.
In an embodiment of the present invention, after the step of forming a source on the N + implantation region and a part of the P + implantation region and before the step of forming a drain on the bottom surface of the SiC substrate, the method further includes:
the temperature is 900-1100 ℃, and the time is 2-5 min.
In one embodiment of the invention, the depositing a P-type boron nitride masking layer in the SiC etch region includes:
depositing a boron nitride epitaxial layer in the SiC etching area, wherein the thickness of the P-type boron nitride masking layer is 0.5-1 mu m;
implanting Be ions into the boron nitride epitaxial layer to form the P-type boron nitride masking layer; wherein the doping concentration of the implanted Be ions is 1 × 10 18 ～1×10 19 cm -3 。
In one embodiment of the invention, the boron nitride is cubic boron nitride; the SiC is 4H-SiC.
In one embodiment of the invention, the source material is Ti/Al/Ni; the drain electrode is made of Ti/Ni; the grid electrode material is Al.
Compared with the prior art, the invention has the beneficial effects that:
according to the SiC MOSFET device based on the boron nitride masking layer and the preparation method thereof, disclosed by the embodiment of the invention, the P-type boron nitride masking layer is introduced into the epitaxial layers below the P well injection region and the P + injection region, so that the electric field concentration phenomenon of the bottom corner of the SiC P well can be relieved, the voltage withstanding characteristic of the device is improved, the reverse electric leakage of the device is reduced, and the effect of the device in the switch application is reduced; meanwhile, the existence of the P-type boron nitride masking layer is equivalent to the expansion of the region of the source electrode P +, so that the P-type region of the body diode is enlarged, and the follow current capability when the P-type boron nitride masking layer is used as a parasitic body diode is also enhanced; in addition, the heterojunction formed by the P-type boron nitride masking layer and the N-type epitaxial layer has a carrier injection phenomenon, so that the conduction current of the parasitic body diode can be further improved, and the follow current capability is improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method for manufacturing a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention;
fig. 3a to fig. 3h are schematic diagrams of a manufacturing process of a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention.
In the figure, 1, a SiC substrate; 2. a first N-type SiC epitaxial layer; 3. a P-type boron nitride masking layer; 4. A second N-type SiC epitaxial layer; 5. a P well injection region; 6. an N + injection region; 7. a P + implantation region; 8. A gate oxide layer; 9. a source electrode; 10. a gate electrode; 11. and a drain electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention, and the SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention includes: the silicon-carbide substrate comprises a SiC substrate 1, a first N-type SiC epitaxial layer 2, a P-type boron nitride masking layer 3, a second N-type SiC epitaxial layer 4, a P well injection region 5, an N + injection region 6, a P + injection region 7, a source electrode 9, a gate oxide layer 8, a gate electrode 10 and a drain electrode 11. Each structural layer of the device is explained below.
A SiC substrate 1, preferably a 4H — SiC substrate 1. The 4H-SiC has larger forbidden band width and good radiation resistance, and is more suitable for power electronic power devices.
And a first N-type SiC epitaxial layer 2 formed on the SiC substrate 1. The first N-type SiC epitaxial layer 2 is also preferably a first N-type 4H-SiC epitaxial layer. The doping ions and doping concentrations of the first N-type SiC epitaxial layer 2 are the same as those of the conventional method, and are not described herein again.
And the P-type boron nitride masking layer 3 is formed in etching regions at two ends of the upper surface of the first N-type SiC epitaxial layer 2, and the upper surface of the P-type boron nitride masking layer 3 is flush with the upper surface of the first N-type SiC epitaxial layer 2. The P-type boron nitride material is an ultra-wide bandgap material, and has higher critical breakdown field strength compared with SiC, so that in a high-power device, the electric field concentration phenomenon of a bottom corner of a SiC P well can be relieved, the voltage withstanding characteristic of the device is improved, the reverse electric leakage of the device is reduced, and the effect of the device in switch application is reduced.
The thickness of the P-type boron nitride mask layer 3 is preferably 0.5 to 1 μm.
The P-type boron nitride mask layer 3 is preferably formed by implanting Be ions into the boron nitride mask layer, and implanting BeThe doping concentration of the ions is 1X 10 18 ～1×10 19 cm -3 。
The boron nitride is preferably cubic boron nitride, the cubic boron nitride is synthesized by hexagonal boron nitride and a catalyst under high temperature and high pressure, and has the excellent performances of high hardness, thermal stability, chemical inertness, good red-transparent appearance, wider forbidden bandwidth and the like, and the characteristics of the materials enable the cubic boron nitride to be more suitable for preparing a high-power device, so that the P-type cubic boron nitride has stronger masking effect when being used as a masking layer in the high-power device, and the device is more effectively protected from being struck by electric field line breakdown.
And a second N-type SiC epitaxial layer 4 formed on the first N-type SiC epitaxial layer 2 and the P-type boron nitride mask layer 3. The second N-type SiC epitaxial layer 4 is preferably a second N-type 4H-SiC epitaxial layer, and the ion implantation and doping concentration of the second N-type SiC epitaxial layer 4 are preferably the same as those of the first N-type SiC epitaxial layer 2.
A P-well implantation region 5 formed by first ion implantation from the second N-type SiC epitaxial layer 4 on the P-type boron nitride masking layer 3; and the length of the P-well implant region 5 is less than the length of the P-type boron nitride masking layer 3. The P-well implant region 5 may be formed by implanting Al ions in the region.
The P-well implantation region 5 is completely formed in the region above the P-type boron nitride masking layer 3, and the length of the P-type boron nitride masking layer 3 is greater than that of the P-well implantation region 5, so that the electric field line can be effectively prevented from being gathered towards the 590-degree angle region of the P-well implantation region, and the breakdown phenomenon is avoided.
And an N + implantation region 6 formed by second ion implantation in an upper region of the P-well implantation region 5, wherein the length of the N + implantation region 6 is smaller than that of the P-well implantation region 5. The N + implantation region 6 may be formed by N ion implantation.
And the P + injection region 7 penetrates through two end parts of the P-well injection region 5 and the N + injection region 6 from top to bottom and is formed by third ion injection. The P + implantation region 7 may be formed by implanting Al ions.
And a source electrode 9 formed on the N + injection region 6 and a part of the P + injection region 7. Specifically, the Ti/Al/Ni source 9 may be formed in the source region on the N + implantation region 6 and a portion of the P + implantation region 7 by a magnetron sputtering or electron beam evaporation process.
And a gate oxide layer 8 formed on the partial P + injection region 7, the P well injection region 5 and the second N-type SiC epitaxial layer 4.
And a gate electrode 10 formed on the gate oxide layer 8. Specifically, the Al gate 10 may be formed on the gate oxide layer 8 by a magnetron sputtering or electron beam evaporation process.
And a drain 11 formed on the bottom surface of SiC substrate 1. Specifically, the Ti/Ni drain electrode 11 may be formed on the bottom surface of the SiC substrate 1 by a magnetron sputtering or electron beam evaporation process.
According to the SiC MOSFET device based on the boron nitride masking layer, disclosed by the embodiment of the invention, the P-type boron nitride masking layer 3 is introduced into the epitaxial layers below the P well injection region 5 and the P + injection region 7, so that the electric field concentration phenomenon of the bottom corner of the SiC P well can be relieved, the voltage withstanding characteristic of the device is improved, the reverse electric leakage of the device is reduced, and the effect of the device in the switch application is reduced; meanwhile, the existence of the P-type boron nitride masking layer 3 is equivalent to the expansion of the region of the source electrode P +, so that the P-type region of the body diode is enlarged, and the follow current capability when the P-type boron nitride masking layer is used as a parasitic body diode is also enhanced; in addition, the heterojunction formed by the P-type boron nitride masking layer 3 and the N-type epitaxial layer has a carrier injection phenomenon, so that the conduction current of the parasitic body diode can be further improved, and the follow current capability is improved.
The following describes a method for manufacturing a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention.
Referring to fig. 2 and fig. 3a to 3h, fig. 2 is a schematic flow chart of a method for manufacturing a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention, and fig. 3a to 3h are schematic diagrams of a process for manufacturing a SiC MOSFET device based on a boron nitride masking layer according to an embodiment of the present invention. The preparation method of the embodiment of the invention comprises the following steps:
s1, a first N-type SiC epitaxial layer 2 is epitaxially grown on a SiC substrate 1, as shown in fig. 3 a.
The SiC substrate 1 is preferably a 4H — SiC substrate 1. The first N-type SiC epitaxial layer 2 is preferably a first N-type 4H-SiC epitaxial layer.
And S2, etching two end parts of the upper surface of the first N-type SiC epitaxial layer 2 to form a SiC etching area, and depositing a P-type boron nitride masking layer 3 in the SiC etching area, as shown in FIG. 3 b.
Illustratively, depositing P-type boron nitride masking layer 3 in the SiC etch region may include:
s21, depositing a boron nitride epitaxial layer in the SiC etching area, wherein the thickness of the P-type boron nitride masking layer 3 is 0.5-1 mu m;
s22, injecting Be ions into the boron nitride epitaxial layer to form a P-type boron nitride masking layer 3; wherein the doping concentration of the implanted Be ions is 1 × 10 18 ～1×10 19 cm -3 。
The material characteristics enable the cubic boron nitride to be more suitable for preparing a high-power device, so that the P-type cubic boron nitride has stronger masking effect when being used as a masking layer in the high-power device, and the device is more effectively protected from being struck by electric field line breakdown.
And S3, epitaxially growing a second N-type SiC epitaxial layer 4 on the first N-type SiC epitaxial layer 2 and the P-type boron nitride mask layer 3, as shown in FIG. 3 c.
The second N-type SiC epitaxial layer 4 is preferably a second N-type 4H-SiC epitaxial layer, and the ion implantation and doping concentration of the second N-type SiC epitaxial layer 4 are preferably the same as those of the first N-type SiC epitaxial layer 2.
S4, injecting Al ions into a region, located above the P-type boron nitride masking layer 3, of the second N-type SiC epitaxial layer to form a P-well injection region 5; and the length of P-well implant 5 is less than the length of P-type boron nitride masking layer 3, as shown in fig. 3 d.
The P-well injection region 5 is completely formed in the region above the P-type boron nitride masking layer 3, and the length of the P-type boron nitride masking layer 3 is greater than that of the P-well injection region 5, so that the electric field can be effectively prevented from being gathered to the 590-degree angle region of the P-well injection region, and the breakdown phenomenon is avoided.
And S5, injecting N ions into the upper region of the P well injection region 5 to form an N + injection region 6, wherein the length of the N + injection region 6 is less than that of the P well injection region 5, as shown in FIG. 3 e.
And S6, injecting Al ions into the two end regions penetrating through the P well injection region 5 and the N + injection region 6 from top to bottom to form a P + injection region 7, as shown in figure 3 f.
And S7, forming a gate oxide layer 8 on the partial P + injection region 7, the P well injection region 5 and the second N type SiC epitaxial layer 4 through thermal oxidation, as shown in figure 3 g.
S8, a source 9 is formed on the N + implant region 6 and a portion of the P + implant region 7, as shown in fig. 3 h.
Specifically, the Ti/Al/Ni source 9 may be formed by sequentially depositing metal Ti, al, and Ni on the N + implantation region 6 and a portion of the P + implantation region 7 of the source by magnetron sputtering or electron beam evaporation.
And S9, forming a drain electrode 11 on the bottom surface of the SiC substrate 1, as shown in FIG. 3 h.
Specifically, the Ti/Ni drain electrode 11 may be formed by depositing metal Ti and Ni in sequence on the bottom surface of the SiC substrate 1 by magnetron sputtering or electron beam evaporation.
S10, a gate 10 is formed on the gate oxide layer 8, as shown in fig. 3 h.
Specifically, the Al gate 10 may be formed by depositing metal Al on the gate oxide layer 8 through a magnetron sputtering or electron beam evaporation process.
Between S9 and S10 may further include:
the temperature is 900-1100 ℃, and the time is 2-5 min.
Namely, the gate 10 is prepared after the device is subjected to the rapid thermal annealing process.
According to the preparation method of the SiC MOSFET device based on the boron nitride masking layer, disclosed by the embodiment of the invention, the P-type boron nitride masking layer 3 is introduced into the epitaxial layer below the P well injection region 5 and the P + injection region 7, so that the electric field concentration phenomenon of the bottom corner of the SiC P well can be relieved, the voltage withstanding property of the device is improved, the reverse electric leakage of the device is reduced, and the effect of the device in the switch application is reduced; meanwhile, the existence of the P-type boron nitride masking layer 3 is equivalent to the expansion of the region of the source electrode P +, so that the P-type region of the body diode is enlarged, and the follow current capability when the P-type boron nitride masking layer is used as a parasitic body diode is also enhanced; in addition, the heterojunction formed by the P-type boron nitride masking layer 3 and the N-type epitaxial layer has a carrier injection phenomenon, so that the conduction current of the parasitic body diode can be further improved, and the follow current capability is improved.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (10)
1. A SiC MOSFET device based on a boron nitride masking layer, comprising:
a SiC substrate;
the first N-type SiC epitaxial layer is formed on the SiC substrate;
the P-type boron nitride masking layers are formed in etching regions at two ends of the upper surface of the first N-type SiC epitaxial layer, and the upper surface of each P-type boron nitride masking layer is flush with the upper surface of the first N-type SiC epitaxial layer;
the second N-type SiC epitaxial layer is formed on the first N-type SiC epitaxial layer and the P-type boron nitride masking layer;
a P-well implantation region formed by first ion implantation from the second N-type SiC epitaxial layer on the P-type boron nitride masking layer; the length of the P well injection region is smaller than that of the P type boron nitride masking layer;
an N + implantation region formed by second ion implantation in an upper region of the P-well implantation region, wherein the length of the N + implantation region is smaller than that of the P-well implantation region;
the P + injection region penetrates through the two end parts of the P trap injection region and the N + injection region from top to bottom and is formed by third ion injection;
the source electrode is formed on the P + injection region and a part of the N + injection region;
the gate oxide layer is formed on part of the N + injection region, the P well injection region and the second N-type SiC epitaxial layer;
the grid electrode is formed on the grid oxide layer;
and the drain electrode is formed on the bottom surface of the SiC substrate.
2. The SiC MOSFET device of claim 1, wherein the P-type boron nitride masking layer has a thickness of 0.5 to 1 μ ι η.
3. The SiC MOSFET device of claim 1, wherein the boron nitride is cubic boron nitride.
4. The SiC MOSFET device of claim 1, wherein the SiC is 4H-SiC.
5. The SiC MOSFET device of claim 1, wherein the first ions and the third ions are both Al ions and the second ions are N ions.
6. A preparation method of a SiC MOSFET device based on a boron nitride masking layer is characterized by comprising the following steps:
epitaxially growing a first N-type SiC epitaxial layer on the SiC substrate;
etching two end parts of the upper surface of the first N-type SiC epitaxial layer to form a SiC etching area, and depositing a P-type boron nitride masking layer in the SiC etching area;
epitaxially growing a second N-type SiC epitaxial layer on the first N-type SiC epitaxial layer and the P-type boron nitride masking layer;
injecting Al ions into a region, located above the P-type boron nitride masking layer, of the second N-type SiC epitaxial layer to form a P-well injection region; the length of the P well injection region is smaller than that of the P type boron nitride masking layer;
injecting N ions into the upper region of the P well injection region to form an N + injection region, wherein the length of the N + injection region is smaller than that of the P well injection region;
injecting Al ions into two end parts which penetrate through the P trap injection region and the N + injection region from top to bottom to form a P + injection region;
forming a gate oxide layer on part of the N + injection region, the P trap injection region and the second N-type SiC epitaxial layer through thermal oxidation;
forming a source electrode on the P + injection region and a part of the N + injection region;
forming a drain on a bottom surface of the SiC substrate;
and forming a grid electrode on the grid oxide layer.
7. The method according to claim 6, further comprising, after the step of forming a source on the P + implant region and a portion of the N + implant region and before the step of forming a drain on the bottom surface of the SiC substrate:
the temperature is 900-1100 ℃, and the time is 2-5 min.
8. The method of claim 6, wherein depositing a P-type boron nitride masking layer in the SiC etched region comprises:
depositing a boron nitride epitaxial layer in the SiC etching area, wherein the thickness of the P-type boron nitride masking layer is 0.5-1 mu m;
implanting Be ions into the boron nitride epitaxial layer to form the P-type boron nitride masking layer; wherein the doping concentration of the implanted Be ions is 1 × 10 18 ～1×10 19 cm -3 。
9. The production method according to claim 6, wherein the boron nitride is cubic boron nitride; the SiC is 4H-SiC.
10. The method according to claim 6, wherein the source material is Ti/Al/Ni; the drain electrode is made of Ti/Ni; the grid electrode material is Al.
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Denomination of invention: A SiC MOSFET Device Based on Boron Nitride Masking Layer and Its Preparation Method Granted publication date: 20230324 Pledgee: Fuyang Zhejiang rural commercial bank Limited by Share Ltd. the Fuchun River branch Pledgor: Zhejiang Xinke Semiconductor Co.,Ltd. Registration number: Y2024980000125 |