CN114171529A - Two-dimensional material heterojunction floating gate memory and preparation method thereof - Google Patents
Two-dimensional material heterojunction floating gate memory and preparation method thereof Download PDFInfo
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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Abstract
The invention provides a two-dimensional material heterojunction floating gate memory, which comprises: a gate layer; an insulating layer covering the gate layer; a plurality of floating gate layers formed on the insulating layer, adjacent two of the plurality of floating gate layers having a space therebetween; a barrier layer formed on the plurality of floating gate layers; a channel layer formed on the barrier layer; the electrode layer comprises a plurality of source electrodes and a plurality of drain electrodes, the channel layer corresponding to each interval is provided with the source electrode or the drain electrode, and one source electrode is arranged between every two adjacent drain electrodes; each floating gate layer includes an enable state that allows storage of electrons and release of electrons, and a disable state that disables storage of electrons and release of electrons; applying a storage bias voltage to the gate layer, wherein electrons in the channel layer tunnel into the floating gate layer in an allowed state, the floating gate layer in the allowed state stores the electrons, and the floating gate layer in a forbidden state does not store the electrons; when a release bias is applied to the gate layer, electrons stored in the floating gate layer in an allowed state tunnel back to the channel layer, and the electrons are released from the floating gate layer in the allowed state.
Description
Technical Field
The embodiment of the invention relates to a floating gate memory, in particular to a two-dimensional material heterojunction floating gate memory and a preparation method thereof.
Background
The integrated circuit industry plays an important role in the development of modern information society. The storage technology is one of the essential technologies in the field, and faces unprecedented challenges in the big data era. Flash memory (NAND), as a representative of memory technology, is approaching its physical limits. The conventional flash memory has problems of slow erasing speed, high power consumption and the like.
Disclosure of Invention
In view of the above, in order to solve at least one technical problem in the above or other aspects of the prior art, the present invention provides a floating gate memory with a novel structure and a method for manufacturing the same, so as to implement fast and low power consumption erasing of the floating gate memory and multi-level storage of the floating gate memory.
In order to solve the technical problems, the invention provides the following technical scheme: in one aspect, the present invention provides a two-dimensional material heterojunction floating gate memory, comprising: the substrate is a gate layer; an insulating layer covering the gate layer; a plurality of floating gate layers formed on the insulating layer, wherein a spacing region is arranged between two adjacent floating gate layers in the plurality of floating gate layers; a barrier layer formed on the plurality of floating gate layers; the channel layer is formed on the barrier layer and is made of two-dimensional semiconductor materials; the electrode layer comprises a plurality of source electrodes and a plurality of drain electrodes, the channel layer corresponding to each interval region is provided with the source electrode or the drain electrode, and one source electrode is arranged between every two adjacent drain electrodes;
wherein each floating gate layer includes an enable state in which storage of electrons and release of electrons are enabled, and a disable state in which storage of electrons and release of electrons are disabled; under the condition of applying a storage bias voltage to the gate layer, electrons of the channel layer tunnel into the floating gate layer in an allowed state, and the floating gate layer in the allowed state stores the electrons; under the condition of applying a releasing bias voltage to the gate layer, the electrons stored by the floating gate layer in the allowed state tunnel back to the channel layer, and the electrons are released by the floating gate layer in the allowed state.
In some embodiments, in the case where one of the plurality of floating gate layers is grounded, the one floating gate layer is in an inhibited state.
In some embodiments, the widths of the respective floating gate layers of the plurality of floating gate layers are not equal.
In some embodiments, the widths of the respective floating gate layers in the plurality of floating gate layers in the preset direction are sequentially decreased.
In some embodiments, the floating gate layer is a two-dimensional material; the barrier layer is a two-dimensional material.
In some embodiments, the floating gate layer comprises one of: MoS2Multilayer graphene (MLG) and MoTe2(ii) a The thickness of the floating gate layer (102) is 1-10 nm.
In some embodiments, the insulating layer comprises one of: SiO 22、SiNx、Al2O3、HfO2AlN; the thickness of the insulating layer is 300nm to 1 μm.
In some embodiments, the barrier layer comprises one of: hexagonal boron nitride (h-BN), HfO2、Al2O3(ii) a The thickness of the barrier layer is 5-20 nm.
In some embodiments, the channel layer has an on-off ratio greater than 103The two-dimensional semiconductor material of (a); the channel layer includes one of: WSe2、MoS2、MoTe2、WS2Black Phosphorus (BP); the thickness of the channel layer is 1 to 20 nm.
In some embodiments, the turn-on voltage of the gate layer is positively correlated to the thickness of the barrier layer, wherein the turn-on voltage is such that the on-off ratio of the channel layer is greater than 103The minimum voltage applied to the gate layer.
The invention also provides a preparation method of the floating gate memory, which comprises the following steps: providing a gate layer; covering an insulating layer on the gate layer; forming a whole floating gate layer on the insulating layer by adopting a CVD (chemical vapor deposition) growth or mechanical dissociation method, and decomposing the whole floating gate layer into a plurality of floating gate layers by adopting electron beam exposure and reactive ion etching; covering the barrier layer on the floating gate layers by adopting a mechanical stripping method; covering the channel layer on the barrier layer by adopting a mechanical stripping method; and forming an electrode layer on the channel layer by adopting electron beam exposure and electron beam evaporation coating methods to obtain the floating gate memory.
According to the two-dimensional material heterojunction floating gate memory provided by the embodiment of the invention, the channel layer is made of a two-dimensional semiconductor material, is sensitive to electrons, has a large on-off ratio, can form a plurality of distinguishable electric conduction states, and meets the characteristic of multilevel storage. By providing a plurality of floating gate layers with unequal widths, the total resistance of the channel layer can be selectively rewritten, so that the floating gate memory can realize multi-level storage.
Drawings
FIG. 1 is a cross-sectional schematic view of a two-dimensional material heterojunction floating gate memory according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an insulating layer formed on a gate layer in a process of fabricating the two-dimensional material heterojunction floating gate memory shown in FIG. 1 according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a plurality of floating gate layers formed on the insulating layer shown in FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a barrier layer formed on the plurality of floating gate layers shown in FIG. 3 according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a channel layer formed on the barrier layer of FIG. 4 in accordance with an embodiment of the present invention;
FIG. 6 is a schematic view of an electrode layer formed on the channel layer shown in FIG. 5 according to an embodiment of the present invention; and
fig. 7 is a flowchart of a method for manufacturing a two-dimensional material heterojunction floating gate memory according to an embodiment of the invention.
[ description of reference ]
100-a gate layer; 101-an insulating layer; 102-a floating gate layer; 103-a barrier layer; 104-a channel layer; 105-electrode layer
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
Novel two-dimensional materials, such as graphene, transition metal sulfides, black phosphorus and the like, have excellent electrical and optical properties, can improve the existing storage technology, and can enable the next generation of low-cost, flexible and wearable storage equipment to become possible.
Based on the inventive concept, the invention provides a two-dimensional material heterojunction floating gate memory and a preparation method thereof.
In one aspect, the invention provides a two-dimensional material heterojunction floating gate memory.
FIG. 1 is a cross-sectional schematic view of a two-dimensional material heterojunction floating gate memory according to an embodiment of the invention.
As shown in fig. 1, a two-dimensional material heterojunction floating gate memory according to an exemplary embodiment of the present invention includes: a substrate, which is a gate layer 100; an insulating layer 101 covering the gate layer 100; a plurality of floating gate layers 102 formed on the insulating layer 101, wherein a spacing region is formed between two adjacent floating gate layers 102 in the plurality of floating gate layers 102; a barrier layer 103 formed on the plurality of floating gate layers 102; a channel layer 104, which is a two-dimensional semiconductor material, formed on the barrier layer 103; and the electrode layer 105 includes a plurality of source electrodes and a plurality of drain electrodes, a source electrode or a drain electrode is disposed on the channel layer 104 corresponding to each spacing region, and one source electrode is disposed between two adjacent drain electrodes.
Further, each floating gate layer 102 includes an enable state that allows storage of electrons and release of electrons, and a disable state that disables storage of electrons and release of electrons; under the condition of applying a storage bias voltage to the gate layer 100, electrons of the channel layer 104 tunnel into the floating gate layer 103 in an allowed state, so that the floating gate layer 102 in the allowed state stores the electrons, and the floating gate layer 102 in a forbidden state does not store the electrons; under the condition of applying a release bias voltage to the gate layer 100, electrons stored in the floating gate layer 102 in an allowed state tunnel back to the channel layer 104, so that the floating gate layer 102 in the allowed state releases the electrons, and the floating gate layer 102 in an inhibited state does not store the electrons; wherein the polarity of the release bias is opposite to that of the storage bias.
According to the two-dimensional material heterojunction floating gate memory of the embodiment of the invention, each floating gate layer 102 in the floating gate layers 102 of the floating gate memory can be in an allowed state or a forbidden state, wherein the allowed state represents that the floating gate layer 102 allows storing and releasing electrons, and the forbidden state represents that the floating gate layer 102 forbids storing and releasing electrons. In the case where one floating gate layer 102 of the plurality of floating gate layers 102 is grounded, the one floating gate layer 102 is in an inhibited state.
In the case where the floating gate layer 102 that controls the inhibited state is grounded, a positive bias is applied to the gate layer 100, electrons in the channel layer 104 tunnel into the floating gate layer 102 that achieves the allowed state, and the floating gate layer 102 that achieves the allowed state stores electrons; with the floating gate layer 102 controlling the inhibit state grounded, a negative bias is applied to the gate layer 100, and electrons stored by the floating gate layer 102 in the enable state tunnel back to the channel layer 104, enabling the floating gate layer 102 in the enable state to release electrons.
According to an embodiment of the invention, a switching ratio greater than 10 is used3The two-dimensional semiconductor material of (a) forms the channel layer 104. Due to the large on-off ratio of the two-dimensional semiconductor material, discrete bit states can be obtained. Particularly, the two-dimensional semiconductor material is sensitive to an electric field which vertically passes through the plane direction of the two-dimensional semiconductor material, has a large on-off ratio, can form a plurality of distinguishable electric conduction states, and meets the characteristic of multi-level storage.
According to an embodiment of the present invention, the widths of the respective floating gate layers 102 of the plurality of floating gate layers 102 are not equal.
According to the embodiment of the invention, the widths of the floating gate layers 102 in the preset direction are sequentially reduced in the plurality of floating gate layers 102.
It should be noted that the operation method of the two-dimensional material heterojunction floating gate memory includes a write operation and an erase operation. Referring to fig. 1, in the write operation, a positive bias is applied to the gate layer 100, a large number of electrons of the channel layer 104 tunnel through the barrier layer 103 and are injected into the floating gate layer 102, so that microsecond-level high-speed write of a state "1" is realized, and after the bias is removed, electrons stored in the floating gate layer 102 cause threshold shift of the floating gate memory device, so as to output high current, so that storage of the state "1" is realized; the erase operation is to effect an erase of state "1" by applying a negative bias on the gate layer 100, with a significant amount of electrons tunneling through the barrier layer 103 back to the channel layer 104. By selecting a particular floating gate layer 102 and keeping the selected floating gate layer 102 grounded, the selected floating gate layer 102 is in a disabled state, and then applying a positive/negative bias to the gate 100, the selected floating gate layer 102 is always kept in a "0" state due to the grounding; while the unselected floating gate layers 102 are in the enable state, the electron storage state of the floating gate layers 102 in the enable state is changed. Since the widths of the floating gate layers 102 are different, the resistances of the channel layers 104 corresponding to the floating gate layers 102 are different, and the total resistance of the channel layers 104 formed in series is controlled by the floating gate layers 102. The weight value of each floating gate layer 102 for regulating the total resistance of the channel layer 104 is different, so that multi-bit regulation of the floating gate memory is realized.
According to the embodiment of the present invention, as shown in fig. 1, the widths of each of the plurality of floating gate layers 102 are not equal, and the storage capacities of each of the floating gate layers 102 for electrons are different. The floating gate memory includes a plurality of floating gate layers 102, for example, N floating gate layers 102, each floating gate layer 102 can be in an enable state or an inhibit state, i.e. 2 can be implementedNAnd storing the state. Because the channel layer 104 is sensitive to the amount of electrons stored in the floating gate layer 102, the amount of electrons stored in the floating gate layer 102 can be reflected by the conductance change of the channel layer 104, and by arranging a plurality of floating gate layers 102 with unequal widths, the total resistance of the channel layer 104 can be selectively rewritten, thereby realizing multi-level storage of the floating gate memory.
As shown in FIG. 1, in an embodiment of the present invention, the floating gate memory includes 3 floating gate layers, the widths of the 3 floating gate layers are sequentially decreased in a predetermined direction, and the floating gate memory can realize 23And 8-level storage is realized.
According to an embodiment of the present invention, the floating gate layer 102 is a two-dimensional material; the barrier layer 103 is a two-dimensional material; the channel layer 104 is a two-dimensional semiconductor material.
According to the embodiment of the invention, the floating gate layer, the barrier layer and the channel layer in the floating gate memory are all two-dimensional materials, so that a heterojunction can be formed by the design, the interface of the heterojunction is flat, the defects are few, the accumulation of electrons at the defects is reduced, the leakage of the electrons is reduced, and the electrons of the floating gate memory can be easily and rapidly written in and erased.
According to an embodiment of the present invention, the floating gate layer 102 is used for storing electrons, and the floating gate layer 102 includes one of: MoS2Multilayer graphene (MLG) and MoTe2For example, the floating gate layer 102 may be multi-layer graphene (MLG), but is not limited thereto.
According to the embodiment of the invention, the thickness of the floating gate layer 102 is 1 to 10nm, for example, the thickness of the floating gate layer 102 may be 1nm, 2nm, 5nm, 8nm, 10nm, but is not limited thereto.
According to an embodiment of the present invention, the floating gate layer 102 may be a single layer of two-dimensional material or may be formed by multiple layers of two-dimensional materials.
According to an embodiment of the present invention, the floating gate layer 102 is formed by CVD growth or mechanical dissociation, but is not limited thereto.
According to an embodiment of the present invention, the material of the gate layer 100 includes a conductive material; the gate layer 100 includes one of: metal electrodes, heavily doped silicon, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, such as, but not limited to, the gate layer 100 being p-type doped silicon or n-type doped silicon.
According to an embodiment of the present invention, the insulating layer 101 includes one of: SiO 22、SiNx、Al2O3、HfO2AlN, e.g. insulating layer 101 of SiO2But is not limited thereto.
According to an embodiment of the present invention, the thickness of the insulating layer 101 is 300nm to 1 μm, for example, the thickness of the insulating layer 101 may be 300nm, 400nm, 600nm, 800nm, 1 μm, but is not limited thereto.
According to the embodiment of the invention, the insulating layer 101 is an insulating medium and is used for preventing the gate layer 100 from contacting the floating gate layer 102, and the arrangement of the insulating layer 101 can prevent electrons of the gate layer 100 from tunneling into the floating gate layer 102 and damaging the floating gate memory.
According to an embodiment of the present invention, the barrier layer 103 is a nanoscale, two-dimensional material, the barrier layer 103 comprising one of: hexagonal boron nitride (h-BN), HfO2、Al2O3For example, the barrier layer 103 may be hexagonal boron nitride (h-BN), but is not limited thereto.
According to the embodiment of the invention, the thickness of the barrier layer 103 is 5 to 20nm, for example, the thickness of the barrier layer 103 may be 5nm, 7nm, 10nm, 15nm, 20nm, but is not limited thereto.
According to an embodiment of the present invention, the turn-on voltage of the gate layer 100 is positively correlated to the thickness of the barrier layer 103. Wherein the turn-on voltage is defined as the turn-on of the channel layer 104The ratio is more than 103The minimum voltage applied by the gate 100. The thinner the thickness of the barrier layer 103 is, the smaller the gate-on voltage of the gate 100 is, the material used for the barrier layer of the heterojunction floating gate memory provided by the embodiment of the invention can be a nanoscale two-dimensional material, the gate layer has low gate-on voltage, and tunneling can be realized by applying a small voltage, so that the power consumption is reduced.
According to an embodiment of the present invention, the channel layer 104 includes one of: WSe2、MoS2、MoTe2、WS2Black Phosphorus (BP), e.g., WSe as channel layer 1042But is not limited thereto.
According to an embodiment of the present invention, the thickness of the channel layer 104 is 1 to 20nm, for example, the thickness of the channel layer 104 may be 1nm, 4nm, 8nm, 12nm, 15nm, 20nm, but is not limited thereto.
According to an embodiment of the present invention, the electrode layer 105 includes a plurality of source electrodes and a plurality of drain electrodes, which are conductive two-dimensional materials or metals.
According to an embodiment of the invention, the material of the electrode layer 105 comprises one of: Ti/Au, Cr/Au, Pt, Al, graphite.
FIG. 2 is a schematic diagram of an insulating layer formed on a gate layer in a process of fabricating the two-dimensional material heterojunction floating gate memory shown in FIG. 1 according to an embodiment of the invention; FIG. 3 is a schematic diagram of a plurality of floating gate layers formed on the insulating layer shown in FIG. 2 according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a barrier layer formed on the plurality of floating gate layers shown in FIG. 3 according to an embodiment of the invention; FIG. 5 is a schematic diagram of a channel layer formed on the barrier layer of FIG. 4 in accordance with an embodiment of the present invention; FIG. 6 is a schematic view of an electrode layer formed on the channel layer shown in FIG. 5 according to an embodiment of the present invention; fig. 7 is a flowchart of a method for manufacturing a two-dimensional material heterojunction floating gate memory according to an embodiment of the invention.
On the other hand, the invention also provides a preparation method of the two-dimensional material heterojunction floating gate memory, as shown in fig. 2-6, the preparation method comprises steps S101 to S106.
In step S101, a gate layer 100 is provided.
In step S102, as shown in fig. 2, an insulating layer 101 is covered on the gate layer 100.
According to an embodiment of the present invention, the insulating layer 101 is formed on the gate layer 100 using a thermal oxidation method.
In step S103, as shown in fig. 3, a plurality of floating gate layers 102 are formed on the insulating layer 101.
According to the embodiment of the invention, the floating gate layer is covered on the surface of the insulating layer 101 by using a CVD growth or mechanical dissociation method to obtain a whole floating gate layer, and then the whole floating gate layer is etched by electron beam Exposure (EBL) and Reactive Ion Etching (RIE) to obtain a plurality of floating gate layers 102.
In step S104, as shown in fig. 4, a barrier layer 103 is formed on the plurality of floating gate layers 102.
According to the embodiment of the invention, the barrier layer 103 is covered on the plurality of floating gate layers 102 by using a mechanical stripping method.
In step S105, as shown in fig. 5, the channel layer 104 is formed on the barrier layer 103.
According to an embodiment of the present invention, the channel layer 104 is covered on the barrier layer 103 by a mechanical lift-off method.
In step S106, as shown in fig. 6, an electrode layer 105 is formed on the channel layer 104 to obtain a floating gate memory.
According to the embodiment of the present invention, an electrode layer 105 is formed on the surface of the channel layer 104 using electron beam Exposure (EBL) and electron beam evaporation coating (EBE), thereby obtaining the two-dimensional material heterojunction floating gate memory structure shown in fig. 1 or 6.
According to an embodiment of the present invention, as shown in fig. 1, n-type doped silicon is used as the gate layer 100; thermal oxidation on n-type doped silicon to form 300nm SiO2As the insulating layer 101; by CVD on SiO2Forming 7.6nm thick multi-layer graphene (MLG) as a floating gate layer, and decomposing the multi-layer graphene (MLG) into a plurality of layers by adopting electron beam exposure and reactive ion etching to form a plurality of floating gate layers 102; forming Al with a thickness of 10nm on the plurality of floating gate layers 1022O3As a barrier layer 103; in Al2O3Black Phosphorus (BP) having a thickness of 15nm is formed as the channel layer 104,graphite was formed on Black Phosphorus (BP) as an electrode layer 105 to obtain BP/Al2O3the/Graphene heterojunction floating gate memory.
According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiments, except that: the material of the channel layer 104 is MoTe2The material of the barrier layer 103 is h-BN to obtain MoTe2the/h-BN/Graphene heterojunction floating gate memory.
According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiments, except that: the material of the floating gate layer 102 is MoTe2The barrier layer 103 is made of h-BN, and the channel layer 104 is made of WSe2To obtain WSe2/h-BN/MoTe2A heterojunction floating gate memory.
According to another embodiment of the present invention, the structure of the two-dimensional material heterojunction floating gate memory has the same technical features as the above embodiments, except that: the material of the floating gate layer 102 is MoS2The barrier layer 103 is made of h-BN, and the channel layer 104 is made of WSe2To obtain WSe2/h-BN/MoS2A heterojunction floating gate memory.
According to the two-dimensional material heterojunction floating gate memory provided by the embodiment of the invention, the channel layer is made of a two-dimensional semiconductor material, is sensitive to electrons, has a large on-off ratio, can form a plurality of distinguishable electric conduction states, and meets the characteristic of multi-level storage. By providing a plurality of floating gate layers with unequal widths, the total resistance of the channel layer can be selectively rewritten, so that the floating gate memory can realize multi-level storage.
According to the two-dimensional material heterojunction floating gate memory provided by the embodiment of the invention, the floating gate layer, the barrier layer and the channel layer are made of two-dimensional materials to form a heterojunction, the interface of the heterojunction is flat, the defects are few, the accumulation of electrons at the defects is reduced, the leakage of electrons is reduced, and the rapid writing and erasing of the electrons are easy.
According to the two-dimensional material heterojunction floating gate memory provided by the embodiment of the invention, the barrier layer is made of a nanoscale two-dimensional material, the starting voltage of the gate layer is low, and electrons can realize tunneling by applying a small voltage, so that the power consumption of the floating gate memory is reduced.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A two-dimensional material heterojunction floating gate memory, comprising:
the substrate is a gate layer;
an insulating layer covering the gate layer;
the floating gate layers are formed on the insulating layer, and a spacing area is arranged between every two adjacent floating gate layers in the floating gate layers;
a barrier layer formed on the plurality of floating gate layers;
the channel layer is formed on the barrier layer and is made of two-dimensional semiconductor materials;
the electrode layer comprises a plurality of source electrodes and a plurality of drain electrodes, the source electrode or the drain electrode is arranged on the channel layer corresponding to each interval region, and one source electrode is arranged between every two adjacent drain electrodes;
wherein each of the floating gate layers includes an enable state in which storage of electrons and release of electrons are enabled, and a disable state in which storage of electrons and release of electrons are disabled;
under the condition of applying a storage bias voltage to the gate layer, electrons of the channel layer tunnel into the floating gate layer in the allowed state, and the floating gate layer in the allowed state stores the electrons;
under the condition of applying a releasing bias voltage to the gate layer, the electrons stored by the floating gate layer in the allowed state tunnel back to the channel layer, and the electrons are released by the floating gate layer in the allowed state.
2. The floating gate memory of claim 1, wherein in the case where one of the plurality of floating gate layers is grounded, the one floating gate layer is in an inhibit state.
3. The floating gate memory of claim 1, wherein the widths of the respective floating gate layers of the plurality of floating gate layers are not equal.
4. The floating gate memory according to claim 3, wherein the widths of the respective floating gate layers in the plurality of floating gate layers in a predetermined direction are sequentially decreased.
5. The floating gate memory of claim 1, wherein the floating gate layer is a two-dimensional material;
the barrier layer is a two-dimensional material.
6. The floating gate memory of claim 1, wherein the floating gate layer comprises one of: MoS2Multilayer graphene (MLG) and MoTe2；
The thickness of the floating gate layer is 1-10 nm;
preferably, the insulating layer comprises one of: SiO 22、SiNx、Al2O3、HfO2、AlN；
The thickness of the insulating layer is 300 nm-1 μm.
7. The floating gate memory of claim 1, wherein the blocking layer comprises one of: hexagonal boron nitride (h-BN), HfO2、Al2O3；
The thickness of the barrier layer is 5-20 nm.
8. The floating gate memory of claim 1 wherein the channel layer has an on-off ratio greater than103The two-dimensional semiconductor material of (a);
the channel layer includes one of: WSe2、MoS2、MoTe2、WS2Black Phosphorus (BP);
the thickness of the channel layer is 1-20 nm.
9. The floating gate memory of claim 1, wherein a turn-on voltage of the gate layer is positively correlated to a thickness of the barrier layer, wherein the turn-on voltage is such that an on-off ratio of the channel layer is greater than 103The minimum voltage applied to the gate layer.
10. The preparation method of the floating gate memory according to any one of claims 1 to 9, comprising the following steps:
providing a gate layer;
covering an insulating layer on the gate layer;
forming a whole floating gate layer on the insulating layer by adopting a CVD (chemical vapor deposition) growth or mechanical dissociation method, and decomposing the whole floating gate layer into a plurality of floating gate layers by adopting electron beam exposure and reactive ion etching;
covering a barrier layer on the plurality of floating gate layers by adopting a mechanical stripping method;
covering a channel layer on the barrier layer by adopting a mechanical stripping method;
and forming an electrode layer on the channel layer by adopting electron beam exposure and electron beam evaporation coating methods to obtain the floating gate memory.
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| CN114597254A (en) * | 2022-05-09 | 2022-06-07 | 华中科技大学 | MoTe2 floating gate transistor, ADC circuit, DCA circuit and method |
| CN114883195A (en) * | 2022-04-03 | 2022-08-09 | 叶宇 | Preparation method of two-dimensional material semiconductor device for detecting target DNA |
| CN115172439A (en) * | 2022-06-30 | 2022-10-11 | 中国科学技术大学 | Two-dimensional material transmission gate mixer and preparation method thereof |
| WO2024036513A1 (en) * | 2022-08-17 | 2024-02-22 | 中国科学技术大学 | Floating-gate memory and preparation method therefor |
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| CN114883195A (en) * | 2022-04-03 | 2022-08-09 | 叶宇 | Preparation method of two-dimensional material semiconductor device for detecting target DNA |
| CN114883195B (en) * | 2022-04-03 | 2024-08-30 | 叶宇 | Two-dimensional material semiconductor device for detecting target DNA and preparation method thereof |
| CN114597254A (en) * | 2022-05-09 | 2022-06-07 | 华中科技大学 | MoTe2 floating gate transistor, ADC circuit, DCA circuit and method |
| CN114597254B (en) * | 2022-05-09 | 2022-08-16 | 华中科技大学 | MoTe 2 Floating gate transistor, ADC circuit, DAC circuit and method |
| CN115172439A (en) * | 2022-06-30 | 2022-10-11 | 中国科学技术大学 | Two-dimensional material transmission gate mixer and preparation method thereof |
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