WO2024036513A1

WO2024036513A1 - Floating-gate memory and preparation method therefor

Info

Publication number: WO2024036513A1
Application number: PCT/CN2022/113064
Authority: WO
Inventors: 左成杰; 苏子佳
Original assignee: 中国科学技术大学
Priority date: 2022-08-17
Filing date: 2022-08-17
Publication date: 2024-02-22

Abstract

Provided in one aspect of the present disclosure are a floating-gate memory and a preparation method therefor. The floating-gate memory comprises: a gate layer, on which an insulating layer, a floating-gate layer, a barrier layer and channel layers are sequentially stacked, wherein the channel layers comprise an n-type channel layer and a p-type channel layer, and the n-type channel layer and the p-type channel layer form a p-n junction; and by means of applying a bias voltage to the gate layer, the channel layers and the floating-gate layer are controlled to jointly realize electron storage and release. In the floating-gate memory, by means of applying different numbers of pulse sequences, the total resistance of channel layers can be selectively rewritten, thereby realizing the multi-level storage function of the floating-gate memory in conjunction with a floating-gate layer.

Description

Floating gate memory and preparation method thereof

Technical field

The present disclosure relates to the field of memory technology, and in particular to a floating gate memory and a preparation method thereof.

Background technique

The growing demand for the storage and analysis of massive data in the modern information society has prompted the development of next-generation processors and storage systems. Since traditional von Neumann architecture computing systems face problems such as slow computing speed, high manufacturing costs, and high power consumption in data transmission between processors and memories, in order to cope with the Internet of Things (IoT) and artificial intelligence (Artificial Intelligence), Various big data issues such as Intelligence (AI) and Cloud Computing force people to create new system architectures to deal with these challenges.

In the integrated storage and computing architecture, the processor and memory are merged together, using their parallel computing capabilities to break the limitations of processor-memory data transmission and solve the problems of slow transmission speed and high power consumption. In such a system, each storage unit acts as a multi-level storage unit that dynamically records and processes information. Compared with binary cells, such multi-level memory cells need to have multiple storage states to provide higher data storage density and processing accuracy. Therefore, it is urgent to find new material architectures as such multi-level memory units.

Contents of the invention

Based on this, on the one hand, the present disclosure provides a floating gate memory, including: a gate layer, an insulating layer, a floating gate layer, a barrier layer and a channel layer are sequentially stacked on the gate layer; the channel layer includes an n-type channel layer And the p-type channel layer, the n-type channel layer and the p-type channel layer form a p-n junction; in which, by applying a bias voltage to the gate layer, the channel layer and the floating gate layer are controlled to store electrons and release electrons together.

According to an embodiment of the present disclosure, the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following: the n-type channel layer is formed on the first region on the barrier layer, and the p-type channel layer is formed on the barrier layer. The second region on the barrier layer is in contact with the surface of the n-type channel layer away from the barrier layer; or the p-type channel layer is formed on the first region on the barrier layer, and the n-type channel layer is formed on the second region on the barrier layer. and is in contact with the surface of the p-type channel layer away from the barrier layer; or the n-type channel layer is formed in the first area on the barrier layer, the p-type channel layer is formed in the second area on the barrier layer, and the n-type channel layer It is arranged in parallel and adjacent contact with the p-type channel layer in the lateral direction; wherein the first region and the second region are different regions.

According to embodiments of the present disclosure, the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following: the n-type channel layer is formed in a first area with a certain interval on the left and right sides of the barrier layer, and the p-type channel layer is formed on the barrier layer. The channel layer is formed in the second area on the barrier layer and is in contact with the surfaces of the n-type channel layers on both sides away from the barrier layer to form an npn vertical bipolar junction transistor (Bipolar Junction Transistor, BJT) type channel; Alternatively, the p-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer, and the n-type channel layer is formed in a second region on the barrier layer and is away from the p-type channel layers on both sides of the barrier layer. surface contact to form a pnp vertical BJT channel; or the n-type channel layer is formed in the first area with a certain distance on the left and right sides of the barrier layer, and the p-type channel layer is formed in the second area on the barrier layer and It is in parallel and adjacent contact with the n-type channel layers on both sides in the lateral direction to form an npn horizontal BJT-type channel; or the p-type channel layer is formed in the first area with a certain interval on the left and right sides of the barrier layer, n The type channel layer is formed in the second region on the barrier layer and is in parallel and adjacent contact with the p-type channel layers on both sides in the lateral direction to form a pnp horizontal BJT type channel, wherein the first region and the second region for different regions.

According to embodiments of the present disclosure, the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following: the n-type channel layer is formed in a first area with a certain interval on the left and right sides of the barrier layer, and the p-type channel layer is formed on the barrier layer. The channel layer is formed in the second area on the barrier layer and is in contact with the surface of the n-type channel layer on both sides away from the barrier layer, and the p-type channel layer is covered with a barrier layer to form an npn vertical metal- Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) type channel; or p-type channel layer is formed in the first area with a certain interval on the left and right sides of the barrier layer, n-type channel layer A second region is formed on the barrier layer and is in contact with the surface of the p-type channel layer on both sides away from the barrier layer, and the n-type channel layer is covered with a barrier layer to form a pnp vertical MOSFET channel; Alternatively, the n-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer, and the p-type channel layer is formed in a second region on the barrier layer and is in a lateral direction with the n-type channel layers on both sides. parallel adjacent contacts, and the p-type channel layer is covered with a barrier layer to form an npn horizontal MOSFET-type channel; or the p-type channel layer is formed in the first area with a certain interval on the left and right sides of the barrier layer, The n-type channel layer is formed in the second area on the barrier layer and is in parallel and adjacent contact with the p-type channel layers on both sides in the lateral direction, and the n-type channel layer is covered with a barrier layer to form a pnp level type MOSFET type channel.

According to an embodiment of the present disclosure, the floating gate layer includes an allowed state that allows storing and releasing electrons, and a forbidden state that prohibits storing and releasing electrons; when a storage bias is applied to the gate layer, electron tunneling of the channel layer Penetrating into the floating gate layer in the allowed state, the floating gate layer in the allowed state stores electrons; when a release bias is applied to the gate layer, the electrons stored in the floating gate layer in the allowed state tunnel back to the channel layer , to realize the floating gate layer in the allowed state to release electrons.

According to embodiments of the present disclosure, when a positive bias voltage is applied to the gate layer, a writing operation of the floating gate memory is realized; when a negative bias voltage is applied to the gate layer, an erasing operation of the floating gate memory is realized.

According to embodiments of the present disclosure, when the floating gate layer is grounded, the floating gate layer is in a disabled state.

According to embodiments of the present disclosure, the material of the insulating layer is one of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO ₂ , and AlN, and the thickness of the insulating layer is 300 nm to 1 μm.

According to embodiments of the present disclosure, the materials of the floating gate layer are all single-layer two-dimensional materials or multi-layer two-dimensional materials, the materials of the barrier layer are all nano-scale two-dimensional materials, and the materials of the n-type channel layer are n-type two-dimensional materials. Two-dimensional semiconductor material, the material of the p-type channel layer is a p-type two-dimensional semiconductor material.

According to embodiments of the present disclosure, the material of the floating gate layer is black phosphorus or multi-layer graphene, and the thickness of the floating gate layer is 0.2-10 nm; the material of the barrier layer is hexagonal lattice boron nitride, HfO ₂ , ZrO ₂ , Al One of ₂ O ₃ , the thickness of the barrier layer is 5~20nm; the material of the n-type channel layer is one of MoS ₂ , MoTe ₂ , WS ₂ , and the material of the p-type channel layer is WSe ₂ , GaSe One of , GeAs, and α-MnS, the thickness of the n-type channel layer and the p-type channel layer is 0.2 to 10 nm.

According to embodiments of the present disclosure, the turn-on voltage of the gate layer is positively related to the thickness of the barrier layer, wherein the turn-on voltage is the minimum voltage applied to the gate layer when the switching ratio of the channel layer is greater than 10 ³ .

A second aspect of the present disclosure also provides a method for preparing a floating gate memory, which is used to prepare the above-mentioned floating gate memory, including: providing a gate layer; and sequentially preparing an insulating layer, a floating gate layer, a barrier layer and a trench on the gate layer. channel layer; the channel layer includes an n-type channel layer and a p-type channel layer, and the n-type channel layer and the p-type channel layer constitute a p-n junction; among them, by applying a bias voltage to the gate layer, the channel layer and The floating gate layer jointly stores and releases electrons.

According to the floating gate memory provided by the embodiment of the present disclosure, an n-type channel layer made of n-type two-dimensional semiconductor material and a p-type channel layer made of p-type two-dimensional semiconductor material are formed on the barrier layer, so that the n-type The p-n junction formed by the channel layer and the p-type channel layer is sensitive to the electric field in a specific direction. Under the control of the electric field, it can form a large switching ratio, and can form multiple distinguishable conductivity states to meet the characteristics of multi-level storage, and then through Applying different numbers of pulse sequences can selectively rewrite the total resistance of the channel layer. Combining the allowed state of the floating gate layer that allows the storage and release of electrons and the forbidden state that prohibits the storage and release of electrons, a floating gate memory can be realized. multi-level storage function.

Furthermore, the structure of the p-n channel layer is set in a variety of implementation methods to better realize the multi-level storage function of the floating gate memory.

Furthermore, by combining the gate layer with the floating gate layer having an allowed state and a disabled state, fast and low-power erasing and writing operations of the floating gate memory are realized.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings needed to describe the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting any creative effort.

FIG. 1 schematically shows a structural diagram of a floating gate memory provided by an embodiment of the present disclosure.

Figure 2 schematically shows a structural diagram of a BJT type channel layer floating gate memory provided by an embodiment of the present disclosure.

FIG. 3 schematically shows a structural diagram of a MOSFET type channel layer floating gate memory provided by an embodiment of the present disclosure.

FIG. 4 schematically shows a flow chart of a floating gate memory preparation method provided by an embodiment of the present disclosure.

FIG. 5A schematically shows a structural diagram of an insulating layer formed on the gate layer in the floating gate memory preparation method provided by an embodiment of the present disclosure.

FIG. 5B schematically shows a structural diagram of forming a floating gate layer on an insulating layer in the floating gate memory preparation method provided by an embodiment of the present disclosure.

FIG. 5C schematically shows a structural diagram of a barrier layer formed on the floating gate layer in the floating gate memory preparation method provided by an embodiment of the present disclosure.

FIG. 5D schematically shows a structural diagram of an n-type channel layer formed on the barrier layer in the floating gate memory preparation method provided by an embodiment of the present disclosure.

FIG. 5E schematically shows a structural diagram of a p-type channel layer formed on the barrier layer in the floating gate memory preparation method provided by an embodiment of the present disclosure.

[Reference symbol]

100-gate layer; 101-insulating layer; 102-floating gate layer; 103-barrier layer; 104-n-type channel layer; 105-p-type channel layer.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The terms "comprising," "comprising," and the like, as used herein, indicate the presence of stated features, steps, operations, and/or components but do not exclude the presence or addition of one or more other features, steps, operations, or components.

In this disclosure, unless otherwise clearly stated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Or integrated; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, it can be indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

In the description of the present disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", The orientation or positional relationship indicated by "inside", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the referred subsystem or element must be Has a specific orientation, is constructed and operates in a specific orientation and therefore is not to be construed as limiting the disclosure.

Throughout the drawings, the same elements are designated by the same or similar reference numerals. Conventional structures or constructions have been omitted when they might obscure the understanding of the present disclosure. Furthermore, the shape, size, and positional relationship of each component in the figure do not reflect the real size, proportion, and actual positional relationship. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Similarly, in the above description of exemplary embodiments of the disclosure, in order to streamline the disclosure and assist in understanding one or more of the various disclosed aspects, various features of the disclosure are sometimes grouped together into a single embodiment, figure, or grouped together. In description. Reference to a description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example includes In at least one embodiment or example of the present disclosure. In this specification, schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

Embodiments of the present disclosure provide a floating gate memory based on two-dimensional material p-n diodes to achieve fast and low-power erasing of the floating gate memory and multi-level storage of the floating gate memory. Detailed introduction will be given below with reference to specific embodiments.

As shown in Figure 1, the floating gate memory may include, for example:

The gate layer 100 can also function as a substrate.

The insulating layer 101 covers the gate layer 100 .

The floating gate layer 102 is formed on the insulating layer 101.

The barrier layer 103 is formed on the floating gate layer 102 .

The channel layer is formed on the barrier layer 103 and includes an n-type channel layer 104 and a p-type channel layer 105 . The n-type channel layer 104 and the p-type channel layer 105 form a p-n junction.

According to embodiments of the present disclosure, a bias voltage is applied to the gate layer to control the channel layer and the floating gate layer to jointly store electrons and release electrons.

In the embodiment of the present disclosure, the positional relationship between the n-type channel layer 104 and the p-type channel layer 105 is:

The n-type channel layer 104 is formed in a first region on the barrier layer 103 , and the p-type channel layer 105 is formed in a second region on the barrier layer 103 and is in contact with the surface of the n-type channel layer 104 away from the barrier layer 103 .

Alternatively, the p-type channel layer 105 is formed in a first region on the barrier layer 103, and the n-type channel layer 104 is formed in a second region on the barrier layer 103 and is in contact with the surface of the p-type channel layer 105 away from the barrier layer 103. .

Alternatively, the n-type channel layer is formed in the first region on the barrier layer, the p-type channel layer is formed in the second region on the barrier layer, and the n-type channel layer and the p-type channel layer are in parallel and adjacent contact in the lateral direction. set up.

Alternatively, the p-type channel layer is formed in the first region on the barrier layer, the n-type channel layer is formed in the second region on the barrier layer, and the n-type channel layer and the p-type channel layer are in parallel and adjacent contact in the lateral direction. set up.

It should be understood that FIG. 1 only shows the n-type channel layer 104 formed in the first region on the barrier layer 103. The p-type channel layer 105 is formed in the second region on the barrier layer 103 and is in contact with the n-type channel layer. 104 is away from the surface contact of the barrier layer 103, the p-type channel layer 105 is formed in the first area on the barrier layer 103, and the n-type channel layer 104 is formed in the second area on the barrier layer 103 and is in contact with the p-type channel layer 104. The situation that the layer 105 is away from the surface contact of the barrier layer 103 and that the n-type channel layer and the p-type channel layer are arranged in parallel and adjacent contact in the lateral direction are not shown. The positional relationship shown in Figure 1 is not used to limit the protection scope of the present disclosure. .

Wherein, the first area and the second area are different areas. The material of the n-type channel layer 104 is an n-type two-dimensional semiconductor material, and the material of the p-type channel layer 105 is a p-type two-dimensional semiconductor material. The surface contact between the p-type channel layer 105 and the n-type channel layer 104 away from the barrier layer 103 can be understood to mean that the p-type channel layer 105 has a three-section structure. The first section is formed in the second area on the barrier layer 103, and the second section is formed in the second area on the barrier layer 103. Three sections are formed on the n-type channel layer 104, and the second section is inclined to connect the first end and the third section. The n-type channel layer and the p-type channel layer are arranged in parallel and adjacent contact in the lateral direction. It can be understood that the n-type channel layer and the p-type channel layer are the same two-dimensional material. The second region is doped differently so that the same two-dimensional material in the first region and the second region presents n-type and p-type. The n-type channel layer and the p-type channel layer are arranged in parallel and adjacent contact in the lateral direction. It can also be understood that the n-type channel layer and the p-type channel layer are the same two-dimensional material. By arranging the first regions on the left and right sides The thickness of the two-dimensional material in the first region and the second region causes the same two-dimensional material in the first region and the second region to exhibit n-type and p-type.

In the embodiment of the present disclosure, the positional relationship between the n-type channel layer 104 and the p-type channel layer 105 can also be:

The n-type channel layer 104 is formed in the first area with a certain distance on the left and right sides of the barrier layer 103. The p-type channel layer 105 is formed in the second area on the barrier layer 103 and is connected to the n-type channel layer 104 on both sides. Contact the surface away from the barrier layer 103 to form an npn vertical BJT channel.

Alternatively, the p-type channel layer 105 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in a second region on the barrier layer 103 and is in contact with the p-type channels on both sides. The layer 105 contacts the surface away from the barrier layer 103 to form a pnp vertical BJT channel.

Alternatively, the n-type channel layer 104 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the p-type channel layer 105 is formed in a second region on the barrier layer 103 and is in contact with the n-type channels on both sides. The layers 104 are in parallel abutting contact in the lateral direction to form an npn horizontal BJT channel.

Alternatively, the p-type channel layer 105 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in a second region on the barrier layer 103 and is in contact with the p-type channels on both sides. The layers 105 are in parallel abutting contact in the lateral direction to form a pnp horizontal BJT channel.

It should be understood that FIG. 2 only shows that the n-type channel layer 104 is formed in the first region with a certain distance on the left and right sides of the barrier layer 103, and the p-type channel layer 105 is formed in the second region on the barrier layer 103 and is connected to the barrier layer 103. When the n-type channel layers 104 on both sides are in contact with the surface of the barrier layer 103, the p-type channel layer 105 is formed in the first area with a certain interval on the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in The second area on the barrier layer 103 is in contact with the surface of the p-type channel layer 105 away from the barrier layer 103 and the n-type channel layer 104 is arranged in parallel contact with the p-type channel layers 105 on both sides in the lateral direction. It is shown that the positional relationship shown in Figure 2 is not used to limit the protection scope of the present disclosure.

The n-type channel layer 104 is formed in the first area with a certain distance on the left and right sides of the barrier layer 103. The p-type channel layer 105 is formed in the second area on the barrier layer 103 and is connected to the n-type channel layer 104 on both sides. The surface contact away from the barrier layer 103 is in contact, and the p-type channel layer 105 is covered with a barrier layer 103 to form an npn vertical MOSFET channel.

Alternatively, the p-type channel layer 105 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in a second region on the barrier layer 103 and is in contact with the p-type channels on both sides. The layer 105 is in contact with the surface away from the barrier layer 103, and the n-type channel layer 104 is covered with a barrier layer 103 to form a pnp vertical MOSFET channel.

Alternatively, the n-type channel layer 104 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the p-type channel layer 105 is formed in a second region on the barrier layer 103 and is in contact with the n-type channels on both sides. The layers 104 are in parallel adjacent contact in the lateral direction, and the p-type channel layer 105 is covered with a barrier layer 103 to form an npn horizontal MOSFET channel.

Alternatively, the p-type channel layer 105 is formed in a first region with a certain distance between the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in a second region on the barrier layer 103 and is in contact with the p-type channels on both sides. The layers 105 are in parallel adjacent contact in the lateral direction, and the n-type channel layer 104 is covered with a barrier layer 103 to form a pnp horizontal MOSFET channel.

It should be understood that FIG. 3 only shows that the n-type channel layer 104 is formed in the first region with a certain distance on the left and right sides of the barrier layer 103, and the p-type channel layer 105 is formed in the second region on the barrier layer 103 and is connected to the barrier layer 103. When the n-type channel layers 104 on both sides are in contact with the surface of the barrier layer 103, the p-type channel layer 105 is formed in the first area with a certain interval on the left and right sides of the barrier layer 103, and the n-type channel layer 104 is formed in The second area on the barrier layer 103 is in contact with the surface of the p-type channel layer 105 away from the barrier layer 103 and the n-type channel layer 104 is arranged in parallel contact with the p-type channel layers 105 on both sides in the lateral direction. It is shown that the positional relationship shown in Figure 3 is not used to limit the protection scope of the present disclosure.

According to an embodiment of the present disclosure, each floating gate layer 102 includes an enable state that allows storing and releasing electrons, and a disable state that prohibits storing and releasing electrons. In other words, the enabled state represents that the floating gate layer 102 allows the storage and release of electrons, and the disabled state represents that the floating gate layer 102 prohibits the storage and release of electrons. Wherein, when the floating gate layer 102 is grounded, the floating gate layer 102 is in a disabled state.

Further, when a storage bias is applied to the gate layer 100, electrons in the channel layer 104 tunnel into the floating gate layer 102 in the allowed state, realizing that the floating gate layer 102 in the allowed state stores electrons, and the floating gate layer 102 in the prohibited state stores electrons. Floating gate layer 102 does not store electrons. When a release bias voltage is applied to the gate layer 100, the electrons stored in the floating gate layer 102 in the allowed state tunnel back to the channel layer 104, causing the floating gate layer 102 in the allowed state to release electrons, and the floating gate layer 102 in the prohibited state can release electrons. Gate layer 102 does not release electrons. The release bias is of opposite polarity than the storage bias.

According to embodiments of the present disclosure, when a positive bias voltage is applied to the gate layer, a writing operation of the floating gate memory is realized, and when a negative bias voltage is applied to the gate layer, an erasing operation of the floating gate memory is realized.

Exemplarily, the writing operation is to apply a forward bias voltage on the gate layer 100, and a large number of electron tunneling blocking layers 103 of the channel layer 104 are injected into the floating gate layer 102 to achieve microsecond-level high-speed writing of state "1". After the bias voltage is removed, the electrons stored in the floating gate layer 102 cause the threshold value of the floating gate memory device to drift, output a high current, and realize the storage of state "1"; the erasing operation is by applying a negative bias voltage on the gate layer 100 , a large number of electrons tunnel through the blocking layer 103 and return to the channel layer 104, realizing the erasure of state “1”.

According to embodiments of the present disclosure, since the materials used for the p-type channel layer and the n-type channel layer are p-type two-dimensional semiconductor materials and n-type two-dimensional semiconductor materials respectively, the p-n junction formed by them has a specific direction (for example, a vertical direction). It is sensitive to electric fields and can form a large switching ratio under the control of electric fields. It can form multiple distinguishable conductivity states to meet the characteristics of multi-level storage. That is, by applying different numbers of pulse sequences to change the amount of electrons stored in the floating gate layer 102, the p-n junction is sensitive to the electric field caused by the electrons stored in the floating gate layer 102 and exhibits different conductivity states. Therefore, the total resistance of the channel layer can be selectively rewritten by applying different sequences of pulses to the gate layer, so that the floating gate memory can achieve multi-level storage.

Because new two-dimensional materials, such as graphene, transition metal sulfides, and black phosphorus, have excellent electrical and optical properties, they can both improve existing storage technologies and enable the next generation of low-cost, flexible, and wearable storage. equipment is possible. Therefore, the embodiments of the present disclosure rationally design the materials and dimensions of each layer structure, as detailed below.

In an embodiment of the present disclosure, the material of the gate layer 100 is a conductive material. Optionally, the material of the gate layer 100 may be one of a metal electrode, heavily doped silicon, gallium arsenide, gallium nitride, silicon carbide, and gallium oxide. For example, the gate layer 100 may be p-type doped silicon. or n-type doped silicon, but is not limited thereto.

In one embodiment of the present disclosure, the insulating layer 101 is an insulating medium used to prevent the gate layer 100 from contacting the floating gate layer 102. The insulating layer 101 can prevent electrons from the gate layer 100 from tunneling into the floating gate layer 102, which affects the floating gate layer. Memory damage. The material of the insulating layer 101 may be one of SiO ₂ , SiN _x , Al ₂ O ₃ , HfO ₂ , and AlN. For example, the insulating layer 101 is SiO ₂ , but it is not limited thereto. The thickness of the insulating layer may be 300 nm to 1 μm. For example, the thickness of the insulating layer 101 may be 300 nm, 400 nm, 600 nm, 800 nm, or 1 μm, but is not limited thereto.

In an embodiment of the present disclosure, the material of the floating gate layer 102 may be a two-dimensional material, a single layer of two-dimensional material, or may be formed of multiple layers of two-dimensional material. Alternatively, the material of the floating gate layer may be black phosphorus (BP) or multilayer graphene (MLG). For example, the floating gate layer 102 is multi-layer graphene (MLG), but is not limited thereto. The thickness of the floating gate layer may be 0.2-10 nm. For example, the thickness of the floating gate layer 102 may be 0.3 nm, 1 nm, 2 nm, 5 nm, 8 nm, or 10 nm, but is not limited thereto.

In an embodiment of the present disclosure, the material of the barrier layer 103 may be a two-dimensional material, and generally a nanometer-scale two-dimensional material is selected. Optionally, the material of the barrier layer 103 may be one of hexagonal lattice boron nitride (h-BN), HfO ₂ , ZrO ₂ , and Al ₂ O ₃ . For example, the barrier layer 103 may be made of hexagonal lattice nitride. Boron (h-BN), but not limited to this. The thickness of the barrier layer may be 5-20 nm. For example, the thickness of the barrier layer 103 may be 5 nm, 7 nm, 10 nm, 15 nm, or 20 nm, but is not limited thereto.

In an embodiment of the present disclosure, the material of the n-type channel layer may be one of MoS ₂ , MoTe ₂ , and WS ₂ . For example, the n-type channel layer 104 is MoS ₂ , but it is not limited thereto. The material of the p-type channel layer may be one of WSe ₂ , GaSe, GeAs, and α-MnS. For example, the p-type channel layer 105 is WSe ₂ , but is not limited thereto. The thickness of the n-type channel layer 104 is 0.2-10 nm. For example, the thickness of the n-type channel layer 104 can be 0.3 nm, 1 nm, 4 nm, or 8 nm, but is not limited thereto. The thickness of the p-type channel layer 105 is 0.2-10 nm. For example, the thickness of the p-type channel layer 105 can be 0.2 nm, 1 nm, 4 nm, or 8 nm, but is not limited thereto.

According to the embodiment of the present disclosure, the floating gate layer 102, the barrier layer 103, the n-type channel layer 104 and the p-type channel layer 105 of the floating gate memory are all two-dimensional materials, forming a heterojunction, and the interface of the heterojunction is smooth. , fewer defects, reducing the accumulation of electrons at defects, which can reduce the leakage of electrons and facilitate rapid writing and erasing of electrons.

According to embodiments of the present disclosure, the turn-on voltage of the gate layer 100 is positively related to the thickness of the barrier layer 103 . The turn-on voltage is defined as the minimum voltage applied to the gate 100 when the switching ratio of the n-type channel layer 104 and the p-type channel layer 105 is greater than 10 ³ . The thinner the thickness of the barrier layer 103, the smaller the turn-on voltage of the gate 100. Therefore, the material used for the barrier layer 103 of the floating gate memory can be a nanoscale two-dimensional material. The turn-on voltage of the gate layer 100 is low, and a small voltage is applied. Tunneling can be achieved and power consumption is reduced.

It should be understood that the material types and size parameters of each layer structure provided by the embodiments of the present disclosure are not arbitrarily selected, but based on the floating gate memory structure provided by the embodiments of the present disclosure, through reasonable design, the performance of the floating gate memory can be further improved. The realization effect of fast and low-power erasing and multi-level storage characteristics of floating gate memory.

Based on the same inventive concept, embodiments of the present disclosure also provide a method for preparing a floating gate memory.

For the convenience of description, in the following, the n-type channel layer 104 is formed in the first area on the barrier layer 103, and the p-type channel layer 105 is formed in the second area on the barrier layer 103 and is away from the n-type channel layer 104. The surface contact of 103 is described as an example.

FIG. 4 schematically shows a flow chart of a floating gate memory preparation method provided by an embodiment of the present disclosure. 5A-5E schematically show structural diagrams corresponding to each operation of the floating gate memory preparation method provided by embodiments of the present disclosure.

Referring to FIG. 4 , combined with FIGS. 5A-5E , the method for preparing a floating gate memory may include operations S201 to S205 , for example.

In operation S201, a gate layer is provided, and an insulating layer is prepared on the gate layer.

In an embodiment of the present disclosure, a thermal oxidation method may be used to prepare the insulating layer 101 on the gate layer 100 . The prepared structure is shown in Figure 5A.

In operation S202, a floating gate layer is prepared on the insulating layer.

In an embodiment of the present disclosure, chemical vapor deposition (CVD) growth or mechanical stripping can be used to cover the floating gate layer on the surface of the insulating layer 101 to obtain a whole floating gate layer, which is then exposed by electron beam ( Electron beam lithography (EBL) and reactive ion etching (RIE) are used to etch the entire floating gate layer to obtain a floating gate layer 102 of a specific shape. The prepared structure is shown in Figure 5B.

In operation S203, a barrier layer is prepared on the floating gate layer.

In an embodiment of the present disclosure, a mechanical peeling method may be used to cover the barrier layer 103 on the floating gate layer 102 . The prepared structure is shown in Figure 5C.

In operation S204, an n-type channel layer is prepared in the first region on the barrier layer.

In an embodiment of the present disclosure, a mechanical peeling method may be used to cover the n-type channel layer 104 to the first area on the barrier layer 103 . The prepared structure is shown in Figure 5D.

In operation S205, a p-type channel layer is prepared in a second region on the barrier layer, and the p-type channel layer is brought into contact with a surface of the n-type channel layer away from the barrier layer.

In an embodiment of the present disclosure, a mechanical peeling method can be used to cover the p-type channel layer 105 to the second area on the barrier layer 103, and keep the p-type channel layer and the n-type channel layer away from the surface of the barrier layer. contact, resulting in floating gate memory. The prepared structure is shown in Figure 5E.

Among them, the material of the n-type channel layer is an n-type two-dimensional semiconductor material, the material of the p-type channel layer is a p-type two-dimensional semiconductor material, the first region and the second region are different regions, and the floating gate layer includes a structure that allows the storage of electrons. and a permitted state for releasing electrons, and a prohibited state for prohibiting storing electrons and releasing electrons. When a storage bias is applied to the gate layer, electrons in the channel layer tunnel into the floating gate layer in the allowed state, allowing the floating gate layer in the allowed state to store electrons; when a release bias is applied to the gate layer , the electrons stored in the floating gate layer in the allowed state tunnel back to the channel layer, causing the floating gate layer in the allowed state to release electrons.

It should be understood that the positional relationship is that the p-type channel layer 105 is formed in the first area on the barrier layer 103, and the n-type channel layer 104 is formed in the second area on the barrier layer 103 and is away from the p-type channel layer 105. The surface contact floating gate layer storage preparation method of 103 is similar to the preparation method shown in Figure 4, except that the preparation sequence of the n-type channel layer 104 and the p-type channel layer 105 is different in the process of preparing the channel layer. No further details will be given here. For details, please refer to the preparation method shown in Figure 4.

It should be understood that the floating gate layer storage preparation method in which the n-type channel layer and the p-type channel layer are arranged in parallel and adjacent contact in the lateral direction are the same as operations S201 to S203 of the preparation method shown in Figure 4, except that: In the process of making the channel layer, the n-type channel layer and the p-type channel layer are made of the same two-dimensional material, and the first and second regions on the left and right sides are doped differently and/or over-set. The thickness of the two-dimensional materials in the first region and the second region on both sides causes the two-dimensional materials in the first region and the second region to exhibit n-type and p-type. No further details will be given here. For details, please refer to the preparation method shown in Figure 4.

It should be understood that the preparation method of the BJT type channel layer floating gate memory is the same as the operations S201 to S203 of the preparation method shown in FIG. Two first regions with a certain distance are defined on both sides. Semiconductor channel layers of the same type are formed in these two first regions, and then a semiconductor channel layer of the opposite type to that of the first region is formed in the second region. The channel layer of the region is in contact with the channel layer of the first region on both sides away from the surface of the barrier layer 103 or the channel layer of the second region is in parallel and adjacent contact with the channel layer of the first region on both sides. This is no longer the case. For details, please refer to the preparation method shown in Figure 4.

It should be understood that the preparation method of the MOSFET-type channel layer floating gate memory is the same as the operations S201 to S203 of the preparation method shown in FIG. Two first regions with a certain distance are defined on both sides. Semiconductor channel layers of the same type are formed in these two first regions, and then a semiconductor channel layer of the opposite type to that of the first region is formed in the second region. The channel layer of the region is in contact with the surface of the first region on both sides away from the barrier layer 103 or the channel layer of the second region is in parallel and adjacent contact with the channel layer of the first region on both sides, and in the third region The channel layer in the two regions is covered with a barrier layer 103, which will not be described in detail here. For details, please refer to the preparation method shown in Figure 4.

Specific examples are listed below to further illustrate the preparation method.

Example 1

The preparation process of the two-dimensional material pn diode floating gate memory is as follows: using n-type doped silicon as the gate layer 100, and using a thermal oxidation method to form 300 nm SiO ₂ as the insulating layer 101 on the n-type doped silicon. CVD is used to grow multi-layer graphene (MLG) with a thickness of 7.6nm on SiO ₂ as a floating gate layer. Electron beam exposure and reactive ion etching are used to etch the multi-layer graphene (MLG) into a specific shape to form a floating gate layer. Gate layer 102. Al ₂ O ₃ with a thickness of 10 nm is formed on the floating gate layer 102 as the barrier layer 103 . MoS ₂ with a thickness of 5 nm is formed on Al ₂ O ₃ as the n-type channel layer 104, WSe ₂ with a thickness of 6 nm is formed on Al ₂ O ₃ as the p-type channel layer 105, and the p-type channel layer is connected to the n-type channel layer 104. Type channel layer edge contact to obtain WSe ₂ -MoS ₂ /Al ₂ O ₃ /MLG two-dimensional material pn diode floating gate memory.

Example 2

The difference between this two-dimensional material pn diode floating gate memory and Example 1 is that: the material of the n-type channel layer 104 is MoTe ₂ , the material of the p-type channel layer 105 is GaSe, and the material of the barrier layer 103 is h-BN. , a GaSe-MoTe ₂ /h-BN/MLG two-dimensional material pn diode floating gate memory was obtained.

Example three

The difference between this two-dimensional material p-n diode floating gate memory and Example 1 is that: the material of the floating gate layer 102 is black phosphorus (BP), the material of the barrier layer 103 is h-BN, and the material of the n-type channel layer 104 is WS2, obtain WSe2-WS2/h-BN/BP two-dimensional material p-n diode floating gate memory.

Example 4

The difference between this two-dimensional material pn diode floating gate memory and Example 1 is that: the material of the floating gate layer 102 is MLG, the material of the barrier layer 103 is Al ₂ O ₃ , and the material of the p-type channel layer 105 is α-MnS. , to obtain α-MnS-MoS ₂ /Al ₂ O ₃ /MLG two-dimensional material pn diode floating gate memory.

Example five

The difference between this two-dimensional material floating gate memory and Example 1 is that the channel layer has a BJT type channel layer structure, in which the n-type channel layer material of the two first areas is MoS ₂ and the second area in the middle is made of MoS 2 . The p-type channel layer is WSe ₂ , and a MoS ₂ -WSe ₂ -MoS ₂ /Al ₂ O ₃ /MLG two-dimensional material BJT type floating gate memory is obtained.

Example 6

The difference between this two-dimensional material floating gate memory and Example 1 is that the channel layer has a MOSFET type channel layer structure, in which the n-type channel layer material of the two first regions is MoS ₂ and the second region in the middle is made of MoS 2 . The p-type channel layer is WSe ₂ , and the p-type channel layer is covered with Al ₂ O ₃ with a thickness of 10 nm to obtain a MoS ₂ -WSe ₂ -MoS ₂ /Al ₂ O ₃ /MLG two-dimensional material MOSFET type floating gate memory.

It should be noted that the floating gate memory preparation method part in the embodiment of the present disclosure corresponds to the floating gate memory structural part in the embodiment of the present disclosure, and its specific implementation details and technical effects are also the same. Herein No longer.

The above-mentioned specific embodiments further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above-mentioned are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

Claims

A floating gate memory, characterized by including:

A gate layer, on which an insulating layer, a floating gate layer, a barrier layer and a channel layer are stacked in sequence;

The channel layer includes an n-type channel layer and a p-type channel layer, and the n-type channel layer and the p-type channel layer form a p-n junction;

Wherein, by applying a bias voltage to the gate layer, the channel layer and the floating gate layer are controlled to jointly store electrons and release electrons.
The floating gate memory according to claim 1, wherein the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following:

An n-type channel layer is formed in a first region on the barrier layer. A p-type channel layer is formed in a second region on the barrier layer and is in contact with a surface of the n-type channel layer away from the barrier layer. ;or

A p-type channel layer is formed in a first region on the barrier layer, and an n-type channel layer is formed in a second region on the barrier layer and is in contact with a surface of the p-type channel layer away from the barrier layer. ;or

An n-type channel layer is formed in a first region on the barrier layer, a p-type channel layer is formed in a second region on the barrier layer, and the n-type channel layer and the p-type channel layer are in Parallel adjacent contact arrangements in the transverse direction;

Wherein, the first area and the second area are different areas.
The floating gate memory according to claim 1, wherein the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following:

An n-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. A p-type channel layer is formed in a second region on the barrier layer and is connected to the n-type channels on both sides. A surface contact of a layer away from the barrier layer to form an npn vertical bipolar junction transistor type channel; or

A p-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. An n-type channel layer is formed in a second region on the barrier layer and is connected to the p-type channels on both sides. A surface contact of a layer away from the barrier layer to form a pnp vertical bipolar junction transistor type channel; or

An n-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. A p-type channel layer is formed in a second region on the barrier layer and is connected to the n-type channels on both sides. The layers are in parallel adjacent contact in the lateral direction to form an npn horizontal bipolar junction transistor type channel; or

A p-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. An n-type channel layer is formed in a second region on the barrier layer and is connected to the p-type channels on both sides. The layers are in parallel adjacent contact in the lateral direction to form a pnp horizontal bipolar junction transistor type channel;

Wherein, the first area and the second area are different areas.
The floating gate memory according to claim 1, wherein the positional relationship between the n-type channel layer and the p-type channel layer includes one of the following: the n-type channel layer is formed on the left and right sides of the barrier layer. There is a first region with a certain interval on both sides, a p-type channel layer is formed in the second region on the barrier layer and is in contact with the surface of the n-type channel layer on both sides away from the barrier layer, and the p-type channel layer The type channel layer is covered with a barrier layer to form an npn vertical metal-oxide semiconductor field effect transistor type channel; or

A p-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. An n-type channel layer is formed in a second region on the barrier layer and is connected to the p-type channels on both sides. The n-type channel layer is in contact with the surface away from the barrier layer, and the n-type channel layer is covered with a barrier layer to form a pnp vertical metal-oxide semiconductor field effect transistor type channel; or

An n-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. A p-type channel layer is formed in a second region on the barrier layer and is connected to the n-type channels on both sides. The layers are in parallel adjacent contact in the lateral direction, and the p-type channel layer is covered with a barrier layer to form an npn horizontal metal-oxide semiconductor field effect transistor type channel; or

A p-type channel layer is formed in a first region with a certain distance between the left and right sides of the barrier layer. An n-type channel layer is formed in a second region on the barrier layer and is connected to the p-type channels on both sides. The layers are in parallel adjacent contact in the lateral direction, and the n-type channel layer is covered with a barrier layer to form a pnp horizontal metal-oxide semiconductor field effect transistor type channel;

Wherein, the first area and the second area are different areas.
The floating gate memory according to claim 1, wherein the floating gate layer includes an allowed state that allows the storage and release of electrons, and a prohibited state that prohibits the storage and release of electrons;

When a storage bias is applied to the gate layer, the electrons in the channel layer tunnel into the floating gate layer in the allowed state, thereby realizing the floating gate layer in the allowed state to store electrons;

When a release bias is applied to the gate layer, the electrons stored in the floating gate layer in the allowed state tunnel back to the channel layer, causing the floating gate layer in the allowed state to release electrons.
The floating gate memory according to claim 1, characterized in that the writing operation of the floating gate memory is realized when a positive bias voltage is applied to the gate layer;

The erasing operation of the floating gate memory is achieved with a negative bias applied to the gate layer.
The floating gate memory according to claim 1, wherein when the floating gate layer is grounded, the floating gate layer is in a disabled state.
The floating gate memory according to claim 1, wherein the material of the insulating layer is one of SiO2 , SiNx , Al2O3 , HfO2 , and AlN, and the thickness of the insulating layer is 300nm. ~1μm.
The floating gate memory according to claim 1, characterized in that the materials of the floating gate layer are all single-layer two-dimensional materials or multi-layer two-dimensional materials, and the materials of the barrier layer are all nano-level two-dimensional materials. , the material of the n-type channel layer is an n-type two-dimensional semiconductor material, and the material of the p-type channel layer is a p-type two-dimensional semiconductor material.
The floating gate memory according to claim 9, characterized in that the material of the floating gate layer is black phosphorus or multi-layer graphene, and the thickness of the floating gate layer is 0.2 to 10 nm;

The material of the barrier layer is one of hexagonal lattice boron nitride, HfO 2 , ZrO 2 , and Al 2 O 3 , and the thickness of the barrier layer is 5 to 20 nm;

The material of the n-type channel layer is one of MoS 2 , MoTe 2 , and WS 2 , and the material of the p-type channel layer is one of WSe 2 , GaSe, GeAs, and α-MnS. The thickness of the n-type channel layer and the p-type channel layer is 0.2-10 nm.
The floating gate memory according to claim 1, wherein the turn-on voltage of the gate layer is positively related to the thickness of the barrier layer, wherein the turn-on voltage is when the switching ratio of the channel layer is greater than 10 3 is the minimum voltage applied to the gate layer.
A method for preparing a floating gate memory, used to prepare the floating gate memory according to any one of claims 1 to 11, characterized in that it includes:

providing a gate layer;

An insulating layer, a floating gate layer, a barrier layer and a channel layer are sequentially prepared on the gate layer;

The channel layer includes an n-type channel layer and a p-type channel layer, and the n-type channel layer and the p-type channel layer form a p-n junction;

Wherein, by applying a bias voltage to the gate layer, the channel layer and the floating gate layer are controlled to jointly store electrons and release electrons.