CN114167256A - Analog measurement device and measurement method based on digital TDR technology - Google Patents
Analog measurement device and measurement method based on digital TDR technology Download PDFInfo
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Abstract
An analog measurement device and a measurement method based on digital TDR technology are used for measuring and calculating the delay information of N channels and carrying out delay correction on measurement data during formal measurement; the device comprises an FPGA module, a pin driver PE corresponding to the multipath channel, an RC filter circuit and an analog-digital converter ADC. The invention solves the problem of insufficient time synchronization precision of the pins of the digital integrated circuit test system by using the low-cost digital TDR technology of analog measurement, can carry out batch automatic test, can conveniently and quickly recalibrate the measurement signals to carry out compensation and correction when the test environment changes, can carry out automatic precision adjustment, can carry out measurement aiming at any path model, and has good universality.
Description
Technical Field
The present invention relates to the field of Automatic Test Equipment (ATE for short), and in particular, to an analog measurement device and a measurement method based on a digital Time Domain Reflectometer (TDR).
Background
With the great progress of science and technology and the wide application in social life, the development of the integrated circuit industry can be said to be new and different day by day. The chip size and operation rate of the chip are greatly improved, and therefore, the production and the test of the integrated circuit are more and more challenged.
Particularly in the test field, as the running speed of the chip is increased, the frequency of a system clock is increased, and the error of a time parameter is allowed to be reduced continuously. In a low-speed test system, the vector period is usually 50ns or 100ns, the steady-state time of the test signal of the test channel is sufficient, and the process of signal transmission inside the channel and the transient process of signal establishment can be basically ignored. However, in high speed systems, the system clock often reaches above 100MHz, and the arrival time of the signal needs to be considered.
That is, the problem of pin time synchronization accuracy, i.e., the problem of time synchronization of a Test vector of each pin (pin) loaded on a chip Under Test (DUT), needs to be focused. Assuming that 2 pins have poor time synchronization and 2 test signals should arrive at the same time, the arrival times differ by 10ns, which is not problematic for a system with a vector period of 100ns, but is likely to be problematic for a system with a vector period of 10ns, which is likely to cause erroneous logic output of the DUT, resulting in DUT test failure. This is a problem caused by insufficient pin time synchronization accuracy, and the higher the speed of the system, the higher the requirement for pin time synchronization accuracy.
The reason for the asynchronous pin time is that the transmission paths of the test signals are different. As is well known, an electrical signal is also one of electromagnetic waves, which propagate in a medium with a certain velocity. The theoretical transmission rate is described by the following equation:
wherein, c0Speed of light, epsilon, in vacuumrRelative dielectric constant, μrRelative magnetic permeability
This equation indicates that the propagation speed of an electrical signal in a medium is lower than that of light in a vacuum. For example, in some 50 Ω coaxial cables the electrical signal travels at approximately 2/3 times the speed of light. Accordingly, the propagation of the electrical signal in the medium also requires a corresponding time. Moreover, similar to sound waves, reflection is also generated when impedance changes occur during transmission, which results in different transmission paths and different transmission times.
In the digital integrated circuit test system, because the test board routing, the connector, the clamp and the like are different, the path difference of each test channel necessarily exists, and the channel time delay is different.
Considering that these propagation delays are unavoidable, some manufacturers tend to concentrate a large amount of signal generation, signal measurement and data processing circuits in the test head closest to the DUT, where the data of the DUT under test is processed at the first time. Nevertheless, the propagation delay and delay variation of the test channel cannot be eliminated at all.
There are also some manufacturers that use external calibration methods. The method comprises the steps of directly measuring the real arrival time difference of pulse signals of all pins on a Device Interface Board (DIB) by using external auxiliary measuring equipment, and correcting the difference to a test channel signal sending end at one time. However, this measurement is time consuming and labor intensive, so these corrections are generally not changed once written to the system. If a user changes the DUT fixture or the DIB according to the test requirement, a new difference is introduced into the transmission delay between the channels, which is a significant limitation.
Therefore, high-end test system manufacturers are urgently required to solve the pin time synchronization accuracy problem.
Disclosure of Invention
The invention aims to provide a low-cost digital TDR technology adopting analog measurement, which solves the problem of insufficient pin time synchronization precision of a digital integrated circuit test system.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an analog measuring device based on digital TDR technology is used for measuring and calculating time delay information (time delay parameters) of N channels and performing time delay correction on measuring data during formal measurement; the FPGA-based multi-channel communication circuit comprises an FPGA module 1, N pin drivers PE2 corresponding to the N channels, an RC filter circuit 3 and an analog-digital converter ADC 4; wherein the content of the first and second substances,
the FPGA module 1 is used for realizing the sending and receiving of the N-channel test signals and the selection of data channels; the system comprises N paths of PWM generators 1-1, N paths of sending signal selectors 1-2, N paths of data sending paths 1-3, N paths of data receiving paths 1-4 and a data path selector 1-5;
the PWM generator 1-1 is used for generating a TDR test pattern of each channel; the transmission signal selector 1-2 of each channel selects a transmission normal test pattern or a TDR test pattern by an enable signal TDR _ EN;
the data transmission path 1-3 of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE 2; wherein, the initialization value of the first programmable delay unit is 0;
each pin driver PE2 is used for carrying out port level conversion on the TDR test pattern of the corresponding channel, and configuring different level thresholds according to a level threshold judgment rule; the pin driver PE2 comprises a receiving channel end cmpl, a sending channel end data and a testing bidirectional channel end;
the data receiving path 1-4 of each channel comprises a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving the measuring signal of the corresponding channel input by the pin driver PE2, and the second programmable delay unit is used for carrying out delay synchronization on the measuring signal of the corresponding channel; the second programmable delay is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
the data path selector 1-5 gates one of the N paths of channels by a selection signal TDR _ DC _ SEL, and transmits the measured TDR signal to an external measurement unit;
the RC filter circuit 3 performs low-pass filtering on the TDR signal after judgment and selection, and converts a duty ratio signal into an analog quantity signal of direct-current voltage;
the analog-to-digital converter ADC4 performs analog-to-digital conversion on the analog signal of the dc voltage filtered by the RC filter circuit 3 to obtain a digitized voltage value, generates determination results with different duty ratios for the TDR reflected signal of the TDR test pattern, and matches the time/voltage coefficient to obtain a measurement result of a corresponding channel.
Further, the FPGA module 1 further includes a parameter configuration unit, where the parameter configuration unit PWM configures the continuous step signal period parameters of the PWM generator 1-1, confirms the period and duty ratio of the TDR test pattern, and sets the threshold level of the pin driver PE 2.
In order to achieve the above object, another technical solution of the present invention is as follows:
a measurement method adopting the analog measurement device based on the digital TDR technology comprises a measurement signal generation step for measuring and calculating the delay information of N channels and a test step for carrying out delay correction on measurement data during formal measurement, wherein the delay information generation step comprises the following steps:
step S1: configuring parameters of an internal module of the FPGA1, including setting parameters of a PWM generator 1-1 and confirming the period and duty ratio of a TDR test pattern; setting a transmission signal selector 1-2, setting TDR _ EN of a test channel to 1, and gating a TDR test pattern; setting a data path selector 1-5, and selecting a required test channel through TDR _ DC _ SEL;
step S2: setting a threshold level of a pin driver PE2, judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel 1-4 of the FPGA module 1 through a pin of the pin driver PE 2; then, the data is output to an external measuring unit through a data path selector 1-5 in a gating mode; wherein, the external measurement unit may include an RC filter circuit 3 and an analog-to-digital converter ADC 4;
step S3: the signal is converted into a direct current level through the RC filter circuit 3, and digital signal conversion is completed at the analog-digital converter ADC 4; obtaining digital voltage corresponding to the TDR signal;
step S4: repeating the step S2, setting different threshold levels, and acquiring digital voltages corresponding to multiple groups of TDR signals of the current channel;
step S5: obtaining a measurement result of the current channel according to a corresponding TDR signal measurement method;
step S6: repeating the steps S1-S5, and measuring the measurement signals of all channels;
step S7: and taking the measurement results of all channels more than or equal to the measurement results of all channels as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit for time delay correction of the measurement data in subsequent normal measurement.
Further, the step S2 specifically includes:
step S21: the PWM generator 1-1 continuously sends a square wave signal S0 with a period T0, wherein the high level width of the square wave signal S0 is Th;
step S22: the square wave signal S0 is sent by the pin driver PE2 and reaches the DUT pin end through the selected test channel, and because the DUT pin end is suspended, R ═ infinity forms a TDR reflection signal, and the source signal and the TDR reflection signal are superimposed to form a signal S1;
step S23: the signal S1 forms a signal S2 after the pin driver PE2 performs a multi-threshold determination process, and the signal S2 generates a time difference Tv between two thresholds according to different comparison thresholds; wherein, Tv comprises two parts of time, one is channel delay Tdly, and the other is voltage rise time;
step S24: and a method of judging a plurality of threshold positions is adopted, the influence of the voltage rise time is eliminated, and the accurate channel delay Tdly is obtained.
Further, the multi-threshold determination process specifically includes:
step S241: the pin driver PE2 uses 1/6 and 5/6 level thresholds, respectively, with a comparison threshold a of 1/6 and a comparison threshold b of 5/6; obtaining a threshold time difference Tv2 according to the method of step S23;
step S242: the pin driver PE2 uses 2/6 and 4/6 level thresholds, respectively, with a comparison threshold a of 2/6 and a comparison threshold b of 4/6; obtaining a threshold time difference Tv1 according to the method of step S23;
step S243: setting the voltage rise time of 1/6-5/6 level threshold and 2/6-4/6 level threshold as negative in the above steps to be the same, and setting the voltage rise time of 3/6-4/6 level threshold and 4/6-5/6 level threshold as negative in the above steps to be the same; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
further, the step S24 is followed by the step S25: and sequentially carrying out time/voltage coefficient verification on each channel in the N channels.
Further, the step S25 specifically includes:
step S251: setting a period of a check pattern as T0, and setting a decision threshold as one of level thresholds 1/6, 2/6, 3/6, 4/6 and 5/6;
step S252: setting the high level time to be Th, and measuring a voltage value by the analog-digital converter ADC4 to be V1;
step S253: resetting the high level time to be Th + delta T, and measuring a voltage value to be V2 by the analog-digital converter ADC 4;
step S254: analysis can show that Δ T corresponds to Δ V ═ V (V2-V1), so Δ T/Δ V results in a coefficient k (ps/mv), i.e., a time/voltage coefficient.
According to the technical scheme, the invention has the following beneficial effects:
firstly, the method is not dependent on an external measurement environment, the implementation method is simple and effective, and the workload is small; the device can be used for batch automatic testing, and when the testing environment changes, the device can conveniently and fast recalibrate the measurement signals to perform compensation and correction.
And secondly, an active probe is not needed, unnecessary interference factors are avoided, and the measurement precision is further improved.
And thirdly, the method has no range limitation, can automatically adjust the precision, can measure any path model and has good general performance.
The method has the advantages of low cost, good effect, high precision related to the clock of the test system and independent of the absolute precision of analog quantity acquisition, and can conveniently improve the measurement precision through clock frequency upgrade so as to meet the constantly changing test requirements.
Drawings
FIG. 1 is a schematic diagram of a TDR signal model
FIG. 2 is a schematic diagram of functional modules of an analog measurement device based on digital TDR technology according to an embodiment of the present invention
FIG. 3 is a schematic diagram of an analog measurement method based on the digital TDR technology in the embodiment of the present invention
FIG. 4 is a diagram illustrating a TDR signal measurement method (using multi-threshold decision principle) according to an embodiment of the present invention
FIG. 5 is a schematic diagram illustrating a principle of time/voltage coefficient verification according to an embodiment of the present invention
Detailed Description
The following description of the present invention will be made in detail with reference to the accompanying drawings 1 to 5.
It should be noted that the low-cost digital TDR technique of analog measurement adopted in the present invention is called Time Domain Reflectometry (Time Domain Reflectometry). TDR is a technique in which a gate determines the state of a system under test in the time domain by evaluating the transmitted and reflected signals. TDR time domain reflectometry is a major tool for measuring transmission line characteristic impedance, and operates in a manner similar to radar positioning.
Referring to fig. 1, fig. 1 is a schematic diagram of a TDR signal model. Assuming that the impedance of the measured path is R, for a step signal, as shown in fig. 1, there are three ideal models for the TDR technique:
when R is infinity (open circuit), the energy of the tail end measuring point is totally reflected back and is superposed with the original signal to form an ascending step signal;
when R is R0 (impedance matching), the transmitted energy is just absorbed by the impedance R at the tail end, no energy is reflected back, and the signal is unchanged;
when R is 0 (short circuit), the end measurement point will generate a negative energy reflection, which is superimposed with the original signal as a down step signal.
The low-cost digital TDR technology adopting analog measurement is based on that when R is infinity, the time parameter of Tdly position is measured, thereby obtaining the measurement signal of the measurement path.
Referring to fig. 2, fig. 2 is a functional block diagram of a TDR measurement circuit according to an embodiment of the present invention. The analog measuring device based on the digital TDR technology is used for measuring and calculating the time delay information of N channels before testing, and carrying out time delay correction on the measured data during formal measurement.
As shown in fig. 2, the analog measurement device based on the digital TDR technology includes a programmable gate array FPGA1, a pin driver PE2 with N channels, an RC filter circuit 3, and an analog-to-digital converter ADC 4.
In an embodiment of the invention, an FPGA module 1 (programmable gate array) is used to implement the sending and receiving of test signals and the selection of data paths. The FPGA1 module mainly comprises a module for realizing the transmission and reception of the test signals of the N channels and the selection of data channels; the system comprises N paths of PWM generators 1-1, N paths of sending signal selectors 1-2, N paths of data sending paths 1-3, N paths of data receiving paths 1-4 and a data path selector 1-5.
The PWM generator 1-1 is used to generate a TDR test pattern for each channel, i.e. a continuous step signal, the period of which is programmable to adapt to different measurement environments or accuracy. The transmission signal selector 1-2 selects whether to transmit the normal test pattern or the TDR test pattern through TDR _ EN, and each channel can individually enable the PWM signal to the test signal output terminal.
The data transmission path 1-3 of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE 2; and the initialization value of the first programmable delay unit is 0.
The data receiving path 1-4 of each channel comprises a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving an external sampling signal input by a pin driver PE2, and the second programmable delay unit is used for carrying out delay synchronization on the external sampling signal; wherein the initialization value of the second programmable delay unit is 0; when the step of generating the measuring signal for measuring and calculating the delay information of the N channels is completed, the value of the second programmable delay unit is a synchronous measuring signal and is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
the data path selector 1-5 gates one of the N paths of channels by a selection signal TDR _ DC _ SEL, and transmits the measured TDR signal to an external measurement unit.
Each pin driver PE2 is configured to perform port level conversion on a TDR test pattern of a corresponding channel, configure different level thresholds according to a level threshold determination rule, perform level decision on a TDR reflected signal of the TDR test pattern, generate a digital logic signal, return to the FPGA1 unit, and perform post-processing.
The pin driver PE2 is used for performing port level conversion on the TDR test pattern of the corresponding channel, configuring different level thresholds according to a level threshold judgment rule, judging a received signal level threshold and the like; the pin driver PE2 comprises a receiving channel end cmpl, a sending channel end data and a testing bidirectional channel end; and port level conversion can be carried out as required, and the functions of three-state output of the TDR test pattern and the like are completed.
Specifically, the pin driver PE2 completes the conversion from the digital level signal to the analog level signal and the control of the tri-state output by configuring different level thresholds. After completion, the signal is output to the N-way transmission signal selector 1-2 inside the FPGA module 1 through the pin (CMPL) of the pin driver PE 2.
The subsequent ADC4 can only perform result calculation and determine the TDR reflected signal to generate different duty ratios after measuring the voltage, thereby obtaining the measurement result of the channel.
And the RC filter circuit 3 (a resistance-capacitance filter circuit) is mainly used for carrying out low-pass filtering on the TDR signals after judgment and selection, and converting the duty ratio signals into direct current voltage for a post-stage circuit to carry out analog quantity acquisition.
And the ADC4 (analog-digital converter) is used for performing low-pass filtering on the TDR signal after judgment and selection, converting the duty ratio signal into an analog quantity signal of direct current voltage, namely the direct current signal after RC filtering, performing analog-digital conversion to obtain a digitized voltage value, entering a post-stage processing module, and converting the digitized voltage value into a time delay result by matching with a time/voltage coefficient.
The analog measurement method based on the digital TDR technology in the embodiment of the invention comprises the following steps:
step S1: configuring parameters of an internal module of the FPGA1, including setting parameters of a PWM generator 1-1 and confirming the period and duty ratio of a TDR test pattern; setting a transmission signal selector 1-2, setting TDR _ EN of a test channel to be 1, and gating a TDR test pattern; data path selectors 1-5 are set to select the desired test path through TDR _ DC _ SEL.
Specifically, the internal module parameters may include setting PWM generator 1-1 parameters, confirming the period and duty cycle of the TDR test pattern; the set transmission signal selector 1-2 selects to transmit the normal test pattern or the TDR test pattern by the enable signal TDR _ EN, for example, by setting the enable signal TDR _ EN of the test channel to 1, gating to transmit the TDR test pattern, or by setting the enable signal TDR _ EN of the test channel to 0, gating to transmit the normal test pattern.
The data path selector 1-5 is set to select the required test path by the selection signal TDR _ DC _ SEL, i.e. one of the N paths of paths is gated by the selection signal TDR _ DC _ SEL, and the measured TDR signal is transmitted to the external measurement unit.
Step S2: setting a threshold level of a pin driver PE2, judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel 1-4 of the FPGA module 1 through a pin of the pin driver PE 2; then, the data is output to an external measuring unit through a data path selector 1-5 in a gating mode; the external measurement unit may include, among other things, an RC filter circuit 3 and an analog-to-digital converter ADC 4.
Step S3: the signal is converted into a direct current level through the RC filter circuit 3, and digital signal conversion is completed at the analog-digital converter ADC 4; and obtaining the digital voltage corresponding to the TDR signal.
Step S4: and repeating the step S2, setting different threshold levels, and acquiring digital voltages corresponding to multiple groups of TDR signals of the current channel.
Step S5: obtaining a measurement result of the current channel according to a corresponding TDR signal measurement method;
step S6: repeating the steps S1-S5, and measuring the measurement signals of all channels;
step S7: and taking the measurement results of all channels more than or equal to the measurement results of all channels as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit for time delay correction of the measurement data in subsequent normal measurement.
Example 1
In the embodiment of the present invention, the key point of the technical solution is a TDR signal measurement method, which is specifically described as follows:
referring to fig. 3, fig. 3 is a schematic diagram illustrating an analog measurement method based on the digital TDR technology according to an embodiment of the present invention. Fig. 3 illustrates the required threshold position, a schematic diagram of signal determination, and a time domain relationship of the determination signal in the TDR signal measurement process.
The TDR signal measurement method is implemented as follows:
step S21: the PWM generator 1-1 continuously transmits a square wave signal S0 with a period T0, wherein the square wave signal S0 has a high level and a width Th.
Step S22: the square wave signal S0 is sent by the pin driver PE2 and reaches the DUT pin terminal of the connector through the selected test channel, and because the DUT pin terminal is suspended, R ═ infinity forms a TDR reflection signal, and the source signal and the TDR reflection signal are superimposed to form a signal S1;
step S23: the signal S1 passes through the comparison unit CMP of the pin driver PE2 to form a signal S2, and the signal S2 generates different determination results according to different comparison thresholds.
As shown in fig. 3, the signal generated by the decision of the comparison threshold a is recorded as S2a, the high level time is Ta, and the signal generated by the decision of the comparison threshold b is recorded as S2b, the high level time is Tb. The time difference between the two thresholds is defined as Tv:
Tv＝(Ta-Tb)/2
wherein Tv comprises two parts of time, one is the channel delay Tdly and one is the voltage rise time.
Step S24: and a method of judging a plurality of threshold positions is adopted, the influence of the voltage rise time is eliminated, and the accurate channel delay Tdly is obtained.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating an implementation flow of multi-threshold determination according to an embodiment of the present invention.
As shown in fig. 4, the multi-threshold determination process includes:
step S241: the pin driver PE2 uses 1/6 and 5/6 level thresholds, respectively, with a comparison threshold a of 1/6 and a comparison threshold b of 5/6; obtaining a threshold time difference Tv2 according to the method of step S23;
step S242: the pin driver PE2 uses 2/6 and 4/6 level thresholds, respectively, with a comparison threshold a of 2/6 and a comparison threshold b of 4/6; in accordance with the method of step S23, a threshold time difference Tv1 is obtained.
As shown in fig. 4, by theoretical analysis, it can be obtained:
step S243: assume that the voltage rise times for the 1/6-5/6 level thresholds and the 2/6-4/6 level thresholds are the same, and the voltage rise times for the 3/6-4/6 level thresholds and the 4/6-5/6 level thresholds are the same; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
thereby, an accurate channel measurement signal can be obtained. Note that TDR signal is superimposed over the reflected signal, Tdly should be 2 times the actual path delay.
It should be noted that the above test procedures are all based on the time parameter calculation, and in step S23, after the signal S2 passes through an external RC filter circuit (low pass filter), the voltage value, not the time value, is actually measured by the ADC 4. Therefore, the time/voltage coefficient of each channel, defined as k, is obtained in (ps/mv) through the time/voltage conversion check.
It is clear to those skilled in the art that the voltage value is always in error during the measurement of the analog-to-digital converter ADC 4. Especially, the signal sent by the common pin of the FPGA1 module, in the test process, the technical scheme of the invention does not actually need to calibrate the high level amplitude of the signal, and only needs to obtain an accurate voltage-time relationship.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a time/voltage coefficient checking principle in an embodiment of the invention. The implementation method for explaining the time/voltage coefficient check by using one of the N channels is as follows:
step S251: setting a period of a check pattern as T0, and setting a decision threshold as 5/6 level threshold;
step S252: setting the high level time to be Th, and measuring a voltage value by the analog-digital converter ADC4 to be V1;
step S253: resetting the high level time to be Th + delta T, and measuring a voltage value to be V2 by the analog-digital converter ADC 4;
step S254: analysis can show that Δ T corresponds to Δ V ═ V (V2-V1), so Δ T/Δ V results in a coefficient k (ps/mv), i.e., a time/voltage coefficient.
It should be noted that the time/voltage coefficient calibration needs to be based on a premise: increasing Δ T only changes the high-low level ratio and does not affect the rising and falling edges, so it is necessary to ensure the completeness of the rising and falling processes before and after the increase, i.e. reserve enough rising and falling time. Also, it should be noted that the time/voltage coefficient calibration coefficients are only applicable to the current T0.
Next, after obtaining the time/voltage coefficient k, the voltage amount measured by the analog-to-digital converter ADC4 may be converted into an amount of time. The measurement signals Tdly for the N-way channels can be obtained separately according to the method used in step S4.
In the practical application process, in order to ensure that the best precision is obtained, a large-range rough measurement is generally carried out, and then the precise measurement is carried out according to the estimated measurement result.
Example 2
The following describes a specific implementation method of the low-cost digital TDR technology using analog measurement according to a preferred embodiment, where the description is performed by a channel and the description of the other steps is not repeated. In addition, in the process of practical application, in order to ensure that the best precision is obtained, a large-range rough measurement is generally carried out, and then the precise measurement is carried out according to the estimated measurement result.
Specifically, the analog measurement method based on the digital TDR technology comprises the following specific implementation steps:
first, the wide range is coarse. As shown in fig. 2, assuming that there are N channels (32-way, 0-31 in the figure), in measuring and calculating the delay information of the N-way channels, for each channel, the measurement channel TDR _ EN is set to 1, and the TDR test pattern is gated. For example, TDR _ DC _ SEL is set to 0, which is gated channel 0 for testing.
As shown in fig. 3, the N-way PWM generator 1-1 is configured, where T0 is set to 100ns, and Th is set to 50 ns; the pin driver PE2 is configured, the threshold a decision level is set to 1/6 × 3.3V (assuming that the PE output signal high level is 3.3V), the ADC measurement voltage is assumed to be 1.848V (the pin output high level of the FPGA is also 3.3V), and the duty ratio of the calculation signal is 1.848/3.3 — 0.56.
That is, the high time is 100 × 0.56 — 56ns, and the high time of the signal S2a can be roughly considered as 50ns +2 × Tdly, so that the rough calculation Tdly is 3ns, and an accurate measurement model of T0 — 20ns can be used.
Second, the enable signal TDR _ EN is set to 0, and the transmission of the TDR test pattern is turned off. Modifying the PWM generator configuration, wherein T0 is 20ns, and Th is 10 ns; the enable signal TDR _ EN is reset to 1 and the subsequent measurement is continued.
Thirdly, checking the coefficient, as shown in fig. 5, measuring T0-20 ns, Th-10 ns, and measuring voltage V1 by the ADC. And repeating the step 2, setting the T0 to be 20ns and the Th to be 15ns, and measuring the voltage V2 by the analog-digital converter ADC 4. The time/voltage coefficient was calculated:
k is 5 × 1000/(V2-V1) × 1000 is 5/(V2-V1) in ps/mv.
Fourthly, the second step is repeated, T0 is set to 20ns, Th is set to 10ns, and accurate measurement is started.
Fifth, as shown in fig. 3, the pin driver PE is configured to set the decision level of the decision threshold a to 1/6 × 3.3V, and the ADC measures the voltage Va. And then, the pin driver PE is reconfigured, the decision level of the threshold b is set to 5/6 × 3.3V, the measurement voltage of the analog-digital converter ADC is Vb, and the measurement voltage difference between the two threshold signals is calculated to be Vab2 ═ Va-Vb)/2.
Sixthly, repeating the fifth step, setting the decision level of the decision threshold a to 2/6 × 3.3V, setting the decision level of the decision threshold b to 4/6 × 3.3V, and calculating the measured voltage difference between the two set decision threshold signals to be Vab 1.
Seventhly, as shown in fig. 3, Tdly ═ 2 × Tv1-Tv 2. Combining the coefficient k, Tdly ═ (2 × Vab1-Vab2) × 1000 × k can be calculated in ps. Thus, the channel measurement result is needed to obtain the double delay parameter of channel 0, i.e., Tdly/2.
Eighth, as shown in fig. 2, the TDR _ DC _ SEL is set to 1 to 31, other test channels are gated, and the measurement results of the N channels can be obtained by repeating the first to seventh steps.
After the test of the measurement signal of each channel is finished, the channel delay compensation technology is combined to carry out synchronous calibration on each channel, so that the time synchronization precision of the pins can be effectively improved, and the accuracy of the subsequent test process is ensured.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (7)
1. An analog measuring device based on digital TDR technology is used for measuring and calculating the delay information of N channels and carrying out delay correction on the measured data during formal measurement; the device is characterized by comprising an FPGA module (1), N pin drivers PE (2) corresponding to the N channels, an RC filter circuit (3) and an analog-digital converter ADC (4); wherein the content of the first and second substances,
the FPGA module (1) is used for realizing the sending and receiving of the N-channel test signals and the selection of data channels; the device comprises N paths of PWM generators (1-1), N paths of sending signal selectors (1-2), N paths of data sending paths (1-3), N paths of data receiving paths (1-4) and a data path selector (1-5);
the PWM generator (1-1) is used for generating a TDR test pattern of each channel; the transmission signal selector (1-2) of each channel selects a transmission normal test pattern or a TDR test pattern by an enable signal TDR _ EN;
the data transmission path (1-3) of each channel comprises a first programmable delay unit and a transmission logic resource unit, wherein the first programmable delay unit is used for carrying out delay synchronization on a normal test pattern of the channel during normal test, and the transmission logic resource unit is used for transmitting the TDR test pattern or the normal test pattern to a pin driver PE (2); wherein, the initialization value of the first programmable delay unit is 0;
each pin driver PE (2) is used for carrying out port level conversion on the TDR test pattern of the corresponding channel, and configuring different level thresholds according to a level threshold judgment rule; the pin driver PE (2) comprises a receiving channel end cmpl, a sending channel end data and a testing bidirectional channel end;
the data receiving path (1-4) of each channel comprises a receiving logic resource unit and a second programmable delay unit, wherein the logic resource unit is used for receiving the measuring signals of the corresponding channel input by the pin driver PE (2), and the second programmable delay unit is used for carrying out delay synchronization on the measuring signals of the corresponding channel; the second programmable delay is used for carrying out delay synchronization on the normally received test data of the channel during normal test;
the data path selector (1-5) gates one of the N paths of channels by a selection signal TDR _ DC _ SEL, and transmits the measured TDR signal to an external measurement unit;
the RC filter circuit (3) performs low-pass filtering on the TDR signal after judgment and selection, and converts a duty ratio signal into an analog quantity signal of direct-current voltage;
and the analog-digital converter ADC (4) performs analog-digital conversion on the analog quantity signal of the direct-current voltage filtered by the RC filter circuit (3) to obtain a digitized voltage value, generates judgment results of different duty ratios on the TDR reflection signal of the TDR test pattern, and matches with a time/voltage coefficient to obtain a measurement signal of a corresponding channel.
2. Analog measurement device based on digital TDR technology according to claim 1, characterized by the FPGA module (1) further comprising a parameter configuration unit PWM configuring successive step signal period parameters of the PWM generator (1-1), confirming the period and duty cycle of the TDR test pattern, and setting the threshold level of the pin driver PE (2).
3. A measurement method using the analog measurement device based on the digital TDR technology of claim 1, comprising a measurement signal generation step for measuring and calculating the delay information of N-channel channels and a test step for performing delay correction on the measurement data during formal measurement, wherein the delay information generation step comprises:
step S1: configuring parameters of an internal module of the FPGA1, including setting parameters of a PWM generator 1-1 and confirming the period and duty ratio of a TDR test pattern; setting a transmission signal selector 1-2, setting TDR _ EN of a test channel to 1, and gating a TDR test pattern; setting a data path selector 1-5, and selecting a required test channel through TDR _ DC _ SEL;
step S2: setting a threshold level of a pin driver PE2, judging a received TDR signal, and transmitting a TDR signal result fed back by a connector to a data receiving channel 1-4 of the FPGA module 1 through a pin of the pin driver PE 2; then, the data is output to an external measuring unit through a data path selector 1-5 in a gating mode; wherein, the external measurement unit may include an RC filter circuit 3 and an analog-to-digital converter ADC 4;
step S3: the signal is converted into a direct current level through the RC filter circuit 3, and digital signal conversion is completed at the analog-digital converter ADC 4; obtaining digital voltage corresponding to the TDR signal;
step S4: repeating the step S2, setting different threshold levels, and acquiring digital voltages corresponding to multiple groups of TDR signals of the current channel;
step S5: obtaining a measurement result of the current channel according to a corresponding TDR signal measurement method;
step S6: repeating the steps S1-S5, and measuring the measurement signals of all channels;
step S7: and taking the measurement results of all channels more than or equal to the measurement results of all channels as time delay parameters for synchronization, and inputting the time delay parameters for synchronization into the first programmable time delay unit and the second programmable time delay unit for time delay correction of the measurement data in subsequent normal measurement.
4. The analog measurement method based on the digital TDR technology of claim 3, wherein the step S2 specifically includes:
step S21: the PWM generator 1-1 continuously sends a square wave signal S0 with a period T0, wherein the high level width of the square wave signal S0 is Th;
step S22: the square wave signal S0 is sent by the pin driver PE2 and reaches the DUT pin end through the selected test channel, and because the DUT pin end is suspended, R ═ infinity forms a TDR reflection signal, and the source signal and the TDR reflection signal are superimposed to form a signal S1;
step S23: the signal S1 forms a signal S2 after the pin driver PE2 performs a multi-threshold determination process, and the signal S2 generates a time difference Tv between two thresholds according to different comparison thresholds; wherein, Tv comprises two parts of time, one is channel delay Tdly, and the other is voltage rise time;
step S24: and a method of judging a plurality of threshold positions is adopted, the influence of the voltage rise time is eliminated, and the accurate channel delay Tdly is obtained.
5. The analog measurement method based on the digital TDR technology of claim 4, wherein the multi-threshold decision process specifically comprises:
step S241: the pin driver PE2 uses 1/6 and 5/6 level thresholds, respectively, with a comparison threshold a of 1/6 and a comparison threshold b of 5/6; obtaining a threshold time difference Tv2 according to the method of step S23;
step S242: the pin driver PE2 uses 2/6 and 4/6 level thresholds, respectively, with a comparison threshold a of 2/6 and a comparison threshold b of 4/6; obtaining a threshold time difference Tv1 according to the method of step S23;
step S243: setting the voltage rise time of 1/6-5/6 level threshold and 2/6-4/6 level threshold as negative in the above steps to be the same, and setting the voltage rise time of 3/6-4/6 level threshold and 4/6-5/6 level threshold as negative in the above steps to be the same; tdly can be calculated using the following method:
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
6. the analog measuring method based on digital TDR technology of claim 4, characterized in that said step S24 is followed by the step S25: and sequentially carrying out time/voltage coefficient verification on each channel in the N channels.
7. The analog measurement method based on the digital TDR technology of claim 6, wherein the step S25 specifically comprises:
step S251: setting a period of a check pattern as T0, and setting a decision threshold as one of level thresholds 1/6, 2/6, 3/6, 4/6 and 5/6;
step S252: setting the high level time to be Th, and measuring a voltage value by the analog-digital converter ADC4 to be V1;
step S253: resetting the high level time to be Th + delta T, and measuring a voltage value to be V2 by the analog-digital converter ADC 4;
step S254: analysis can show that Δ T corresponds to Δ V ═ V (V2-V1), so Δ T/Δ V results in a coefficient k (ps/mv), i.e., a time/voltage coefficient.
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