CN114156383B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN114156383B
CN114156383B CN202111468676.XA CN202111468676A CN114156383B CN 114156383 B CN114156383 B CN 114156383B CN 202111468676 A CN202111468676 A CN 202111468676A CN 114156383 B CN114156383 B CN 114156383B
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layer
type
gettering
away
functional layer
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CN114156383A (en
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伏兵
嵇庆培
马英杰
蔡和勋
许宗琦
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Xiamen Changelight Co Ltd
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Xiamen Changelight Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a semiconductor substrate having opposing first and second surfaces; the epitaxial structure is arranged on the first surface and is provided with a plurality of layers of first gettering layers and second gettering layers which are alternately arranged; the first functional layer is arranged on one side surface of the epitaxial structure, which is away from the first surface; the active layer is arranged on the surface of the first functional layer, which is away from the epitaxial structure; the second functional layer is arranged on the surface of the active layer, which is away from the first functional layer. Therefore, the scheme adopts the first gettering layers and the second gettering layers which are alternately arranged to replace the traditional GaAs buffer layer, so that the influence of substrate defects and impurities on the external structure can be weakened, the background impurity concentration and oxygen element residues in the reaction chamber environment can be reduced, conditions are provided for growing high-quality epitaxial materials, and meanwhile, the cost and the growth time are reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
Along with the continuous development of semiconductor technology, semiconductor devices are developed towards high power and high brightness, and taking an LED as an example, the LED has the advantages of small volume, light weight, less heat productivity, low power consumption, long service life, good monochromaticity, high response speed, environmental protection, good shock resistance and the like, so that the LED is widely applied to various fields. Along with the continuous progress of scientific technology, the living concept of people is changed, and the quaternary system AlGaInP (aluminum gallium indium phosphide) yellow-green light emitting diode is widely applied to various fields such as signal indication, traffic indication, automobile illumination, special illumination and the like. The quaternary system AlGaInP material has the advantages that as the wavelength is shortened, the Al component of the active layer is continuously increased, and the combination of Al atoms and oxygen or carbon atoms causes serious lattice defects of the material, so that the luminous efficiency is reduced; on the other hand, the energy band of the yellow-green light is gradually converted into an indirect energy gap from a direct energy gap due to the increase of the proportion of the Al component, so that the internal quantum efficiency is greatly reduced, and the light efficiency of the LED product in the yellow-green light wave band is lower; meanwhile, when the metal organic vapor deposition (MOCVD) technology is used for production, the edge performance of the epitaxial wafer after growth is poor due to poor epitaxial deposition efficiency of the edge of the slide glass disc, the production yield is low, and the problems are more obvious in a yellow-green light wave band with a more limited process window.
In the prior art, for a high-brightness 570nm led, in order to achieve the wavelength during epitaxial growth, an AlGaInP quaternary quantum well with a high Al component is required, and because oxygen element is easily absorbed by Al to form deep level defects, the internal quantum efficiency is affected, and in order to reduce the effect, a method of prolonging the pre-baking time is generally adopted to reduce the oxygen content in a reaction chamber, but the cost and the productivity are greatly affected.
Disclosure of Invention
In view of this, the present application provides a semiconductor device and a method for manufacturing the same, which not only can weaken the influence of substrate defects and impurities on the external structure, but also can reduce the background impurity concentration and oxygen element residue in the reaction chamber environment, and provide conditions for producing high-quality epitaxial materials.
In order to achieve the above object, the present invention provides the following technical solutions:
a semiconductor device, the semiconductor device comprising:
a semiconductor substrate having opposing first and second surfaces;
The epitaxial structure is arranged on the first surface and is provided with a plurality of layers of first gettering layers and second gettering layers which are alternately arranged;
The first functional layer is arranged on one side surface of the epitaxial structure, which is away from the first surface;
The active layer is arranged on the surface of the first functional layer, which is away from the epitaxial structure;
the second functional layer is arranged on the surface of the active layer, which is away from the first functional layer.
Preferably, in the semiconductor device, the epitaxial structure has 2-20 layers of alternately arranged first gettering layers and second gettering layers.
Preferably, in the semiconductor device, the first gettering layer and the second gettering layer are both N-type gettering layers.
Preferably, in the semiconductor device, the first gettering layer is an AlAs layer, and the second gettering layer is a GaAs layer;
or the first gettering layer is an AlAs layer, and the second gettering layer is an Al xGa1-x As layer; wherein x is more than or equal to 0 and less than or equal to 1;
Or the first gettering layer is an (Al yGa1-y)0.5In0.5 P layer) layer, and the second gettering layer is an (Al zGa1-z)0.5In0.5 P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
Preferably, in the semiconductor device, the thickness of the first gettering layer is 2-50nm; the thickness of the second gettering layer is 2-50nm.
Preferably, in the semiconductor device, the semiconductor substrate is an N-type GaAs substrate having a crystal orientation <100> biased toward <111> a by 2 degrees to 15 degrees.
Preferably, in the semiconductor device, the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer;
Or the first functional layer is a P-type functional layer, and the second functional layer is an N-type functional layer.
Preferably, in the semiconductor device, the first functional layer is an N-type functional layer, and the N-type functional layer includes:
The corrosion stop layer is arranged on the surface of the epitaxial structure, which is away from the semiconductor substrate;
the N-type ohmic contact layer is arranged on the surface of the corrosion cut-off layer, which is away from the epitaxial structure;
the coarsening layer is arranged on the surface of the N-type ohmic contact layer, which is away from the corrosion cut-off layer;
the N-type current expansion layer is arranged on the surface of the coarsening layer, which is away from the N-type ohmic contact layer;
the N-type limiting layer is arranged on the surface of the N-type current expansion layer, which is away from the roughened layer.
Preferably, in the semiconductor device, the second functional layer is a P-type functional layer, and the P-type functional layer includes:
the P-type limiting layer is arranged on the surface of the active layer, which is away from the first functional layer;
the P-type current expansion layer is arranged on the surface of the P-type limiting layer, which is away from the active layer;
And the P-type ohmic contact layer is arranged on the surface of the P-type current expansion layer, which is away from the P-type limiting layer.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
arranging an epitaxial structure on the first surface, wherein the epitaxial structure is provided with a plurality of layers of alternately arranged first gettering layers and second gettering layers;
a first functional layer is arranged on the surface of one side of the epitaxial structure, which is away from the first surface;
an active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer;
and a second functional layer is arranged on the surface, away from the first functional layer, of the active layer.
As can be seen from the above description, in the semiconductor device and the manufacturing method thereof provided by the technical solution of the present invention, the semiconductor device includes: a semiconductor substrate having opposing first and second surfaces; the epitaxial structure is arranged on the first surface and is provided with a plurality of layers of first gettering layers and second gettering layers which are alternately arranged; the first functional layer is arranged on one side surface of the epitaxial structure, which is away from the first surface; the active layer is arranged on the surface of the first functional layer, which is away from the epitaxial structure; the second functional layer is arranged on the surface of the active layer, which is away from the first functional layer.
According to the scheme, the first gettering layers and the second gettering layers which are alternately arranged are adopted to replace the traditional GaAs buffer layer, so that the influence of substrate defects and impurities on an epitaxial structure can be weakened, the background impurity concentration and oxygen element residues of the reaction chamber environment can be reduced, conditions are provided for producing high-quality epitaxial materials, and meanwhile, the cost and the growth time are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and are not intended to limit the scope of the application, since any modification, variation in proportions, or adjustment of the size, etc. of the structures, proportions, etc. should be considered as falling within the spirit and scope of the application, without affecting the effect or achievement of the objective.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;
fig. 3-6 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, however, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As described in the background art, with the continuous development of semiconductor technology, semiconductor devices are developed towards high power and high brightness, and LED is taken as an example:
For high brightness 570nm led: in epitaxial growth, to achieve the wavelength, an AlGaInP quaternary quantum well with high Al component is needed, and oxygen element is easily absorbed by Al to form deep level defects, so that internal quantum efficiency is influenced, and in order to reduce the influence, a pre-baking method is generally adopted to reduce the oxygen content in a reaction chamber. Residual oxygen in the reaction chamber can be basically removed by high temperature and long-time baking, but the cost and the productivity are greatly affected.
Whereas for high power infrared LEDs: the infrared high-power chip has high working temperature and high requirements on the crystal quality and stability of each epitaxial layer, and the doping elements and the concentration of each epitaxial layer need to be accurately controlled in epitaxial growth, so that the background impurity concentration and the lattice defects are particularly important. A method of prebaking and controlling the defect density of the substrate is generally employed. The method for controlling the defect density of the substrate is to purchase a substrate with low defect density from a substrate supplier, and the substrate with low defect density has less proportion and high technical difficulty in the process of growing the crystal on the substrate, so that the price is often more than one time of that of a conventional substrate.
In view of this, the present invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device including:
a semiconductor substrate having opposing first and second surfaces;
The epitaxial structure is arranged on the first surface and is provided with a plurality of layers of first gettering layers and second gettering layers which are alternately arranged;
The first functional layer is arranged on one side surface of the epitaxial structure, which is away from the first surface;
The active layer is arranged on the surface of the first functional layer, which is away from the epitaxial structure;
the second functional layer is arranged on the surface of the active layer, which is away from the first functional layer.
According to the scheme, the first gettering layers and the second gettering layers which are alternately arranged are adopted to replace the traditional GaAs buffer layer, so that the influence of substrate defects and impurities on an epitaxial structure can be weakened, the background impurity concentration and oxygen element residues of the reaction chamber environment can be reduced, conditions are provided for producing high-quality epitaxial materials, and meanwhile, the cost and the growth time are reduced.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, where, as shown in fig. 1, the semiconductor device includes:
A semiconductor substrate 21, the semiconductor substrate 21 having opposite first and second surfaces;
An epitaxial structure 22 disposed on the first surface, the epitaxial structure 22 having a plurality of first gettering layers 221 and second gettering layers 222 alternately disposed;
A first functional layer 23 disposed on a side surface of the epitaxial structure 22 facing away from the first surface;
An active layer 24 disposed on a surface of the first functional layer 23 facing away from the epitaxial structure 22; the active layer 24 may be a superlattice multiple quantum well structure;
The second functional layer 25 is disposed on the surface of the active layer 24 facing away from the first functional layer 23.
In an embodiment of the present invention, the semiconductor substrate 21 may be an N-type GaAs substrate with a crystal orientation <100> biased toward <111> a by 2 degrees to 15 degrees.
On the N-type GaAs substrate, 2-20 layers of alternately stacked first gettering layers 221 and second gettering layers 222 may be provided. In the embodiment shown in fig. 1, the first gettering layer 221 and the second gettering layer 222 may have 5 layers, which are the first gettering layer 221, the second gettering layer 222, and the first gettering layer 221, respectively. The number of layers can be adjusted according to the requirements, and is not limited to the mode of the application.
The order of generating the first gettering layer 221 and the second gettering layer 222 may be adjusted based on the requirement, and the first gettering layer 221 may be generated first and the second gettering layer 222 may be generated second; the second gettering layer 222 may be first generated and the first gettering layer 221 may be regenerated.
In the embodiment of the present invention, the first gettering layer 221 and the second gettering layer 222 are both N-type gettering layers. The first gettering layer 221 and the second gettering layer 222 each have a gettering effect.
Wherein, the first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be a GaAs layer;
Alternatively, the first gettering layer 221 may be an AlAs layer and the second gettering layer 222 may be an Al xGa1-x As layer; wherein x is more than or equal to 0 and less than or equal to 1; for example, the second gettering layer 222 may be an Al 0.5Ga1-0.5 As layer;
Alternatively, the first gettering layer 221 may be (Al yGa1-y)0.5In0.5 P layer, the second gettering layer 222 may be (Al zGa1-z)0.5In0.5 P layer; wherein 0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1. For example, the first gettering layer 221 may be (Al 0.3Ga1-0.3)0.5In0.5 P layer, the second gettering layer 222 may be (Al 0.6Ga1-0.6)0.5In0.5 P layer).
In the embodiment of the present invention, the thickness of the first gettering layer 221 may be 2-50nm; the thickness of the second gettering layer 222 may be 2-50nm. For example, it may be 30nm
The thickness of the first gettering layer 221 may be the same as or different from the thickness of the second gettering layer 222. For example, the thickness of the first gettering layer 221 and the thickness of the second gettering layer 222 are both 30nm; or the thickness of the first gettering layer 221 is 20nm and the thickness of the second gettering layer 222 is 30nm. May be set on a demand basis and is not limited to the manner in which the present application is described.
In the embodiment of the present invention, the first functional layer 23 may be an N-type functional layer, and the second functional layer 25 may be a P-type functional layer;
alternatively, the first functional layer 23 may be a P-type functional layer, and the second functional layer 25 may be an N-type functional layer.
As shown in fig. 2, fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, where the first functional layer 23 is an N-type functional layer, and the N-type functional layer includes:
A corrosion-stop layer 231 provided on a surface of the epitaxial structure 22 facing away from the semiconductor substrate 21;
an N-type ohmic contact layer 232 disposed on the surface of the etch stop layer 231 facing away from the epitaxial structure 22;
The roughened layer 233 is arranged on the surface of the N-type ohmic contact layer 232, which is away from the corrosion cut-off layer 231;
An N-type current expansion layer 234 disposed on a surface of the roughened layer 233 facing away from the N-type ohmic contact layer 232;
And an N-type limiting layer 235 disposed on the surface of the N-type current spreading layer 234 facing away from the roughened layer 233.
As shown in fig. 2, the second functional layer 25 is a P-type functional layer, and the P-type functional layer includes:
a P-type confinement layer 251 disposed on a surface of the active layer 24 facing away from the first functional layer 23;
a P-type current spreading layer 252 disposed on the surface of the P-type confinement layer 251 facing away from the active layer 24;
and a P-type ohmic contact layer 253 disposed on a surface of the P-type current spreading layer 252 facing away from the P-type confinement layer 251.
As can be seen from the above description, in the semiconductor device provided by the technical scheme of the present invention, the first gettering layers and the second gettering layers which are alternately arranged are adopted to replace the conventional GaAs buffer layer, so that not only can the influence of substrate defects and impurities on the epitaxial structure be weakened, but also the background impurity concentration and oxygen element residue of the reaction chamber environment can be reduced, conditions are provided for producing high-quality epitaxial materials, and meanwhile, the cost and the growth time are reduced.
Based on the above embodiment, another embodiment of the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 1 to fig. 6, and fig. 3 to fig. 6 are process flow diagrams of the method for manufacturing a semiconductor device according to the embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
Step S101: as shown in fig. 3, a semiconductor substrate 21 is provided, the semiconductor substrate 21 having opposite first and second surfaces;
The semiconductor substrate 21 may be an N-type GaAs substrate having a <100> bias <111> a of 2 degrees to 15 degrees in crystal orientation.
Step S102: as shown in fig. 4, an epitaxial structure 22 is disposed on the first surface, and the epitaxial structure 22 has a plurality of first gettering layers 221 and second gettering layers 222 alternately disposed;
wherein, the first gettering layer 221 and the second gettering layer 222 are both N-type gettering layers.
The first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be a GaAs layer;
Or, the first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be an Al xGa1-x As layer; wherein x is more than or equal to 0 and less than or equal to 1;
alternatively, the first gettering layer 221 may be (Al yGa1-y)0.5In0.5 P layer) and the second gettering layer 222 may be (Al zGa1-z)0.5In0.5 P layer; wherein 0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1).
Step S103: as shown in fig. 5, a first functional layer 23 is provided on a side surface of the epitaxial structure 22 facing away from the first surface;
As shown in fig. 2, the first functional layer 23 may be an N-type functional layer, and the N-type functional layer includes: a corrosion-stop layer 231 provided on a surface of the epitaxial structure 22 facing away from the semiconductor substrate 21; an N-type ohmic contact layer 232 disposed on the surface of the etch stop layer 231 facing away from the epitaxial structure 22; the roughened layer 233 is arranged on the surface of the N-type ohmic contact layer 232, which is away from the corrosion cut-off layer 231; an N-type current expansion layer 234 disposed on a surface of the roughened layer 233 facing away from the N-type ohmic contact layer 232; and an N-type limiting layer 235 disposed on the surface of the N-type current spreading layer 234 facing away from the roughened layer 233.
Step S104: as shown in fig. 6, an active layer 24 is provided on the surface of the first functional layer 23 facing away from the epitaxial structure 22; the active layer 24 may be a superlattice multiple quantum well structure.
Step S105: as shown in fig. 1, a second functional layer 25 is arranged on the surface of the active layer 24 facing away from the first functional layer 23.
As shown in fig. 2, the second functional layer 25 may be a P-type functional layer, and the P-type functional layer includes: a P-type confinement layer 251 disposed on a surface of the active layer 24 facing away from the first functional layer 23; a P-type current spreading layer 252 disposed on the surface of the P-type confinement layer 251 facing away from the active layer 24; and a P-type ohmic contact layer 253 disposed on a surface of the P-type current spreading layer 252 facing away from the P-type confinement layer 251.
In step S102, a pre-bake is performed before the epitaxial structure 22 is grown, and the pre-bake temperature may be set to 650-850 degrees and the time may be set to 5-30 minutes. For example, the pre-bake temperature may be set at 700 degrees and the time set at 15 minutes.
After the pre-bake is completed, an epitaxial structure 22 is grown on the first surface of the semiconductor substrate 21. Taking the epitaxial structure 22 with 5 gettering layers as an example, a first gettering layer 221, a second gettering layer 222 and a first gettering layer 221 are sequentially grown on the first surface of the semiconductor substrate 21.
Specifically, a method of growing epitaxial structure 22 having 5 gettering layers includes:
1. And a first gettering layer 221 is grown on the first surface in a high-temperature low-speed mode, wherein the first gettering layer 221 can be a first GaAs layer, the temperature can be 680-780 ℃, the long speed is 1-10A/s, and the time is 0.5-2min. The purpose is that: the defect of the substrate can be eliminated, the stress is released, and the subsequent crystal growth is facilitated.
2. And a second gettering layer 222 is grown on the surface of one side of the first GaAs layer facing away from the semiconductor substrate 21 by adopting a high-temperature low-speed mode, wherein the second gettering layer 222 can be a first AlAs layer, the temperature can be set to 680-780 ℃, the long speed is set to 1-10A/s, and the time is set to 0.5-2min. The purpose is that: the high temperature releases the water oxygen in the environment, part of the water oxygen is discharged along with the carrier gas, part of the water oxygen is absorbed by the AlAs, volatile impurities in the spare parts of the reaction chamber are dissociated, the background impurity concentration is reduced, the high temperature can promote the AlAs to absorb the oxygen, and the dissociated P-type impurities such as Mg, C and the like are inhibited from being incorporated into the AlAs.
3. And a second GaAs layer grows on the surface of one side of the first AlAs layer, which is away from the first GaAs layer, in a high-temperature low-speed mode, wherein the temperature can be 680-780 ℃, the long-speed is 1-10A/s, and the time is 0.5-2min. The purpose is that: the defect of the substrate can be eliminated, the stress is released, and the subsequent crystal growth is facilitated.
4. And a second AlAs layer grows on the surface of one side of the second GaAs layer, which is away from the first AlAs layer, in a low-temperature and low-speed mode, wherein the temperature can be set to 600-700 ℃, the long speed is set to 1-10A/s, and the time is set to 0.5-2min. The purpose is that: the lattice constants of AlAs/GaAs are 5.66A/5.65A respectively, and the low-temperature AlAs and high-temperature GaAs are better in matching degree by calculating the thermal expansion coefficient (5.2E-6/5.73E-6), so that the subsequent high-quality crystal growth is facilitated.
5. And a third GaAs layer grows on the surface of one side of the second AlAs layer, which is away from the second GaAs layer, in a high-temperature low-speed mode, wherein the temperature can be 680-780 ℃, the long-speed is 1-10A/s, and the time is 0.5-2min. The purpose is that: the defect of the substrate can be eliminated, the stress is released, and the subsequent crystal growth is facilitated.
The epitaxial structure 22 may be an LED epitaxial structure with a gettering layer, a VCESL (vertical cavity surface emitting laser) epitaxial structure with a gettering layer, an InP epitaxial structure with a gettering layer, or an HBT (heterojunction bipolar transistor) epitaxial structure with a gettering layer.
As can be seen from the above description, in the method for manufacturing a semiconductor device provided by the technical scheme of the present invention, the first gettering layers and the second gettering layers which are alternately arranged are adopted to replace the conventional GaAs buffer layer, so that not only can the influence of substrate defects and impurities on the external structure be weakened, but also the background impurity concentration and oxygen element residue of the reaction chamber environment can be reduced, conditions are provided for growing high-quality epitaxial materials, and meanwhile, the cost and the growth time are reduced.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. The manufacturing method disclosed in the embodiment corresponds to the semiconductor device disclosed in the embodiment, so that the description is simpler, and the relevant points are only referred to the description of the semiconductor device.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. A semiconductor device, comprising:
a semiconductor substrate having opposing first and second surfaces;
The epitaxial structure is arranged on the first surface and is provided with a plurality of layers of first gettering layers and second gettering layers which are alternately arranged; the epitaxial structure is provided with 2-20 layers of first gettering layers and second gettering layers which are alternately arranged; the first gettering layer and the second gettering layer are both N-type gettering layers;
The first functional layer is arranged on one side surface of the epitaxial structure, which is away from the first surface;
The active layer is arranged on the surface of the first functional layer, which is away from the epitaxial structure;
the second functional layer is arranged on the surface of the active layer, which is away from the first functional layer;
the first functional layer is a P-type functional layer, and the second functional layer is an N-type functional layer;
Or the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer;
The N-type functional layer comprises:
The corrosion stop layer is arranged on the surface of the epitaxial structure, which is away from the semiconductor substrate;
the N-type ohmic contact layer is arranged on the surface of the corrosion cut-off layer, which is away from the epitaxial structure;
the coarsening layer is arranged on the surface of the N-type ohmic contact layer, which is away from the corrosion cut-off layer;
the N-type current expansion layer is arranged on the surface of the coarsening layer, which is away from the N-type ohmic contact layer;
The N-type limiting layer is arranged on the surface of the N-type current expansion layer, which is away from the roughened layer;
The P-type functional layer comprises:
the P-type limiting layer is arranged on the surface of the active layer, which is away from the first functional layer;
the P-type current expansion layer is arranged on the surface of the P-type limiting layer, which is away from the active layer;
And the P-type ohmic contact layer is arranged on the surface of the P-type current expansion layer, which is away from the P-type limiting layer.
2. The semiconductor device according to claim 1, wherein the first gettering layer is an AlAs layer and the second gettering layer is a GaAs layer;
or the first gettering layer is an AlAs layer, and the second gettering layer is an Al xGa1-x As layer; wherein x is more than or equal to 0 and less than or equal to 1;
Or the first gettering layer is an (Al yGa1-y)0.5In0.5 P layer) layer, and the second gettering layer is an (Al zGa1-z)0.5In0.5 P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
3. The semiconductor device according to claim 2, wherein a thickness of the first gettering layer is 2 to 50nm; the thickness of the second gettering layer is 2-50nm.
4. The semiconductor device according to claim 1, wherein the semiconductor substrate is an N-type GaAs substrate having a crystal orientation <100> biased toward <111> a by 2 degrees to 15 degrees.
5. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
Arranging an epitaxial structure on the first surface, wherein the epitaxial structure is provided with a plurality of layers of alternately arranged first gettering layers and second gettering layers; the epitaxial structure is provided with 2-20 layers of first gettering layers and second gettering layers which are alternately arranged; the first gettering layer and the second gettering layer are both N-type gettering layers;
a first functional layer is arranged on the surface of one side of the epitaxial structure, which is away from the first surface;
an active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer;
A second functional layer is arranged on the surface, away from the first functional layer, of the active layer;
the first functional layer is a P-type functional layer, and the second functional layer is an N-type functional layer;
Or the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer;
The N-type functional layer comprises:
The corrosion stop layer is arranged on the surface of the epitaxial structure, which is away from the semiconductor substrate;
the N-type ohmic contact layer is arranged on the surface of the corrosion cut-off layer, which is away from the epitaxial structure;
the coarsening layer is arranged on the surface of the N-type ohmic contact layer, which is away from the corrosion cut-off layer;
the N-type current expansion layer is arranged on the surface of the coarsening layer, which is away from the N-type ohmic contact layer;
The N-type limiting layer is arranged on the surface of the N-type current expansion layer, which is away from the roughened layer;
The P-type functional layer comprises:
the P-type limiting layer is arranged on the surface of the active layer, which is away from the first functional layer;
The P-type current expansion layer is arranged on the surface of the P-type limiting layer, which is away from the active layer; and the P-type ohmic contact layer is arranged on the surface of the P-type current expansion layer, which is away from the P-type limiting layer.
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