CN114156383A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN114156383A
CN114156383A CN202111468676.XA CN202111468676A CN114156383A CN 114156383 A CN114156383 A CN 114156383A CN 202111468676 A CN202111468676 A CN 202111468676A CN 114156383 A CN114156383 A CN 114156383A
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layer
type
functional layer
gettering
epitaxial structure
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CN114156383B (en
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伏兵
嵇庆培
马英杰
蔡和勋
许宗琦
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Xiamen Changelight Co Ltd
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Xiamen Changelight Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The application discloses a semiconductor device and a manufacturing method thereof, the semiconductor device comprises: a semiconductor substrate having opposing first and second surfaces; the epitaxial structure is arranged on the first surface and provided with a plurality of first impurity absorption layers and a plurality of second impurity absorption layers which are alternately arranged; the first functional layer is arranged on the surface of one side, away from the first surface, of the epitaxial structure; the active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer; and the second functional layer is arranged on the surface of the active layer, which is deviated from the first functional layer. Therefore, the scheme adopts the first gettering layer and the second gettering layer which are alternately arranged in multiple layers to replace the traditional GaAs buffer layer, so that the influence of substrate defects and impurities on the epitaxial structure can be weakened, the background impurity concentration and oxygen element residue of the reaction chamber environment can be reduced, conditions are provided for growing high-quality epitaxial materials, and the cost and the growth time are reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, semiconductor devices are developing towards high power and high brightness, taking an LED as an example, the LED has the advantages of small volume, light weight, less heat productivity, low power consumption, long service life, good monochromaticity, high response speed, environmental protection, good shock resistance and the like, so that the LED is widely applied to various fields. With the continuous progress of science and technology and the change of life concept of people, the quaternary system AlGaInP (aluminum gallium indium phosphide) yellow-green light emitting diode is widely applied to various fields of signal indication, traffic indication, automobile illumination, special illumination and the like. As the wavelength of the quaternary system AlGaInP material is shortened, the Al component of the active layer is continuously increased, and the combination of Al atoms and oxygen or carbon atoms causes the material to generate serious lattice defects, so that the luminous efficiency is reduced; on the other hand, the energy band of the yellow-green light is gradually changed from a direct energy gap to an indirect energy gap due to the improvement of the proportion of the Al component, and the internal quantum efficiency is greatly reduced, so that the luminous efficiency of the yellow-green light waveband LED product is lower; meanwhile, when the organic metal vapor deposition (MOCVD) technology is used for production, because the edge epitaxial deposition efficiency of the slide glass disc is poor, the edge performance of an epitaxial wafer after growth is poor, the production yield is low, and the problems are more obviously reflected in a yellow-green light wave band which is more limited in a process window.
In the prior art, for a 570nm led with high brightness, in order to reach the wavelength during epitaxial growth, an AlGaInP quaternary quantum well with high Al composition is needed, and oxygen element is easily absorbed by Al to form deep level defects, which affect internal quantum efficiency.
Disclosure of Invention
In view of the above, the present disclosure provides a semiconductor device and a method for manufacturing the same, which can not only weaken the substrate defects and the influence of impurities on the epitaxial structure, but also reduce the background impurity concentration and the oxygen residue in the reaction chamber environment, thereby providing conditions for growing high-quality epitaxial materials.
In order to achieve the above purpose, the invention provides the following technical scheme:
a semiconductor device, the semiconductor device comprising:
a semiconductor substrate having opposing first and second surfaces;
the epitaxial structure is arranged on the first surface and provided with a plurality of first impurity absorption layers and a plurality of second impurity absorption layers which are alternately arranged;
the first functional layer is arranged on the surface of one side, away from the first surface, of the epitaxial structure;
the active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer;
and the second functional layer is arranged on the surface of the active layer, which is deviated from the first functional layer.
Preferably, in the above semiconductor device, the epitaxial structure has 2 to 20 layers of the first gettering layer and the second gettering layer alternately disposed.
Preferably, in the semiconductor device described above, the first gettering layer and the second gettering layer are both N-type gettering layers.
Preferably, in the above semiconductor device, the first gettering layer is an AlAs layer, and the second gettering layer is a GaAs layer;
or the first impurity absorption layer is an AlAs layer, and the second impurity absorption layer is AlxGa1-xAn As layer; wherein x is more than or equal to 0 and less than or equal to 1;
or the first impurity-absorbing layer is (Al)yGa1-y)0.5In0.5A P layer, the second gettering layer is (Al)zGa1-z)0.5In0.5A P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
Preferably, in the above semiconductor device, the first gettering layer has a thickness of 2 to 50 nm; the thickness of the second gettering layer is 2-50 nm.
Preferably, in the above semiconductor device, the semiconductor substrate is an N-type GaAs substrate having a crystal orientation of <100> biased toward <111> a of 2 degrees to 15 degrees.
Preferably, in the above semiconductor device, the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer;
or, the first functional layer is a P-type functional layer, and the second functional layer is an N-type functional layer.
Preferably, in the above semiconductor device, the first functional layer is an N-type functional layer, and the N-type functional layer includes:
the corrosion cut-off layer is arranged on the surface, away from the surface of the semiconductor substrate, of the epitaxial structure;
the N-type ohmic contact layer is arranged on the surface, away from the epitaxial structure, of the corrosion stop layer;
the coarsening layer is arranged on the surface, away from the corrosion stop layer, of the N-type ohmic contact layer;
the N-type current expansion layer is arranged on the surface, away from the N-type ohmic contact layer, of the coarsened layer;
and the N-type limiting layer is arranged on the surface of the N-type current expansion layer, which is deviated from the coarsening layer.
Preferably, in the above semiconductor device, the second functional layer is a P-type functional layer, and the P-type functional layer includes:
the P-type limiting layer is arranged on the surface of the active layer, which is deviated from the first functional layer;
the P-type current expansion layer is arranged on the surface of the P-type limiting layer, which is deviated from the active layer;
and the P-type ohmic contact layer is arranged on the surface of the P-type current expansion layer, which is deviated from the P-type limiting layer.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
arranging an epitaxial structure on the first surface, wherein the epitaxial structure is provided with a plurality of first impurity absorption layers and second impurity absorption layers which are alternately arranged;
arranging a first functional layer on the surface of one side, away from the first surface, of the epitaxial structure;
an active layer is arranged on the surface of the first functional layer, which is far away from the epitaxial structure;
and arranging a second functional layer on the surface of the active layer, which is far away from the first functional layer.
As can be seen from the above description, in the semiconductor device and the manufacturing method thereof according to the technical solution of the present invention, the semiconductor device includes: a semiconductor substrate having opposing first and second surfaces; the epitaxial structure is arranged on the first surface and provided with a plurality of first impurity absorption layers and a plurality of second impurity absorption layers which are alternately arranged; the first functional layer is arranged on the surface of one side, away from the first surface, of the epitaxial structure; the active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer; and the second functional layer is arranged on the surface of the active layer, which is deviated from the first functional layer.
According to the scheme, the first gettering layer and the second gettering layer which are alternately arranged in multiple layers are adopted to replace a traditional GaAs buffer layer, so that the influence of substrate defects and impurities on an epitaxial structure can be weakened, the background impurity concentration and oxygen element residue of a reaction chamber environment can be reduced, conditions are provided for growing a high-quality epitaxial material, and the cost and the growth time are reduced simultaneously.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;
fig. 3-6 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As described in the background, with the continuous development of semiconductor technology, semiconductor devices are developed towards high power and high brightness, taking LEDs as an example:
for a high brightness 570nm LED: during epitaxial growth, to reach the wavelength, an AlGaInP quaternary quantum well with a high Al composition is needed, oxygen is easily absorbed by Al to form deep level defects, which affect the internal quantum efficiency, and to reduce the effect, a pre-baking method is usually adopted to reduce the oxygen content in the reaction chamber. Residual oxygen in the reaction chamber can be basically removed by high-temperature and long-time baking, but the cost and the productivity are greatly influenced.
And for high power infrared LEDs: the infrared high-power chip has high working temperature and high requirements on the crystal quality and stability of each epitaxial layer, and the doping elements and the concentration of each epitaxial layer need to be accurately controlled in epitaxial growth, so that the reduction of the background impurity concentration and the reduction of lattice defects are particularly important. A pre-bake and a method of controlling the defect density of the substrate are generally used. The method for controlling the defect density of the substrate is to purchase the substrate with low defect density from a substrate supplier, and in the crystal growth process of the substrate, the substrate with low defect density occupies less area, the technical difficulty is high, and the price is often more than one time of that of the conventional substrate.
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device including:
a semiconductor substrate having opposing first and second surfaces;
the epitaxial structure is arranged on the first surface and provided with a plurality of first impurity absorption layers and a plurality of second impurity absorption layers which are alternately arranged;
the first functional layer is arranged on the surface of one side, away from the first surface, of the epitaxial structure;
the active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer;
and the second functional layer is arranged on the surface of the active layer, which is deviated from the first functional layer.
According to the scheme, the first gettering layer and the second gettering layer which are alternately arranged in multiple layers are adopted to replace a traditional GaAs buffer layer, so that the influence of substrate defects and impurities on an epitaxial structure can be weakened, the background impurity concentration and oxygen element residue of a reaction chamber environment can be reduced, conditions are provided for growing a high-quality epitaxial material, and the cost and the growth time are reduced simultaneously.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, and as shown in fig. 1, the semiconductor device includes:
a semiconductor substrate 21, the semiconductor substrate 21 having opposing first and second surfaces;
an epitaxial structure 22 disposed on the first surface, wherein the epitaxial structure 22 has a plurality of first gettering layers 221 and second gettering layers 222 alternately disposed;
a first functional layer 23 disposed on a surface of the epitaxial structure 22 facing away from the first surface;
an active layer 24 disposed on a surface of the first functional layer 23 facing away from the epitaxial structure 22; the active layer 24 may be a superlattice multiple quantum well structure;
and the second functional layer 25 is arranged on the surface of the active layer 24, which is far away from the first functional layer 23.
In the embodiment of the present invention, the semiconductor substrate 21 may be an N-type GaAs substrate having a crystal orientation of <100> biased toward <111> a of 2 to 15 degrees.
On the N-type GaAs substrate, 2 to 20 layers of the first gettering layer 221 and the second gettering layer 222 alternately stacked may be provided. In the embodiment shown in fig. 1, the first gettering layer 221 and the second gettering layer 222 may be 5 layers, and are the first gettering layer 221, the second gettering layer 222, and the first gettering layer 221, respectively. The number of layers can be adjusted according to requirements, and is not limited to the mode described in the application.
The generation order of the first gettering layer 221 and the second gettering layer 222 may be adjusted based on the demand, and the first gettering layer 221 may be generated first, and then the second gettering layer 222 may be generated; the second gettering layer 222 may be formed first, and then the first gettering layer 221 may be formed.
In the embodiment of the present invention, the first gettering layer 221 and the second gettering layer 222 are both N-type gettering layers. The first gettering layer 221 and the second gettering layer 222 each have a gettering effect.
The first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be a GaAs layer;
alternatively, the first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be AlxGa1-xAn As layer; wherein x is more than or equal to 0 and less than or equal to 1; for example, the second gettering layer 222 may be Al0.5Ga1-0.5An As layer;
alternatively, the first impurity-absorbing layer 221 may be (Al)yGa1-y)0.5In0.5The P layer and the second gettering layer 222 may be (Al)zGa1-z)0.5In0.5A P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1. For example, the first gettering layer 221 may be (Al)0.3Ga1-0.3)0.5In0.5The P layer and the second gettering layer 222 may be (Al)0.6Ga1-0.6)0.5In0.5And a P layer.
In the embodiment of the present invention, the thickness of the first impurity absorption layer 221 may be 2 to 50 nm; the thickness of the second gettering layer 222 may be 2-50 nm. E.g. may be 30nm
The thickness of the first gettering layer 221 and the thickness of the second gettering layer 222 may be the same or different. For example, the thickness of the first gettering layer 221 and the thickness of the second gettering layer 222 are both 30 nm; or the thickness of the first gettering layer 221 is 20nm and the thickness of the second gettering layer 222 is 30 nm. The setting can be based on the requirement, and is not limited to the mode described in the application.
In this embodiment of the present invention, the first functional layer 23 may be an N-type functional layer, and the second functional layer 25 may be a P-type functional layer;
alternatively, the first functional layer 23 may be a P-type functional layer, and the second functional layer 25 may be an N-type functional layer.
As shown in fig. 2, fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention, where the first functional layer 23 is an N-type functional layer, and the N-type functional layer includes:
an etch stop layer 231 disposed on a surface of the epitaxial structure 22 facing away from the semiconductor substrate 21;
an N-type ohmic contact layer 232 disposed on a surface of the etch stop layer 231 facing away from the epitaxial structure 22;
a roughened layer 233 disposed on a surface of the N-type ohmic contact layer 232 facing away from the etch stop layer 231;
an N-type current spreading layer 234 disposed on the surface of the roughened layer 233 facing away from the N-type ohmic contact layer 232;
and an N-type confinement layer 235 disposed on the surface of the N-type current spreading layer 234 facing away from the roughened layer 233.
As shown in fig. 2, the second functional layer 25 is a P-type functional layer, and the P-type functional layer includes:
a P-type confinement layer 251 disposed on a surface of the active layer 24 facing away from the first functional layer 23;
a P-type current spreading layer 252 disposed on the surface of the P-type confinement layer 251 facing away from the active layer 24;
and a P-type ohmic contact layer 253 arranged on the surface of the P-type current spreading layer 252, which is far away from the P-type limiting layer 251.
As can be seen from the above description, in the semiconductor device provided in the technical solution of the present invention, the first gettering layer and the second gettering layer alternately arranged in multiple layers are used to replace the conventional GaAs buffer layer, so that not only can the influence of the substrate defect and the impurity on the epitaxial structure be weakened, but also the background impurity concentration and the oxygen element residue in the reaction chamber environment can be reduced, conditions are provided for growing high-quality epitaxial materials, and the cost and the growth time are reduced.
Based on the above embodiment, another embodiment of the present invention further provides a manufacturing method of a semiconductor device, as shown in fig. 1 to 6, and fig. 3 to 6 are process flow charts of the manufacturing method of the semiconductor device according to the embodiment of the present invention, where the manufacturing method includes:
step S101: as shown in fig. 3, providing a semiconductor substrate 21, wherein the semiconductor substrate 21 has a first surface and a second surface opposite to each other;
the semiconductor substrate 21 may be an N-type GaAs substrate having a crystal orientation of <100> biased toward <111> a of 2 to 15 degrees.
Step S102: as shown in fig. 4, an epitaxial structure 22 is disposed on the first surface, and the epitaxial structure 22 has a plurality of first gettering layers 221 and second gettering layers 222 alternately disposed;
wherein the first gettering layer 221 and the second gettering layer 222 are both N-type gettering layers.
The first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be a GaAs layer;
alternatively, the first gettering layer 221 may be an AlAs layer, and the second gettering layer 222 may be AlxGa1-xAn As layer; wherein x is more than or equal to 0 and less than or equal to 1;
alternatively, the first impurity-absorbing layer 221 may be (Al)yGa1-y)0.5In0.5P layer, orThe second gettering layer 222 may be (Al)zGa1-z)0.5In0.5A P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
Step S103: as shown in fig. 5, a first functional layer 23 is disposed on a side surface of the epitaxial structure 22 facing away from the first surface;
as shown in fig. 2, the first functional layer 23 may be an N-type functional layer, which includes: an etch stop layer 231 disposed on a surface of the epitaxial structure 22 facing away from the semiconductor substrate 21; an N-type ohmic contact layer 232 disposed on a surface of the etch stop layer 231 facing away from the epitaxial structure 22; a roughened layer 233 disposed on a surface of the N-type ohmic contact layer 232 facing away from the etch stop layer 231; an N-type current spreading layer 234 disposed on the surface of the roughened layer 233 facing away from the N-type ohmic contact layer 232; and an N-type confinement layer 235 disposed on the surface of the N-type current spreading layer 234 facing away from the roughened layer 233.
Step S104: as shown in fig. 6, an active layer 24 is disposed on a surface of the first functional layer 23 facing away from the epitaxial structure 22; the active layer 24 may be a superlattice multiple quantum well structure.
Step S105: as shown in fig. 1, a second functional layer 25 is provided on the surface of the active layer 24 facing away from the first functional layer 23.
As shown in fig. 2, the second functional layer 25 may be a P-type functional layer, which includes: a P-type confinement layer 251 disposed on a surface of the active layer 24 facing away from the first functional layer 23; a P-type current spreading layer 252 disposed on the surface of the P-type confinement layer 251 facing away from the active layer 24; and a P-type ohmic contact layer 253 arranged on the surface of the P-type current spreading layer 252, which is far away from the P-type limiting layer 251.
In step S102, a pre-baking is performed before the epitaxial structure 22 is grown, wherein the pre-baking temperature may be set to 650-. For example, the pre-bake temperature may be set at 700 degrees for 15 min.
After the pre-baking is finished, an epitaxial structure 22 is grown on the first surface of the semiconductor substrate 21. Taking the epitaxial structure 22 having 5 gettering layers as an example, a first gettering layer 221, a second gettering layer 222, and a first gettering layer 221 are sequentially grown on the first surface of the semiconductor substrate 21.
Specifically, the method for growing the epitaxial structure 22 having 5 gettering layers includes:
1. growing a first impurity absorption layer 221 on the first surface in a high-temperature low-speed manner, wherein the first impurity absorption layer 221 can be a first GaAs layer, the temperature can be set to 680-780 ℃, the long speed is set to 1-10A/s, and the time is set to 0.5-2 min. The purpose is as follows: can eliminate the defects of the substrate, release stress and be beneficial to subsequent crystal growth.
2. And growing a second gettering layer 222 on the surface of the first GaAs layer, which is opposite to the side of the semiconductor substrate 21, in a high-temperature and low-speed manner, wherein the second gettering layer 222 may be a first AlAs layer, the temperature may be set to 680-780 ℃, the long speed is set to 1-10A/s, and the time is set to 0.5-2 min. The purpose is as follows: the water oxygen in the environment is released at high temperature, part of the water oxygen is discharged along with carrier gas, part of the water oxygen is absorbed by the AlAs, simultaneously volatile impurities in spare parts of the reaction chamber are dissociated, the background impurity concentration is reduced, the high temperature can promote the AlAs to absorb the oxygen, and P-type impurities such as Mg, C and the like which are dissociated are inhibited from being incorporated into the AlAs.
3. And growing a second GaAs layer on the surface of one side, away from the first GaAs layer, of the first AlAs layer by adopting a high-temperature low-speed mode, wherein the temperature can be set to be 680-780 ℃, the long speed is set to be 1-10A/s, and the time is set to be 0.5-2 min. The purpose is as follows: can eliminate the defects of the substrate, release stress and be beneficial to subsequent crystal growth.
4. And growing a second AlAs layer on the surface of one side of the second GaAs layer, which is far away from the first AlAs layer, by adopting a low-temperature and low-speed mode, wherein the temperature can be set to 600-700 ℃, the long speed is set to be 1-10A/s, and the time is set to be 0.5-2 min. The purpose is as follows: the lattice constants of AlAs/GaAs are respectively 5.66A/5.65A, and the matching degree of low-temperature AlAs and high-temperature GaAs is better by utilizing the thermal expansion coefficient (5.2E-6/5.73E-6) for calculation, thereby being beneficial to subsequent high-quality crystal growth.
5. And growing a third GaAs layer on the surface of one side, away from the second GaAs layer, of the second AlAs layer by adopting a high-temperature low-speed mode, wherein the temperature can be set to be 680-780 ℃, the long speed is set to be 1-10A/s, and the time is set to be 0.5-2 min. The purpose is as follows: can eliminate the defects of the substrate, release stress and be beneficial to subsequent crystal growth.
It should be noted that the epitaxial structure 22 may be an LED epitaxial structure with a gettering layer, or a VCESL (vertical cavity surface emitting laser) epitaxial structure with a gettering layer, or an InP epitaxial structure with a gettering layer, or an HBT (heterojunction bipolar transistor) epitaxial structure with a gettering layer.
As can be seen from the above description, in the manufacturing method of the semiconductor device provided in the technical solution of the present invention, the first gettering layer and the second gettering layer alternately arranged in multiple layers are used to replace the conventional GaAs buffer layer, so that not only the influence of the substrate defects and impurities on the epitaxial structure can be weakened, but also the background impurity concentration and oxygen element residue in the reaction chamber environment can be reduced, conditions are provided for growing high-quality epitaxial materials, and the cost and the growth time are reduced.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The manufacturing method disclosed by the embodiment corresponds to the semiconductor device disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the partial description of the semiconductor device.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate having opposing first and second surfaces;
the epitaxial structure is arranged on the first surface and provided with a plurality of first impurity absorption layers and a plurality of second impurity absorption layers which are alternately arranged;
the first functional layer is arranged on the surface of one side, away from the first surface, of the epitaxial structure;
the active layer is arranged on the surface, away from the epitaxial structure, of the first functional layer;
and the second functional layer is arranged on the surface of the active layer, which is deviated from the first functional layer.
2. The semiconductor device of claim 1, wherein the epitaxial structure has 2-20 alternating first and second gettering layers.
3. The semiconductor device according to claim 2, wherein the first gettering layer and the second gettering layer are both N-type gettering layers.
4. The semiconductor device according to claim 3, wherein the first gettering layer is an AlAs layer, and the second gettering layer is a GaAs layer;
or, the first getteringThe layer is an AlAs layer, and the second gettering layer is AlxGa1-xAn As layer; wherein x is more than or equal to 0 and less than or equal to 1;
or the first impurity-absorbing layer is (Al)yGa1-y)0.5In0.5A P layer, the second gettering layer is (Al)zGa1-z)0.5In0.5A P layer; wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
5. The semiconductor device according to claim 4, wherein a thickness of the first gettering layer is 2 to 50 nm; the thickness of the second gettering layer is 2-50 nm.
6. The semiconductor device according to claim 1, wherein the semiconductor substrate is an N-type GaAs substrate having a crystal orientation of <100> biased toward <111> a from 2 degrees to 15 degrees.
7. The semiconductor device according to claim 1, wherein the first functional layer is an N-type functional layer, and the second functional layer is a P-type functional layer;
or, the first functional layer is a P-type functional layer, and the second functional layer is an N-type functional layer.
8. The semiconductor device according to claim 7, wherein the first functional layer is an N-type functional layer, the N-type functional layer comprising:
the corrosion cut-off layer is arranged on the surface, away from the surface of the semiconductor substrate, of the epitaxial structure;
the N-type ohmic contact layer is arranged on the surface, away from the epitaxial structure, of the corrosion stop layer;
the coarsening layer is arranged on the surface, away from the corrosion stop layer, of the N-type ohmic contact layer;
the N-type current expansion layer is arranged on the surface, away from the N-type ohmic contact layer, of the coarsened layer;
and the N-type limiting layer is arranged on the surface of the N-type current expansion layer, which is deviated from the coarsening layer.
9. The semiconductor device according to claim 7, wherein the second functional layer is a P-type functional layer, the P-type functional layer comprising:
the P-type limiting layer is arranged on the surface of the active layer, which is deviated from the first functional layer;
the P-type current expansion layer is arranged on the surface of the P-type limiting layer, which is deviated from the active layer;
and the P-type ohmic contact layer is arranged on the surface of the P-type current expansion layer, which is deviated from the P-type limiting layer.
10. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
arranging an epitaxial structure on the first surface, wherein the epitaxial structure is provided with a plurality of first impurity absorption layers and second impurity absorption layers which are alternately arranged;
arranging a first functional layer on the surface of one side, away from the first surface, of the epitaxial structure;
an active layer is arranged on the surface of the first functional layer, which is far away from the epitaxial structure;
and arranging a second functional layer on the surface of the active layer, which is far away from the first functional layer.
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