CN114156256A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN114156256A
CN114156256A CN202111033649.XA CN202111033649A CN114156256A CN 114156256 A CN114156256 A CN 114156256A CN 202111033649 A CN202111033649 A CN 202111033649A CN 114156256 A CN114156256 A CN 114156256A
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China
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region
interposer substrate
substrate
semiconductor package
passivation layer
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CN202111033649.XA
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English (en)
Inventor
张艾妮
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN114156256A publication Critical patent/CN114156256A/zh
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Abstract

一种半导体封装，包括：基底衬底；插入衬底，包括具有面向基底衬底的第一表面和与第一表面相对的第二表面的半导体衬底、以及在第一表面的至少一部分上的钝化层；多个连接凸块，位于基底衬底与插入衬底之间；底部填充树脂，位于基底衬底与插入衬底之间的空间中；以及第一半导体芯片和第二半导体芯片，在插入衬底上。插入衬底具有其中包括多个连接凸块的第一区域以及与第一区域的外围相邻的第二区域和第三区域，并且钝化层在第一区域和第二区域中并且包括在第二区域中的第一压纹图案。

Description

半导体封装
相关申请的交叉引用
本申请要求于2020年9月7日在韩国知识产权局递交的韩国专利申请No.10-2020-0113791的优先权，其公开内容通过引用整体并入本文中。
技术领域
本公开涉及一种半导体封装。
背景技术
已开发了用于在单个封装中嵌入多个半导体芯片的系统级封装(SIP)技术。具有硅通孔(TSV)的插入衬底已用于在封装中形成将半导体芯片彼此连接的精细互连。
发明内容
示例实施例提供了一种具有改善的可靠性的半导体封装。
根据示例实施例，一种半导体封装包括：基底衬底，包括第一互连结构；插入衬底，包括：具有面向基底衬底的第一表面和与第一表面相对的第二表面的半导体衬底、在第二表面上并且包括第二互连结构的互连区域、延伸通过半导体衬底并且将第二互连结构电连接到第一互连结构的通孔、以及在第一表面的至少一部分上的钝化层；多个连接凸块，在基底衬底与插入衬底之间，并且将通孔电连接到第一互连结构；底部填充树脂，位于基底衬底与插入衬底之间的空间中；以及第一半导体芯片和第二半导体芯片，在插入衬底的互连区域上，并且通过第二互连结构彼此电连接。插入衬底具有其中包括多个连接凸块的第一区域以及与第一区域的外围相邻的第二区域和第三区域，并且钝化层在第一区域和第二区域中并且包括在第二区域中的第一压纹图案。
根据示例实施例，一种半导体封装包括：插入衬底，具有包括多个通孔的第一区域、与第一区域的外围相邻的第二区域、以及与第二区域的外围相邻的第三区域；钝化层，位于插入衬底的第一表面上并处于第一区域和第二区域中，其中钝化层的表面包括第二区域中的第一压纹图案；以及多个半导体芯片，在插入衬底的第二表面上。第二区域与插入衬底的边缘间隔开，并且第三区域在第二区域与插入衬底的边缘之间。
根据示例实施例，一种半导体封装包括：插入衬底，包括具有第一表面和与第一表面相对的第二表面的半导体衬底、在第二表面上并且包括互连结构的互连区域、在第一表面上的多个凸块焊盘、在第一表面上与多个凸块焊盘的外围相邻的多个虚设图案、延伸通过半导体衬底并且将互连结构电连接到多个凸块焊盘的多个通孔、以及在多个凸块焊盘和多个虚设图案上的钝化层；以及第一半导体芯片和第二半导体芯片，在插入衬底上，并且通过互连结构彼此电连接。钝化层与插入衬底的边缘间隔开预定距离，并且具有沿多个虚设图案的表面弯曲的压纹图案。
附图说明
通过结合附图的以下具体实施方式，将更清楚地理解本公开的上述和其他方面、特征和优点。
图1A是示出了根据示例实施例的用于制造半导体封装的插入衬底的晶片的一部分的平面图。
图1B是根据示例实施例的半导体封装的截面图。
图1C是图1B的区域“A”的局部放大图。
图1D是示出了图1B的插入衬底的下表面的平面图。
图1E是示出了在图1B的半导体封装中出现的裂纹的蔓延(propagation)路径的平面图。
图1F是示出了在图1B的半导体封装中出现的裂纹的蔓延路径的截面图。
图2是示出了图1B的半导体封装中的一些组件的修改示例的截面图。
图3A和图3B是根据示例实施例的半导体封装的截面图。
图4A和图4B是示出了图3A的半导体封装中的一些组件的修改示例的截面图。
图5A至图5C是示出了根据各种示例实施例的半导体封装的插入衬底的平面图。
图6是根据示例实施例的半导体封装的截面图。
图7是根据示例实施例的半导体封装的截面图。
图8是根据示例实施例的半导体封装的截面图。
图9A至图9G是示出了制造图1B的半导体封装中的一些组件的方法的示意性截面图。
具体实施方式
在下文中，将参考附图来描述示例实施例。
图1A至图1F是示出了根据示例实施例的半导体封装1000A的图。图1A是示出了根据示例实施例的用于制造半导体封装的插入衬底100的晶片WR的一部分的平面图，图1B是根据示例实施例的半导体封装1000A的截面图，并且图1C是图1B的区域“A”的局部放大图。图1D是示出了图1B的插入衬底100的下表面的平面图，并且图1E和图1F是分别示出了在图1B的半导体封装1000A中出现的裂纹的蔓延路径的平面图和截面图。图1B的插入衬底示出了沿图1D的线I-I'截取的竖直截面图。图1B的半导体封装1000A示出了沿图1E的线II-II'截取的竖直截面图。
参考图1A，用于制造插入衬底100的晶片WR可以包括多个主要区域(或者，芯片区域)MR和划线道(scribe lane)区域或区SL。多个主要区域MR中的每个主要区域可以包括其中形成有多个硅通孔的区域。多个主要区域MR可以通过划线道区SL彼此间隔开。
划线道区域SL可以是在晶片WR上制造主要区域MR的工艺完成之后在锯切工艺期间沿其切割晶片WR以将各个插入衬底100彼此分开的区域。划线道区域SL可以包括接触区域SLa和非接触区域SLb。接触区域SLa在锯切工艺中与锯片接触，而非接触区SLb在锯切工艺中不与锯片接触。考虑到工艺误差，非接触区域SLb可以是边沿区域。在锯切工艺中，接触区域SLa的一部分可能会保留而不会被去除。通过锯切工艺彼此分开的插入衬底100中的每个插入衬底可以包括接触区域SLa中的在非接触区域SLb周围部分保留的区域。因此，插入衬底100可以包括与主要区域MR相对应的第一区域R1、与非接触区域SLb相对应的第二区域R2、以及第三区域R3，即，接触区域SLa中的在锯切工艺之后保留的区域。在本文中使用术语“第一”、“第二”等仅为了将一个元件或区域与另一个元件或区域区分开。主要区域MR和非接触区域SLb可以覆盖有钝化层140。如本文中所使用的那样，“覆盖”或“围绕”或“填充”另一元件或区域的元件或区域可以完全或部分地覆盖或围绕或填充该另一元件或区域。
例如，划线道区域SL的宽度可以在约300微米(μm)至350μm的范围内，并且锯条的宽度可以在约40μm至60μm的范围内。接触区域SLa的宽度可以在约80μm至100μm的范围内，并且非接触区域SLb的宽度可以在通过将划线道区域SL的宽度减去接触区域SLa的宽度而得到的范围内。在接触区域SLa的锯切工艺之后保留的区域R3的宽度可以为约10μm或更多。
参考图1B，半导体封装1000A可以包括基底衬底10、插入衬底100、多个半导体芯片20、多个连接凸块31、32和33、以及底部填充树脂40。
基底衬底10可以包括衬底主体11、分别设置在衬底主体11的下表面和上表面上的焊盘12和13、以及将焊盘12和13彼此电连接的第一互连结构14。基底衬底10可以被配置为其上安装有插入衬底100和半导体芯片20的支撑衬底，并且可以被配置为半导体封装的衬底，包括印刷电路板(PCB)、陶瓷衬底、玻璃衬底和带状布线板。
衬底主体11可以根据基底衬底10的类型而包括各种材料。例如，当基底衬底10是印刷电路板时，衬底主体11可以被配置为覆铜层压板或包括堆叠在其横截面或两个表面上的互连层的覆铜层压板。涂覆有阻焊剂的下保护层和上保护层可以分别形成在衬底主体11的下表面和上表面上。
焊盘12和13以及第一互连结构14可以形成将基底衬底10的下表面与上表面连接的电路径。焊盘12和13以及第一互连结构14可以包括合金，该合金包括以下项之中的至少一种或者两种或更多种：铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)和碳(C)。第一互连结构14可以包括：形成在衬底10中的单个互连层或多个互连层、以及将互连层彼此连接的过孔。
多个半导体芯片20可以安装在插入衬底100上，并且可以通过插入衬底100的前侧上的互连区域130或第二互连结构132彼此电连接。多个半导体芯片20可以包括第一半导体芯片21和第二半导体芯片22，第一半导体芯片21和第二半导体芯片22包括不同类型的集成电路。第一半导体芯片21可以包括逻辑芯片，例如中央处理单元(CPU)、图形处理单元(GPU)、现场可编程门阵列(FPGA)、数字信号处理器(DSP)、密码处理器、微处理器、微控制器、模数转换器或专用集成电路(ASIC)。第二半导体芯片22可以包括：易失性存储器器件(例如，动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM))、非易失性存储器器件(例如，相变随机存取存储器(PRAM)、磁随机存取存储器(MRAM)、电阻随机存取存储器(RRAM)或闪存)、或者高性能存储器器件(例如，高带宽存储器(HBM)或混合存储器立方体(HMC))。
多个连接凸块31、32和33可以具有倒装芯片连接结构，该倒装芯片连接结构例如具有焊球、导电凸块、或者诸如引脚栅格阵列、球栅格阵列或接点栅格阵列之类的栅格阵列。多个连接凸块31、32和33可以包括合金，该合金包括以下项之中的至少一种或者两种或更多种：铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)和碳(C)。例如，多个连接凸块31、32和33可以包括合金，该合金包括锡(Sn)(例如，Sn-Ag-Cu)。
基底衬底10的下表面上的第一连接凸块31可以将第一互连结构14与外部设备(例如，主板)进行物理连接和电连接。设置在基底衬底10与插入衬底100之间的第二连接凸块32可以将插入衬底100的通孔120和基底衬底10的第一互连结构14彼此物理连接和电连接。半导体芯片20的下表面上的第三连接凸块33可以将半导体芯片20与插入衬底100的第二互连结构130彼此物理连接和电连接。第一连接凸块至第三连接凸块31、32和33可以具有不同的尺寸。第一连接凸块31可以具有比第二连接凸块32和第三连接凸块33中的每一个的尺寸大的尺寸，并且第二连接凸块32可以具有比第三连接凸块33的尺寸大的尺寸。
底部填充树脂40可以部分或完全地填充插入衬底100与基底衬底10之间的空间，并且可以围绕第二连接凸块32。底部填充树脂40可以延伸到插入衬底100的边缘，以覆盖插入衬底100的侧表面S3的一部分。底部填充树脂40可以包括绝缘聚合物，例如，环氧树脂。在半导体封装1000A的热循环(TC)测试中，在围绕插入衬底100的底部填充树脂40的边缘部分和拐角部分中可能会出现裂纹(参见图1E和图1F)。裂纹可以沿插入衬底100的下表面蔓延，并且可以引起插入衬底100与底部填充树脂40之间的界面分层。在示例实施例中，压纹图案可以引入到插入衬底100的后侧上的钝化层140的边缘中，以减少或防止由裂纹引起的插入衬底100与底部填充树脂40之间的界面分层。
插入衬底100可以包括半导体衬底110、通孔120、互连区域130和钝化层140。与第二连接凸块32和第三连接凸块33接触的多个凸块焊盘101和102可以分别设置在插入衬底100的下表面和上表面上。凸块焊盘101和102可以被设置为嵌入在插入衬底100的下表面和上表面中。在这种情况下，凸块焊盘101和102的侧表面可以被由氧化硅、氮化硅或其组合形成的绝缘层围绕。凸块焊盘101和102可以包括合金，该合金包括以下项之中的至少一种或者两种或更多种：铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)和碳(C)。
半导体衬底110可以设置在基底衬底10上，并且可以具有面向基底衬底10的第一表面S1以及与第一表面S1相对的第二表面S2。半导体衬底110可以是半导体晶片。半导体衬底110可以包括诸如硅(Si)和锗(Ge)之类的半导体元素、或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和磷化铟(InP)之类的化合物半导体。半导体衬底110的底侧或后侧可以覆盖有由氧化硅、氮化硅或其组合形成的绝缘层。
通孔120可以是在竖直方向(Z方向)上穿透半导体衬底110的硅通孔(TSV)。通孔120可以提供将插入衬底100的下表面和上表面上的凸块焊盘101和102彼此连接的电路径。通孔120可以将插入衬底100上的第二互连结构130与基底衬底10的第一互连结构14彼此电连接。通孔120可以包括导电插塞121以及围绕导电插塞121的阻挡层122。导电插塞121可以包括金属，例如，钨(W)、钛(Ti)、铝(Al)或铜(Cu)。可以使用电镀工艺、物理气相沉积(PVD)工艺或化学气相沉积(CVD)工艺来形成导电插塞121。阻挡层122可以包括绝缘阻挡层或/和导电阻挡层。绝缘阻挡层可以包括氧化物、氮化物、碳化物、聚合物或其组合。导电阻挡层可以设置在绝缘阻挡层与导电插塞121之间。导电阻挡层可以例如包括金属化合物，例如氮化钨(WN)、氮化钛(TiN)或氮化钽(TaN)。可以使用PVD工艺或CVD工艺来形成阻挡层122。
互连区域130可以设置在插入衬底100的顶侧或前侧上或半导体衬底110的第二表面S2上，并且可以包括第一层间绝缘层131和第二互连结构132。第一层间绝缘层131可以设置在半导体衬底110的第二表面S2上，并且可以包括氧化硅或氮化硅。第二互连结构132可以将多个半导体芯片20互连，或者可以将多个半导体芯片20连接到基底衬底10。第二互连结构132可以包括单金属互连或多金属互连以及接触过孔。接触过孔可以将金属互连彼此连接，或者可以将金属互连与上凸块焊盘102彼此连接。第二互连结构132可以将通孔120与上凸块焊盘102彼此电连接和物理连接。
钝化层140可以设置在插入衬底100的底侧或后侧上，并且可以覆盖第一表面S1的至少一部分。钝化层140可以覆盖插入衬底100的除插入衬底100的边缘之外的其他部分。钝化层140可以具有被形成为暴露插入衬底100的下凸块焊盘101的一部分的开口，并且第二连接凸块32可以设置在该开口中。在示例实施例中，压纹图案可以形成在钝化层140的边缘上，以减少或防止在底部填充树脂40中出现的裂纹沿插入衬底100的下表面蔓延。钝化层140可以包括绝缘聚合物，例如，光敏聚酰亚胺(PSPI)。
连同图1C一起参考图1A和图1B，在半导体封装1000A中，插入衬底100可以具有：第一区域R1，其中包括多个第二连接凸块32；以及第二区域R2和第三区域R3，在第一区域R1的外围外部或与第一区域R1的外围相邻，第二区域R2和第三区域R3中可以没有第二连接凸块32。钝化层140可以设置在第一区域R1和第二区域R2中，并且可以包括第二区域R2中的第一压纹图案141。第二区域R2和第三区域R3可以是或对应于锯切工艺之前的划线道区域SL。第二区域R2的宽度W1可以大于第三区域R3的宽度W2。第三区域R3可以在与插入衬底100的边缘EG2相距与宽度W2相对应的第一距离的范围内。与宽度W2相对应的第一距离可以为约10μm或更多，例如在10μm至50μm的范围内。
半导体衬底110的与第三区域R3相对应的第一表面S1或插入衬底100的下表面可以与底部填充树脂40直接接触，并且可以没有钝化层140。如本文中所使用的那样，当层或元件被称为“直接”或“紧密”在另一层或元件上或者接触或邻近另一层或元件时，不存在中间层或元件。在TC测试期间，在底部填充树脂40的边缘中出现的裂纹可能会沿半导体衬底110的与第三区域R3相对应的第一表面S1以及插入衬底100的下表面引起底部填充树脂40与插入衬底100之间的界面分层。另外，当裂纹蔓延到多个第二连接凸块32之中的最外面的第二连接凸块32a或向第一区域R1的内部蔓延时，插入衬底100的连接可靠性可能会劣化。
在示例实施例中，钝化层140的第一压纹图案141可以与底部填充树脂40直接接触，以减少或防止由裂纹引起的界面分层。另外，可以减少或防止裂纹蔓延到第一区域R1的最外面的第二连接凸块32a，以确保插入衬底100的连接可靠性。用于减少或防止裂纹的钝化层140的高度可以为约1μm或更多。例如，钝化层140的高度可以在1μm至5μm的范围内。钝化层140的高度可以指从半导体衬底110的第一表面S1到第一压纹图案141的凸出部分的高度(即，沿竖直或Z方向)。
连同图1D一起参考图1B和图1C，在半导体封装1000A中，插入衬底100可以具有：包括以矩阵形式布置的多个通孔120的第一区域R1、与第一区域R1的外围相邻或连续围绕第一区域R1的第二区域R2、以及与第二区域R2的外围相邻或连续围绕第二区域R2的第三区域R3。第二区域R2可以被设置为围绕第一区域R1的边缘或边界EG1。钝化层140可以设置在插入衬底100的一个表面上，并且可以覆盖第一区域R1和第二区域R2。第一压纹图案141可以设置在第二区域R2中的钝化层140的表面上。第一压纹图案141可以包括布置在第二区域R2中的多个点状结构。第二区域R2可以通过第三区域R3与插入衬底100的边缘EG2间隔开。多个半导体芯片20可以设置在插入衬底100的另一个表面上。图1D中所示的下凸块焊盘101可以分别限定对应的通孔120的位置。
参考图1E和图1F，可以确认在根据示例实施例的半导体封装1000A中存在裂纹蔓延路径。在TC测试期间，在底部填充树脂40的外部出现的裂纹CR可以沿插入衬底100的下表面蔓延到第一区域R1。在钝化层140的边缘中形成的第一压纹图案141可以与底部填充树脂40直接接触，以防止裂纹CR的蔓延。第一压纹图案141可以与插入衬底100的主要区域或第一区域R1的外围相邻或围绕插入衬底100的主要区域或第一区域R1，并且可以减少或防止由裂纹CR引起的对插入衬底100的损坏。
图2是示出了图1B的半导体封装1000A中的一些组件的修改示例的截面图。图2示出了图1B的半导体封装1000A中的插入衬底100的修改示例。
参考图2，修改的插入衬底100a可以包括钝化层140，钝化层140还包括第二压纹图案142。第一区域R1的边缘或边界EG1可以与多个第二连接凸块32之中的最外面的第二连接凸块32a间隔开预定距离。钝化层140还可以包括在第一区域R1的边缘或边界EG1与最外面的第二连接凸块32a之间(即，在第二区域R2与最外面的第二连接凸块32a之间)的第二压纹图案142。第二压纹图案142可以进一步增大与底部填充树脂40的接触面积。另外，第二压纹图案142可以减少或防止由于裂纹引起的对最外面的第二连接凸块32a的损坏。
图3A和图3B是根据示例实施例的半导体封装1000B的截面图。
参考图3A和图3B，半导体封装1000B还可以包括与图1B的第一压纹图案141相对应的第一虚设图案143-1。可以不在设备操作或功能中使用本文中所描述的虚设图案。插入衬底100还可以包括在第一表面S1或插入衬底100的一个表面(或者，下表面)上的第一虚设图案143-1，并且第一虚设图案143-1可以设置在第二区域R2中以被钝化层140覆盖。钝化层140的第一压纹图案141可以具有与第一虚设图案143-1相对应或符合第一虚设图案143-1的弯曲形状。可以使用第一虚设图案143-1来形成第一压纹图案141，而无需用于形成第一压纹图案141的附加工艺(例如，光刻蚀刻工艺)。第一虚设图案143-1的线宽(第一虚设图案143-1在X方向上的宽度)可以为约0.5μm或更多，并且相邻的第一虚设图案143-1之间的间距(相邻的第一虚设图案143-1之间的在X方向上的距离)可以是0.5μm或更多。例如，第一虚设图案143-1的线宽可以在0.5μm至5μm的范围内，并且相邻的第一虚设图案143-1之间的间距可以在0.5μm至5μm的范围内。覆盖第一虚设图案143-1的钝化层140的高度可以为约1.5μm或更多。例如，钝化层140的高度可以在1.5μm至5μm的范围内。钝化层140的高度可以被限定为从半导体衬底110的第一表面S1到第一压纹图案141的凸出部分的高度。
第一虚设图案143-1可以与下凸块焊盘101实质上共面。第一虚设图案143-1可以包括与下凸块焊盘101相同的金属。第一虚设图案143-1的厚度可以与下凸块焊盘101的厚度实质上相同。第一虚设图案143-1可以具有点图案形状或线图案形状。
图4A和图4B是示出了图3A的半导体封装1000B中的一些组件的修改示例的截面图。图4A和图4B示出了图3A的半导体封装1000B中的插入衬底100的修改示例。
参考图4A，修改的插入衬底100b可以包括钝化层140，钝化层140还包括第二虚设图案143-2。插入衬底100b还可以包括在半导体衬底110的第一表面S1或插入衬底100b的一个表面(或者，下表面)上的第二虚设图案143-2，并且第二虚设图案143-2可以覆盖有钝化层140。第二虚设图案143-2可以设置在第一区域R1的边缘或边界EG1与最外面的第二连接凸块32a之间。第二虚设图案143-2可以设置在第一区域R1内的最外面的第二连接凸块32a的外围的外部，或者被设置为与第一区域R1内的最外面的第二连接凸块32a的外围相邻。第二压纹图案142可以具有与第二虚设图案143-2的表面相对应或符合第二虚设图案143-2的表面的弯曲形状。第二虚设图案143-2的线宽(第二虚设图案143-2在X方向上的宽度)可以为约0.5μm或更多，并且相邻的第二虚设图案143-2之间的间距(相邻的第二虚设图案143-2之间的在X方向上的距离)可以为约0.5μm或更多。例如，第二虚设图案143-2的线宽可以在0.5μm至5μm的范围内，并且相邻的第二虚设图案143-2之间的间距可以在0.5μm至5μm的范围内。覆盖第二虚设图案143-2的钝化层140的高度可以为约1.5μm或更多。例如，钝化层140的高度可以在1.5μm至5μm的范围内。钝化层140的高度可以被限定为从半导体衬底110的第一表面S1到第二压纹图案142的凸出部分的高度。
参考图4B，修改的插入衬底100c可以包括钝化层140，钝化层140包括第一压纹图案141和第二压纹图案142以及第二虚设图案143-2。在本修改示例中，可以省略与划线道区域相对应的第二区域R2中的虚设图案，但是本公开不限于此。第一压纹图案141和第二压纹图案142以及第一虚设图案143-1和第二虚设图案143-2可以以各种形式组合，并且不限于所示出的示例。因此，参考图1B、图2、图3B、图4A和图4B，在示例实施例中，插入衬底100可以包括：设置在第一表面S1上的多个下凸块焊盘101、设置在第一表面S1上的多个下凸块焊盘101的外部或外围上的虚设图案143-1和/或143-2、通过半导体衬底110将第二互连结构132与多个下凸块焊盘101彼此电连接的多个通孔120、以及覆盖多个下凸块焊盘101以及多个虚设图案143-1和/或143-2的钝化层140。钝化层140可以与插入衬底100的边缘EG2间隔开预定距离，并且可以具有沿多个虚设图案143-1和/或143-2的表面弯曲或实质上符合多个虚设图案143-1和/或143-2的表面的压纹图案141和/或142。多个虚设图案143-1和/或143-2可以与多个下凸块焊盘101电绝缘。
图5A至图5C是示出了根据各种示例实施例的半导体封装的插入衬底的平面图。
参考图5A至图5C，在各种示例实施例中，可以以如下方式设置第一压纹图案141和第二压纹图案142：将各自具有预定长度的多个条状结构和/或多个点状结构进行组合，以围绕多个下凸块焊盘101或多个通孔120的外部或外围。
例如，如图5A中所示，在根据示例实施例的插入衬底100d中，第一压纹图案141和第二压纹图案142可以以这样的方式设置：多个条状结构围绕第一区域R1以及多个下凸块焊盘101(或者，最外面的下凸块焊盘101a)的外部或周边。多个条状结构141B和142B可以被形成为沿第一区域R1的边缘或边界EG1延伸。
例如，如图5B中所示，在根据示例实施例的插入衬底100e中，第一压纹图案141和第二压纹图案142可以以这样的方式设置：将多个条状结构141B和142B以及多个点状结构141D和142D进行组合，以围绕第一区域R1以及多个下凸块焊盘101(或者，最外面的下凸块焊盘101a)的外部。多个条状结构141B和142B可以设置在拐角部分C中，并且多个点状结构141D和142D可以设置在条形部分D中。多个条状结构141B和142B可以在拐角部分C处弯折或成角度。
例如，如图5C中所示，在根据示例实施例的插入衬底100f中，第一压纹图案141和第二压纹图案142可以包括彼此平行地布置的多个条状结构141B和142B。在示例实施例中，一些条状结构141B'可以被设置为与第一区域R1和第二区域R2重叠。在示例实施例中，条状结构141B和142B以及点状结构141D和142D可以以除图5A至图5C的示例中所示的形状之外的各种形式组合。
图6是根据示例实施例的半导体封装1000C的截面图。
参考图6，半导体封装1000C可以包括设置在半导体衬底110的前侧上的第一互连区域130以及设置在半导体衬底110的底侧(或者，后侧)上的第二互连区域150。第二互连区域150可以包括第二层间绝缘层151和第三互连结构152。第二层间绝缘层151可以设置在半导体衬底110的第一表面S1上，并且可以包括氧化硅或氮化硅。第三互连结构152可以包括单金属互连。然而，本公开不限于此，并且第三互连结构152可以包括比附图中所示的金属互连和接触过孔更少或更多的金属互连和接触过孔。接触过孔可以将第三互连结构152与下凸块焊盘101连接。通孔120可以将第二互连结构132与第三互连结构152彼此电连接。第二互连结构132和第三互连结构152可以实质上重新分布半导体芯片20的连接端子。
图7是根据示例实施例的半导体封装1000D的截面图。
参考图7，半导体封装1000D还可以包括插入衬底100上的模制构件50、基底衬底10上的加强件60、以及散热件70。模制构件50可以包封插入衬底100上的多个半导体芯片20的至少一部分。模制构件50例如可以包括诸如环氧树脂之类的热固性树脂、诸如聚酰亚胺树脂之类的热塑性树脂、包括无机填料和/或玻璃纤维的预浸料、味之素积层膜(ABF)、FR-4、双马来酰亚胺三嗪(BT)、环氧模塑化合物(EMC)等。模制构件50还可以包括填充插入衬底100与半导体芯片20之间的空间的底部填充树脂。在这种情况下，底部填充树脂可以是以模制底部填充(MUF)方式形成的模制构件50的一部分。
加强件60可以设置在基底衬底10上，以控制封装的翘曲。加强件60可以设置在基底衬底10上，以连续或不连续地围绕半导体芯片20的侧表面。加强件60可以被配置为包括诸如铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金之类的金属。加强件60可以通过结合构件61附接到基底衬底10。结合构件61例如可以是导热胶带、导热油脂、导热粘合剂等。
散热件70可以设置在半导体芯片20上，以将从半导体芯片20生成的热量散发到半导体封装1000D的外部或外面。散热件70可以设置在加强件60上，并且可以与半导体芯片20接触。散热件70可以是覆盖半导体芯片20的上表面的板的形式。散热件70可以包括诸如金(Au)、银(Ag)或铜(Cu)之类的金属，或者包括诸如石墨或石墨烯之类的导电材料。散热件70可以通过与加强件60相似的粘合构件71附接到加强件60或半导体芯片20。
图8是根据示例实施例的半导体封装1000E的截面图。
参考图8，半导体封装1000E可以包括包含不同类型的集成电路的第一半导体芯片至第三半导体芯片21、22和23。第一半导体芯片21可以包括与多个第二半导体芯片22和第三半导体芯片23通信的逻辑电路。
多个第二半导体芯片22可以在竖直方向(Z方向)上堆叠，并且可以通过硅通孔(TSV)22V彼此连接。多个第二半导体芯片22可以包括诸如DRAM、静态RAM(SRAM)之类的易失性存储器器件、以及诸如PRAM、MRAM、RRAM、闪存器件之类的易失性存储器器件。在多个第二半导体芯片22中，第一半导体芯片21可以基于信号存储或输出数据。
第三半导体芯片23可以是中央处理单元(CPU)、图形处理单元(GPU)和片上系统(SoC)中的至少一个，并且可以连接以与第一半导体芯片21通信。在一些实施例中，第三半导体芯片23可以设置在第一半导体芯片21下方。
图9A至图9G是示出了制造图1B的半导体封装1000A中的一些组件的方法的示意性截面图。图9A至图9G示出了制造图1B的插入衬底100的方法。
参考图9A，可以在第一载体C1上的半导体晶片WR上形成通孔120、互连区域130和上凸块焊盘102。半导体晶片WR可以具有通过划线道区域SL划分或分开的多个主要区域MR或第一区域R1，划线道区域SL各自包括接触区域SLa和非接触区域SLb。通孔120可以从半导体衬底110或半导体晶片WR的第二表面S2向半导体衬底110的内部延伸或延伸到半导体衬底110中。通孔120可以包括围绕圆柱形侧表面的导电阻挡层、过孔绝缘层等。过孔绝缘层可以包括氧化物、氮化物、碳化物、聚合物或其组合。
互连区域130可以包括第一层间绝缘层131和第二互连结构132。第一层间绝缘层131可以包括氧化硅。第二互连结构132可以包括多金属互连和接触过孔。可以在互连区域130的表面上形成上凸块焊盘102。第二互连结构132可以将上凸块焊盘102与通孔120彼此电连接。第二互连结构132的一部分可以将上凸块焊盘102互连。可以通过重复地执行光刻工艺、蚀刻工艺、电镀工艺和抛光工艺来形成通孔120和互连区域130。
参考图9B，可以倒置图9A的半导体晶片WR，然后将其附接到第二载体C2。粘合层AD可以存在于第二载体C2的表面上。可以将半导体晶片WR附接到第二载体C2，使得上凸块焊盘102嵌入在粘合层AD中。
参考图9C，可以去除半导体晶片WR的一部分以暴露通孔120，并且可以在半导体晶片WR的第一表面S1上形成下凸块焊盘101。可以使用化学机械抛光(CMP)工艺、回蚀工艺或其组合来去除半导体晶片WR的一部分。可以使用光刻工艺和电镀工艺来形成下凸块焊盘101。可以去除半导体晶片WR以暴露通孔120，而不是第一表面S1。在这种情况下，通孔120的突出侧表面可以被氧化硅层或氮化硅层围绕。
参考图9D，钝化层140可以形成在半导体晶片WR的第一表面S1上。钝化层140可以由绝缘聚合物形成。可以通过例如旋涂工艺或喷涂工艺来形成钝化层140。可以使用光刻工艺等来去除钝化层140的一部分，以暴露下凸块焊盘101。
参考图9E，可以去除图9D的钝化层140的一部分，以暴露下凸块焊盘101和接触区域SLa。可以使用光刻工艺等来去除钝化层140。可以去除钝化层140中的在锯切工艺中与锯片直接接触的接触区域SLa上的一部分，以减少或防止在锯切工艺中出现裂纹。
参考图9F，可以对钝化层140中的在非接触区域SLb上的表面进行处理，以形成压纹图案141。可以使用光刻工艺等来形成压纹图案141。压纹图案141可以形成在主要区域MR的外侧或外围，以阻止裂纹蔓延到主要区域MR的路径。在另一实施例中，可以进一步形成沿主要区域MR的边缘延伸的压纹图案。
参考图9G，可以使用锯片BL沿划线道SL切割半导体晶片WR。锯片BL可以在划线道SL的接触区域SLa内切割半导体晶片WR。在锯切工艺之后，未被锯条BL去除的残留区域RSL可以存在于非接触区SLb的一侧。在锯切工艺之后分开的单独的插入衬底100可以包括与主要区域MR相对应的第一区域R1、与非接触区域SLb相对应的第二区域R2、以及与残留区域RSL相对应的第三区域R3。
如上所述，可以将压纹图案引入到覆盖插入衬底的后侧的钝化层中，以提供具有改善的可靠性的半导体封装。
虽然以上已经示出并描述了示例实施例，但是本领域技术人员应清楚，在不脱离由所附权利要求限定的本发明构思的范围的情况下，可以进行修改和改变。

Claims (20)

1.一种半导体封装，包括：
基底衬底，包括第一互连结构；
插入衬底，包括：具有面向所述基底衬底的第一表面和与所述第一表面相对的第二表面的半导体衬底、在所述第二表面上并且包括第二互连结构的互连区域、延伸通过所述半导体衬底并且将所述第二互连结构电连接到所述第一互连结构的通孔、以及在所述第一表面的至少一部分上的钝化层；
多个连接凸块，在所述基底衬底与所述插入衬底之间，并且将所述通孔电连接到所述第一互连结构；
底部填充树脂，在所述基底衬底与所述插入衬底之间的空间中；以及
第一半导体芯片和第二半导体芯片，在所述插入衬底的所述互连区域上，并且通过所述第二互连结构彼此电连接，
其中，所述插入衬底包括：第一区域，包括所述多个连接凸块；第二区域，与所述第一区域的外围相邻；以及，第三区域，与所述第二区域的外围相邻，
所述钝化层在所述第一区域和所述第二区域中并且包括在所述第二区域中的第一压纹图案，以及
所述第三区域没有所述钝化层。
2.根据权利要求1所述的半导体封装，其中，所述第二区域和所述第三区域没有所述多个连接凸块，并且所述第二区域的宽度大于所述第三区域的宽度。
3.根据权利要求1所述的半导体封装，其中，所述第三区域在与所述插入衬底的边缘相距第一距离的范围内，并且所述第三区域在所述第二区域与所述插入衬底的所述边缘之间。
4.根据权利要求3所述的半导体封装，其中，所述第一距离为10μm或更多。
5.根据权利要求1所述的半导体封装，其中，所述第三区域与所述底部填充树脂直接接触。
6.根据权利要求1所述的半导体封装，其中，所述第一压纹图案的表面与所述底部填充树脂直接接触。
7.根据权利要求1所述的半导体封装，其中，所述第一表面上的所述钝化层与所述插入衬底的边缘间隔开10μm或更多。
8.根据权利要求1所述的半导体封装，其中，所述插入衬底还包括在所述半导体衬底的所述第一表面上的第一虚设图案，其中所述第一虚设图案上具有所述钝化层，
所述第一虚设图案在所述第二区域中，以及
所述第一压纹图案弯曲以符合所述第一虚设图案。
9.根据权利要求1所述的半导体封装，其中，所述第一区域的外围延伸超出所述多个连接凸块之中的最外面的连接凸块预定距离，以及
所述钝化层还包括第二压纹图案，所述第二压纹图案在处于所述第二区域与所述最外面的连接凸块之间的所述第一区域的外围中。
10.根据权利要求9所述的半导体封装，其中，所述插入衬底还包括在所述半导体衬底的所述第一表面上的第二虚设图案，其中所述第二虚设图案上具有所述钝化层，
所述第二虚设图案在处于所述第二区域与所述最外面的连接凸块之间的所述第一区域的外围中，以及
所述第二压纹图案弯曲以符合所述第二虚设图案。
11.根据权利要求1所述的半导体封装，其中，所述插入衬底还包括在所述半导体衬底的所述第一表面上的第三互连结构，以及
所述通孔将所述第二互连结构电连接到所述第三互连结构。
12.一种半导体封装，包括：
插入衬底，具有包括多个通孔的第一区域、与所述第一区域的外围相邻的第二区域、以及与所述第二区域的外围相邻的第三区域；
钝化层，位于所述插入衬底的第一表面上并处于所述第一区域和所述第二区域中，所述钝化层的表面包括所述第二区域中的第一压纹图案；以及
多个半导体芯片，在所述插入衬底的与所述第一表面相对的第二表面上，
其中，所述第二区域与所述插入衬底的边缘间隔开，并且所述第三区域在所述第二区域与所述插入衬底的所述边缘之间。
13.根据权利要求12所述的半导体封装，其中，所述第一压纹图案包括具有预定长度的多个条状结构和/或多个点状结构围绕所述第一区域的形状。
14.根据权利要求12所述的半导体封装，还包括：
第一虚设图案，位于所述插入衬底的所述第一表面上并处于所述第二区域中，其中所述第一虚设图案上具有所述钝化层，
其中，所述第一压纹图案弯曲以符合所述第一虚设图案。
15.根据权利要求12所述的半导体封装，其中，所述钝化层位于所述第一表面上并处于所述第一区域中，并且其中，所述钝化层的表面还包括在所述第一区域内并且与所述多个通孔的外围相邻的第二压纹图案。
16.根据权利要求15所述的半导体封装，其中，所述第二压纹图案包括具有预定长度的多个条状结构和/或多个点状结构围绕所述多个通孔的外围的形状。
17.根据权利要求15所述的半导体封装，还包括：
第二虚设图案，位于所述插入衬底的所述第一表面上并处于所述第一区域中，其中所述第二虚设图案上具有所述钝化层，
其中，所述第二压纹图案弯曲以符合所述第二虚设图案。
18.一种半导体封装，包括：
插入衬底，包括：具有第一表面和与所述第一表面相对的第二表面的半导体衬底、在所述第二表面上并且包括互连结构的互连区域、在所述第一表面上的多个凸块焊盘、在所述第一表面上与所述多个凸块焊盘的外围相邻的多个虚设图案、延伸通过所述半导体衬底并且将所述互连结构电连接到所述多个凸块焊盘的多个通孔、以及在所述多个凸块焊盘和所述多个虚设图案上的钝化层；以及
第一半导体芯片和第二半导体芯片，在所述插入衬底上，并且通过所述互连结构彼此电连接，
其中，所述钝化层与所述插入衬底的边缘间隔开预定距离，并且包括沿所述多个虚设图案的表面弯曲的压纹图案。
19.根据权利要求18所述的半导体封装，其中，所述钝化层与所述插入衬底的所述边缘间隔开10μm或更多。
20.根据权利要求18所述的半导体封装，其中，所述多个虚设图案中的每个虚设图案在第一方向上的线宽为0.5μm或更多，以及
所述多个虚设图案之中的紧邻的虚设图案之间的在所述第一方向上的间距为0.5μm或更多。
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US8952533B2 (en) 2012-09-10 2015-02-10 Futurewei Technologies, Inc. Devices and methods for 2.5D interposers
US9728511B2 (en) 2013-12-17 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer and semiconductor die
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US10177114B2 (en) 2015-11-25 2019-01-08 Invensas Corporation Hybrid 3D/2.5D interposer
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