CN114138360A

CN114138360A - Multi-core programming starting method and system of DSP on Flash

Info

Publication number: CN114138360A
Application number: CN202111342349.XA
Authority: CN
Inventors: 张鹏程; 肖博峰; 周舟; 张昭
Original assignee: Shanghai Huayuan Chuangxin Software Co ltd
Current assignee: Shanghai Huayuan Chuangxin Software Co ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-03-04
Anticipated expiration: 2041-11-12
Also published as: CN114138360B

Abstract

The utility model provides a multi-core programming starting method and a multi-core programming starting system of a DSP (digital signal processor) on a Flash, which comprise the following steps: burning an environment variable, a secondary BootLoader, a primary core operating system mirror image and a preset number of secondary core bare computer programs into Flash; loading a secondary Bootloader from a 0 address of the Flash by using a ROM Bootloader built in the DSP and operating the secondary Bootloader; the secondary Bootloader reads the environment variable from the Flash to obtain the address of the mirror image of the main core operating system in the Flash; the secondary Bootloader loads a primary core operating system mirror image and jumps to a primary core operating system mirror image address for operation; the method comprises the steps that a main core operating system mirror image reads environment variables from Flash at a preset time point according to service requirements, and programming addresses of a preset number of slave core bare machine programs in Flash are obtained; and selecting and starting a slave core bare machine program according to the environment variable, loading the started slave core bare machine program by the main core operating system mirror image, setting the running ADDRESS of the slave core bare machine program to the BOOT _ MAGIC _ ADDRESS ADDRESS of the slave core, sending IPC interrupt to the slave core, and running the slave core.

Description

Multi-core programming starting method and system of DSP on Flash

Technical Field

The utility model relates to the technical field of power-on self-booting of embedded equipment, in particular to a multi-core programming starting method and a multi-core programming starting system of a DSP (digital signal processor) on a Flash.

Background

At present, with its high performance, DSP is widely used in signal processing field. The high-performance DSP commonly used in the market is TMS320C6678 chip of TI company and a domestic DSP chip substituted by the TMS chip. The starting modes of the devices comprise a plurality of types such as EMIF, SRIO, Ethernet, PCIE, I2C, SPI, UART and NAND. The local boot is usually started using SPI Flash or EMIF Flash. The TMS320C6678 chip and the alternative domestic DSP chip both give a detailed description of the two starting modes, but the starting modes jump to the execution of a loaded program after the ROM Bootloader finishes loading the program, so that the control right is given out, and a great play space is provided for a user. The user only needs to make the program loaded by the ROM Bootloader meet the required format. The program loaded by the ROM Bootloader can be a secondary Bootloader or a service program. In some scenarios, the primary core is required to run the operating system, and the secondary core is required to run the bare metal program. Searching the existing patent, a solution to the scene directly is not found. On the other hand, for the programming method, the official example of the TMS320C6678 chip provides a method for programming one file by running an example program once through a JTAG emulator, multiple times of running and programming multiple files are required, and flexibility is not achieved; a domestic DSP manufacturer provides a multi-core programming example started based on SPI Flash, and needs to use a special tool to merge and format-convert an out file in ELF format generated by each core to obtain a dat file to be programmed, which cannot individually program each core, nor is flexible enough.

Patent document CN101178658A (application No. 200710171619.9) discloses an upgrade system and an upgrade method based on DSP, which are used for upgrading an embedded system based on DSP, and include: the de-multiplexing module is used for obtaining upgrading data from the transmission stream; utilizing a starting loading module to execute the initialization of hardware equipment and distributing flash memories which store a starting loading program and a DSP main program; the interactive module provides users with real-time understanding of the upgrading progress condition of the embedded system, and the upgrading system and the upgrading method of the utility model can solve the problem of manual service of the existing upgrading system, thereby saving the later labor cost and providing a convenient, reliable and low-cost implementation method for the implementation of projects and the upgrading of later value-added modules.

Patent document CN111506334A (application number: 202010345859.1) discloses a method and system for online upgrading a program of a DSP chip, which receives an online upgrade instruction and a program file sent by an upper computer through a FLASH of the DSP chip, updates a start program in the FLASH according to the online upgrade instruction, and writes storage location data of the start program in the FLASH into a CMD file; and restarting the DSP chip, and leading the R AM of the DSP chip into the updated starting program in the FLASH according to the command of the CMD file and running the starting program, so that the DSP program is carried from the FLASH to the RAM for running, thereby improving the running speed of the program, automatically running from the newly upgraded program when the DSP chip is electrified next time, and avoiding the running program from collapsing when an error occurs in the upgrading process.

Patent document CN110427223A (application number: 201910587781.1) discloses a method for dynamically loading a multi-core DSP based on a PCIE bus of an upper computer, the method including: the multi-core DSP is in communication connection with an upper computer; transmitting a program to the multi-core DSP; triggering a PCIE MSI interrupt to enable the multi-core DSP to run the program; and the multi-core DSP receives data from the upper computer in a PCIE DMA mode and returns the operation result of the running program to the upper computer. The method and the system have the advantages of low cost, low power consumption, small system size, portability and capability of being separated from an external field to quickly carry out related debugging; the rapid loading and starting of the program can be realized under the condition that the system is not restarted, so that the application is flexible, and the debugging time is saved; and the system data transmission efficiency is higher, and the practical transmission efficiency is far higher than that of a common gigabit network interface due to the adoption of a PCIE2.0 protocol.

Patent document CN103955376A (application number: 201410056275.7) discloses a DSP self-starting secondary on-demand loading method, which includes: modularizing a program stored in a ROM externally connected with a DSP according to functions, and dividing the program into an initial BOOT module BOOT, a main frame BOOT module BOOT2 and application modules, wherein the application modules comprise sub application program modules with different functions; after the DSP is powered on and reset, an initial BOOT module BOOT is automatically loaded from the ROM, and the initial BOOT module BOOT is used for loading a main frame BOOT module BOOT 2; the DSP runs an initial BOOT module BOOT, and then loads a main frame BOOT module BOOT2 from the ROM; the DSP runs the main frame BOOT module BOOT2 and then loads the corresponding sub application modules from the ROM application module according to the requirements of the main control unit. The utility model effectively avoids the function module integration process brought by the traditional one-time program loading method, thereby maximally using the internal resources of the DSP hardware.

Patent document CN205692152U (application number: CN201521044700.7) discloses an improved structure of a DSP start-up mode, which includes Flash and DSP connected in a single way, where the DSP includes a CPU and a memory; the Flash is connected with the DSP through an EMIF bus; the Flash comprises a moving program block and an application program block; the application program block enters the memory in the DSP through the moving program block; the boot program is stored in the Flash, the DSP executes the boot program after the power is on, the application program is moved to the DSP memory from the Flash, and then the program is executed from the memory, so that the execution speed is higher, and the operation efficiency is improved.

Patent document CN106293807A (application number: 201610595947.0) discloses a Flash chip boot loading method based on DSP. The utility model adopts a method of firstly programming the process of guiding and loading a Flash chip to a monitoring program, and utilizes a serial port to transmit data, firstly programming a monitoring program to the front half part of the Flash chip, then electrifying the monitoring program again to automatically start the monitoring program, programming an application program to the rear half part of the Flash chip, and electrifying a change-over switch again to realize the self-starting of the application program. The whole process is free from the constraint of a JTAG simulator when the application program is programmed, so that the upgrading and maintenance of system software during the external field test are more convenient and operable. Meanwhile, the Bootloader program is controlled in 1 Kbyte, so that the trouble that the Bootloader needs to be written and operated twice is avoided.

Patent document CN106569833A (application number: 201610998885.8) discloses a method for online upgrading a DSP program with a secondary BOOT, first copying a section of the secondary BOOT program from a ROM area to a RAM area and starting execution from a first address of the secondary BOOT program; then the DSP guides the online upgrading program from the ROM area to the RAM area and runs the online upgrading program; the upper computer issues a data frame of the program through the communication module; after writing the data frame into the ROM area, the ROM operation module replies a confirmation frame to the upper computer until the data frame is completely issued; and the functional program area in the ROM area is verified and the verification result is transmitted to the upper computer. The online upgrading program and the functional program provided by the utility model exist relatively independently, and the RAM expenditure in operation can be effectively saved. The two-stage BOOT program segment provided by the utility model is short, can be quickly started, guides the program in the function area or the online upgrading area to the RAM and runs, and is very suitable for industrial occasions with strict real-time requirements.

Patent document CN107506208A (application number: 201710574750.3) discloses an online upgrade method for DSP firmware for preventing equipment from burning out, which divides FLASH into two partitions: an application partition and a secure programming firmware partition; the application program partition is used for installing DSP application program firmware for realizing product functions; the safe programming firmware partition is used for installing safe programming firmware, and the safe programming firmware is used for realizing online upgrading of DSP application program firmware; the firmware of the safe programming firmware partition is programmed before leaving factory, and the content of the partition cannot be changed in subsequent use or upgrade. The utility model uses the FLASH double-partition DSP firmware installation mode, and executes the firmware upgrading operation by the safe programming firmware, thereby avoiding the problems that the DSP firmware can not be started and the subsequent firmware can not be programmed due to the abnormal upgrading firmware.

Patent document CN108038067A (application number: CN201711447008.2) discloses a method for programming DSP user programs through a serial port, belonging to the field of information technology, and characterized by comprising the following steps: (1) configuring the DSP to be started from Flash; (2) dividing the Flash into a plurality of sectors, and selecting any one of the sectors to solidify a Bootloader program; (3) connecting an upper computer with the DSP through a serial port to perform data communication; (4) executing a Bootloader program solidified in the Flash and a control instruction transmitted by the upper computer until the programming of the user program data is completed. Only one GPIO is needed for configuration, so that the programming flexibility is improved; the RS422 is used for data transmission, so that the transmission distance and the data transmission reliability can be increased, and the updating requirement of the external field program can be met.

Patent document CN108762828A (application number: 201810372343.9) discloses a DSP multi-core array secondary startup method and device, the method includes: solidifying the pre-loaded user main program into a FLASH memory of an external host; solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array; when the DSP multi-core array is started, generating a power-on reset signal and determining whether a DSP secondary starting mode is started or not; calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program; and starting and running the user main program in a processor of the DSP multi-core array. The utility model adopts a secondary program loading starting mode to realize that the DSP multi-core array directly loads the user main program without depending on an external network and an external control device.

Patent document CN109213531A (application number: 201811015884.2) discloses a simplified implementation method of power-on self-starting of a multi-core DSP based on EMIF16, and belongs to the technical field of power-on self-booting of embedded devices. Through the three-level loading process, the multi-core program is stored in a segmented mode by modifying the CMD file, and the program programming function and the secondary bootstrap program are written, so that the compiling and programming processes of the multi-core program can be completed under the same CCS engineering, and finally the power-on self-starting of the multi-core DSP program is correctly realized. The method provided by the utility model abandons the current complex processing process of electrifying self-starting of the multi-core DSP, does not need to respectively build projects for compiling the multi-core program, omits the step of manually synthesizing a plurality of mapping files, and improves the loading efficiency of the multi-core program; the method for programming the programming function in engineering is adopted, so that the programming of the multi-core program is convenient; the power-on loading process is simple, the readability of the program is higher, the debugging period is greatly shortened, and the correct and reliable loading operation of the multi-core DSP software can be realized.

Patent document CN107656773A (application number: 201710898403.6) discloses a multi-core DSP boot method, which includes the steps of: s1, setting a ROM region in a multi-core DSP chip, loading a pre-established start loading program in the ROM region, wherein the start loading program comprises a plurality of start modes for starting the multi-core DSP chip of a plurality of peripheral devices, and configuring the peripheral devices required to be adopted when the chip is started and the start modes required to be adopted by the peripheral devices through a start mode register; and S2, after the chip is reset, the main core executes a starting loading program, reads a starting mode register, acquires a target peripheral required to be adopted currently and a target starting mode required to be adopted, loads a user program, and after the user program is loaded, jumps the other cores to a specified address by an interrupt mode to start executing respective user programs. The utility model can realize multi-peripheral multi-mode multi-core DSP starting, and has high memory utilization rate and efficiency, wide application range and strong flexibility.

Patent document 103064806B (application number: 201210589013.8) discloses a method for controlling DSP to realize secondary startup by using CPLD, the program of DSP in the embedded system of the present invention is stored in the off-chip program memory; each time the DSP program is powered on, the loading needs to be divided into a first-level loading stage and a second-level loading stage; the first stage is automatically carried out by the DSP in a DMA or EDMA mode, a section of code at the beginning of an off-chip program memory is transmitted to the on-chip address 0x00 for execution, and the whole transmission process is not controlled by a user; the secondary loading is carried out on the basis of successful primary loading, and the code executing the primary loading copies the application program of the user from a loading address to a running address. The utility model has the advantages of short secondary start, high reliability of the judging mode, easy code compiling, convenient debugging, convenient and flexible signal monitoring on the IO pin by using the oscilloscope and convenient and flexible connection with the DSP, and is convenient for the wiring of the printed board.

Patent document CN111190772A (application number: cn202010004472.x) discloses a DSP secondary start system and method for resisting space single event upset, which solidifies three identical user main programs into two independent external NOR FLASH memories; solidifying the monitoring program into an external PROM memory; determining to enter a two-out-of-three loading main program or enter an on-orbit programming state according to an on-orbit programming register inside the FPGA; the anti-fuse FPGA receives an RS422 instruction and an upper injection program; an external SRAM of the FPGA is used as an upper note program for caching; after receiving an on-orbit programming instruction, the FPGA monitors a program to enter an on-orbit programming mode; the FPGA receives the FLASH switching instruction and then controls the chip selection signal switching between the FLASH1 and the FLASH 2. Compared with the existing secondary starting method for performing triple modular redundancy on the whole FLASH or DSP minimum system, the method can reduce the occupied printed board area and obviously reduce the hardware cost on one hand, and can obtain lower single event upset failure rate by using two FLASH chips by storing three programs in one FLASH chip on the other hand.

In summary, the existing DSP boot solution focuses on expanding the DSP upgrade manner (e.g., online upgrade, expanding the hardware interface type of the transmission program file, and adding upgrade options during the boot process), increasing the operation speed, enhancing the boot stability, and simplifying the operation. The simplified implementation method for multi-core DSP power-on self-starting based on EMIF16 is used for simplifying operation, programs of all cores are divided into different segment spaces by modifying cmd files of a single CCS project, program segments of out files generated by CCS project compiling are copied to addresses designated by the cmd files in the loading process of a simulator, loaded program segments are burnt into Flash by forcibly pointing a PC pointer to a burning function in the same project, programs of a plurality of cores are burnt at one time, and the method has good creativity. But generally, a user is more familiar with directly compiling the generated out file by using a development tool, wherein the out file is in an ELF format.

Disclosure of Invention

Aiming at the defects in the prior art, the utility model aims to provide a method and a system for starting multi-core programming of a DSP on a Flash.

The multi-core programming starting method of the DSP on the Flash provided by the utility model comprises the following steps:

step S1: burning an environment variable, a secondary BootLoader, a primary core operating system mirror image and a preset number of secondary core bare computer programs into Flash;

step S2: loading a secondary Bootloader from a 0 address of the Flash by using a ROM Bootloader built in the DSP and operating the secondary Bootloader;

step S3: the secondary Bootloader reads the environment variable from the Flash to obtain the address of the mirror image of the main core operating system in the Flash;

step S4: the secondary Bootloader loads a primary core operating system mirror image and jumps to a primary core operating system mirror image address for operation;

step S5: the method comprises the steps that a main core operating system mirror image reads environment variables from Flash at a preset time point according to service requirements, and programming addresses of a preset number of slave core bare machine programs in Flash are obtained;

step S6: and selecting and starting a slave core bare machine program according to the environment variable, loading the started slave core bare machine program by the main core operating system mirror image, setting the running ADDRESS of the slave core bare machine program to the BOOT _ MAGIC _ ADDRESS ADDRESS of the slave core, sending IPC interrupt to the slave core, and running the slave core.

Preferably, the DSP is a TMS320C6678 chip or a domestic substitute chip; the Flash is SPI Flash or EMIF Flash.

Preferably, the step S1 includes:

step S1.1: planning spaces respectively occupied by environment variables, a secondary BootLoader, operating system images of a main core and bare computer programs of a preset number of secondary cores in Flash;

step S1.2: and burning the environment variable, the secondary BootLoader, the operating system image of the main core and the bare computer programs of the preset number of the secondary cores into Flash at one time by using a JTAG simulator.

Preferably, the planning of the environment variables, the secondary BootLoader, the operating system images of the primary core and the bare computer programs of the preset number of secondary cores in the Flash respectively occupy spaces which are not overlapped with each other; the preset number of slave bare computer programs occupy the preset number of Flash spaces.

Preferably, the step S2 includes: and the file format generated by compiling the secondary Bootloader is converted according to the requirement of a ROM Bootloader loading program built in the DSP.

Preferably, the environment variable burn-in Flash includes: burning the environment variable to a corresponding address in Flash, and setting the operating system mirror image of the main core and the burning addresses of the bare computer programs of the preset number of secondary cores in Flash according to the environment variable; and according to the environment variable setting, selecting to load and start the corresponding bare metal program of the corresponding slave core.

Preferably, the operating system image of the primary core and the bare computer programs of the preset number of secondary cores are in an ELF format, and the ELF format is generated by default compiling of a CCS development environment and a Rede development environment without format conversion.

Preferably, the secondary Bootloader and the primary kernel operating system image perform file parsing and loading an ELF format file according to an ELF V1.2 standard.

The multi-core programming starting system of the DSP on the Flash provided by the utility model comprises the following components:

module M1: burning an environment variable, a secondary BootLoader, a primary core operating system mirror image and a preset number of secondary core bare computer programs into Flash;

module M2: loading a secondary Bootloader from a 0 address of the Flash by using a ROM Bootloader built in the DSP and operating the secondary Bootloader;

module M3: the secondary Bootloader reads the environment variable from the Flash to obtain the address of the mirror image of the main core operating system in the Flash;

module M4: the secondary Bootloader loads a primary core operating system mirror image and jumps to a primary core operating system mirror image address for operation;

module M5: the method comprises the steps that a main core operating system mirror image reads environment variables from Flash at a preset time point according to service requirements, and programming addresses of a preset number of slave core bare machine programs in Flash are obtained;

module M6: and selecting and starting a slave core bare machine program according to the environment variable, loading the started slave core bare machine program by the main core operating system mirror image, setting the running ADDRESS of the slave core bare machine program to the BOOT _ MAGIC _ ADDRESS ADDRESS of the slave core, sending IPC interrupt to the slave core, and running the slave core.

Preferably, said module M1 comprises:

module M1.1: planning spaces respectively occupied by environment variables, a secondary BootLoader, operating system images of a main core and bare computer programs of a preset number of secondary cores in Flash;

module M1.2: burning the environment variable, the secondary BootLoader, the operating system mirror image of the main core and the bare computer programs of the preset number of secondary cores into Flas at one time by using a JTAG simulator;

planning spaces respectively occupied by environment variables, a secondary BootLoader, operating system images of a main core and bare computer programs of a preset number of secondary cores in Flash, wherein the spaces are not overlapped with each other; the preset number of slave bare computer programs occupy the preset number of Flash spaces;

the module M2 includes: and the file format generated by compiling the secondary Bootloader is converted according to the requirement of a ROM Bootloader loading program built in the DSP.

Preferably, the DSP is a TMS320C6678 chip or a domestic substitute chip; the Flash is SPI Flash or EMIF Flash;

the environment variable burn-in Flash includes: burning the environment variable to a corresponding address in Flash, and setting the operating system mirror image of the main core and the burning addresses of the bare computer programs of the preset number of secondary cores in Flash according to the environment variable; selecting to load and start the bare computer programs of corresponding slave cores according to the setting of the environment variables;

the main core operating system mirror image and the preset number of bare computer programs of the secondary cores are in an ELF format, the ELF format is generated by default compiling of a CCS development environment and a Rede development environment, and format conversion is not needed;

and the secondary Bootloader and the main kernel operating system mirror image execute file analysis and loading an ELF format file according to the ELF V1.2 standard.

Compared with the prior art, the utility model has the following beneficial effects:

1. for an application scene that a DSP main core runs an operating system and a slave core runs a bare computer program, a programming starting scheme is provided;

2. bootloader, a main core operating system mirror image, the programming addresses of all the slave core bare machine programs and which cores to start can be controlled by environment variables, and the programming parts can be controlled by a custom programming project, so that the method has high flexibility;

3. the operating system image of the main core and the bare computer program of the secondary core are in an ELF format, can be generated by default compiling of a CCS development environment of TI and a Rede development environment of China department of Electrical 32, and do not need format conversion, thereby simplifying the operation.

Drawings

Other features, objects and advantages of the utility model will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a general block diagram of a multi-core programming starting method of a DSP on Flash;

FIG. 2 is an implementation of a secondary Bootloader;

FIG. 3 is a step of the master core operating system starting the slave core;

FIG. 4 is an ELF executable file format;

FIG. 5 illustrates steps of parsing and loading an ELF executable file.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the utility model, but are not intended to limit the utility model in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the utility model. All falling within the scope of the present invention.

Example 1

step S1: burning an environment variable, a secondary BootLoader, a main core operating system mirror image and 7 slave core bare computer programs into Flash;

step S2: loading a secondary Bootloader from a 0 address of Flash by using a ROM Bootloader (RBL) built in a DSP manufacturer and operating the secondary Bootloader;

step S5: the method comprises the steps that a main core operating system mirror image reads environment variables from Flash at a preset time point according to service requirements, and programming addresses of 7 slave core bare machine programs in Flash are obtained;

Specifically, the DSP is a TMS320C6678 chip of TI company or a domestic substitute chip; the Flash is SPI Flash or EMIF Flash.

Specifically, the primary core runs a secondary Bootloader and an operating system, and the secondary core runs a bare computer program; the bare metal program refers to a program that does not run an operating system.

Specifically, the step S1 includes:

step S1.1: planning spaces respectively occupied by environment variables, a secondary BootLoader, an operating system mirror image of a main core and bare computer programs of 7 slave cores in Flash;

step S1.2: and burning the environment variable, the secondary BootLoader, the operating system image of the main core and the bare computer programs of 7 slave cores into Flash at one time by using a JTAG simulator.

Specifically, the planning of the spaces respectively occupied by the environment variables, the secondary BootLoader, the operating system image of the master core and the bare computer programs of the 7 slave cores in Flash are not overlapped with each other; the bare computer programs of 7 slave cores occupy 7 Flash spaces. And loading the self-defined programming project through the JTAG simulator for one-time programming.

Specifically, the step S2 includes: the secondary Bootloader is independently developed by the Chinese electronic department 32, and the format of a file generated by compiling is converted according to the requirement of a ROM Bootloader loading program built in a DSP manufacturer.

Specifically, the environment variable burn-in Flash includes: the environment variable is programmed to a determined address in Flash, an operating system mirror image of a main core and a programming address of a bare machine program of a slave core in Flash are set according to the environment variable, and the slave cores can be set to be loaded and started.

Specifically, the operating system image of the primary core and the bare computer program of the secondary core are in an ELF format, and the ELF format is generated by default compiling of a CCS development environment of the TI and a Rede development environment of the chinese electrical department 32, and format conversion is not needed.

Specifically, the process of loading the ELF format file by the secondary Bootloader and the primary core operating system is independently developed by the chinese electrical department 32, and file analysis and loading are performed according to the ELF V1.2 standard.

module M1: burning an environment variable, a secondary BootLoader, a main core operating system mirror image and 7 slave core bare computer programs into Flash;

module M2: loading a secondary Bootloader from a 0 address of Flash by using a ROM Bootloader (RBL) built in a DSP manufacturer and operating the secondary Bootloader;

module M5: the method comprises the steps that a main core operating system mirror image reads environment variables from Flash at a preset time point according to service requirements, and programming addresses of 7 slave core bare machine programs in Flash are obtained;

Specifically, the module M1 includes:

module M1.1: planning spaces respectively occupied by environment variables, a secondary BootLoader, an operating system mirror image of a main core and bare computer programs of 7 slave cores in Flash;

module M1.2: and burning the environment variable, the secondary BootLoader, the operating system image of the main core and the bare computer programs of 7 slave cores into Flash at one time by using a JTAG simulator.

Specifically, the module M2 includes: the secondary Bootloader is independently developed by the Chinese electronic department 32, and the format of a file generated by compiling is converted according to the requirement of a ROM Bootloader loading program built in a DSP manufacturer.

Example 2

Example 2 is a modification of example 1

The general framework of the utility model is shown in figure 1. Planning the space respectively occupied by the environment variable, the secondary Bootloader, the ELF format operating system mirror image of the main core and the ELF format bare computer programs of the 7 slave cores in Flash, and loading a programming project by using a JTAG simulator to burn in Flash at one time. The Flash can be SPI Flash or EMIF Flash, and the hardware sets the start mode of DSP correspondingly. When the DSP is powered on and started, a ROM Bootloader (RBL) built in a DSP manufacturer loads a secondary Bootloader from a 0 ADDRESS corresponding to Flash according to the content of a starting mode register and runs the secondary Bootloader, the secondary Bootloader reads environment variables from the Flash, obtains a programming ADDRESS of an operating system mirror image of a main core in the Flash, loads an operating system, jumps to the operating system ADDRESS to run, the operating system of the main core reads the environment variables from the Flash at a proper time, obtains the programming addresses of bare computer programs of 7 slave cores in the Flash and starts which slave cores, loads slave core programs according to the programming addresses, sets the running addresses of the slave cores to the BOOT _ MAGIC _ ADDRESS addresses of the slave cores, and sends IPC interrupt to the slave cores to enable the slave cores to run.

Flash takes an S29GL256S chip of span corporation as an example, and describes spaces respectively occupied by an environment variable, a secondary Bootloader, an operating system image of a master core, and bare computer programs of 7 slave cores, as shown in table 1. The S29GL256S chip has 32MB in total, one sector size of 128KB (═ 0x20000), and is connected to the DSP through the EMIF interface. The position of the secondary Bootloader is determined as the position of 0 address, and the address space occupied by the environment variable, the mirror image of the operating system of the main core and the bare computer program of the secondary core can be adjusted according to specific conditions.

TABLE 1 Flash space planning (take S29GL256S chip as an example)

Content providing method and apparatus	Flash offset address	Length (byte)
			Two-level Bootloader	0x0	0xE0000
Environmental variables	0xE0000	0x20000
			Primary kernel operating system images	0x100000	0x300000
Bare machine program for core 1	0x400000	0x180000
			Bare machine program for core 2	0x580000	0x180000
Bare machine program for core 3	0x700000	0x180000
			Bare machine program for core 4	0x880000	0x180000
Bare machine program for core 5	0xA00000	0x180000
			Bare machine program for core 6	0xB80000	0x180000
Bare machine program for core 7	0xD00000	0x180000
			Flash reserved space	0xE80000	0x1180000

The structure of the environment variables is shown in the following code. The Core _ Mask controls which slave cores are loaded and started through a bit Mask mode, bit N controls Core N, the value of bit N is 1 to indicate that Core N is loaded and started, and the value of bit N is 0 to indicate that Core N is not loaded and started. For example, if it is necessary to start cores 0 to 6, Core _ Mask is 0x7 f. The dev _ offset array is used for storing the offset addresses of the operating system image of the main core and the bare computer programs of the slave cores in Flash, wherein dev _ offset [0] represents the offset address of the operating system of the main core in Flash, and dev _ offset [1] -dev _ offset [7] represents the offset addresses of the bare computer programs of the cores 1-7 in Flash. The magic _ id is obtained by performing CRC operation on other members except the magic _ id in the environment variable structure body, and is used for checking the environment variable and ensuring that the environment variable is effective.

The implementation of the secondary Bootloader includes the following steps, as shown in fig. 2.

The method comprises the following steps: initializing a main PLL clock of the DSP chip;

step two: initializing a DDR PLL clock of the DSP chip, and initializing DDR;

step three: initializing an EMIF interface;

step four: reading an environment variable from Flash, and acquiring the address of an ELF format operating system mirror image of a main core in the Flash;

step five: reading the operating system mirror image from the Flash, analyzing an ELF format head, acquiring an entry address of the operating system mirror image, analyzing the information of each program segment, and copying each program segment into a memory.

Step six: and jumping to an entry address of an operating system mirror image for execution, and ending the running of the secondary Bootloader.

The secondary Bootloader is loaded by a ROM Bootloader (RBL for short) built in a DSP manufacturer. For example, for an EMIF interface, the RBL of the TMS320C6678 chip directly directs a program counter PC to the 0 address of Flash, where the 0 address needs to store an executable code segment, and the RBL of the domestic DSP chip is in a Boot Table format, and the domestic DSP chip can analyze the content in the Boot Table format to complete the copying of the program segment. And after the second-level Bootloader is compiled, conversion is carried out according to the RBL requirement of a DSP manufacturer.

The main core operating system adopts a homemade Reworks operating system which is independently researched and developed by the electrical department 32 in China. The step in which it loads the slave core is as follows, as shown in FIG. 3.

The method comprises the following steps: when appropriate time (usually after the hardware resources needed to be used by the slave cores are initialized), the operating system of the master core reads the environment variables from the Flash, and obtains the programming addresses of the ELF format bare engine programs of the 7 slave cores in the Flash and which slave cores are started;

step two: starting from the Core 1, checking the Core _ Mask and judging whether the Core is started or not;

step three: if the core is started, further reading a bare computer program of the core from Flash, analyzing an ELF head, acquiring an entry ADDRESS, setting the entry ADDRESS to the BOOT _ MAGIC _ ADDRESS ADDRESS of the core, analyzing program segment information, copying the program segment to a memory, sending IPC interrupt to the core, and enabling the core to run; if the core is not started, the next core is checked directly.

Step four: the cores 2 to 7 execute the second step and the third step. And (6) ending.

The out files generated by default compilation of the CCS development environment of the TI and the Rede development environment of the China department of Electrical 32 are in an ELF format, and in order to simplify the programming step and ensure the consistency of a JTAG simulator debugging program and the programming files, the ELF format files are directly used by the main core operating system mirror image and the bare computer program of the slave core. The second-level Bootloader loads an operating system mirror image of the primary core, and the operating system of the primary core loads a bare computer program of the secondary core, and the executable file in the ELF format needs to be analyzed and loaded. The ELF format executable file is constructed as shown in FIG. 4, and the parsing and loading process includes the following steps, as shown in FIG. 5.

The method comprises the following steps: reading the ELF head from the Flash and analyzing the ELF head. The structure of the ELF header is shown in the following code, wherein e _ entry is the entry address of the program, e _ phoff is the offset address of the program header table in the ELF file, e _ phntsize is the length of each program header in the program header table, and e _ phnum is the number of program headers in the program header table.

#define EI_NIDENT 16

typedef struct{

unsigned char e_ident[EI_NIDENT]；

Elf32_Half e_type；

Elf32_Half e_machine；

Elf32_Word e_version；

Elf32_Addr e_entry；

Elf32_Off e_phoff；

Elf32_Off e_shoff；

Elf32_Word e_flags；

Elf32_Half e_ehsize；

Elf32_Half e_phentsize；

Elf32_Half e_phnum；

Elf32_Half e_shentsize；

Elf32_Half e_shnum；

Elf32_Half e_shstrndx；

}Elf32_Ehdr；

Step two: and reading a program header table from Flash according to the information of the ELF header. The length of the header table is e _ phentsize multiplied by e _ phnum.

Step three: and analyzing each program head in the program head table, and loading the program segment into the memory. A program header specifies information of a program segment. The format of the program header is shown in the following code, where p _ offset is the offset address of the program segment in the ELF file, p _ vaddr is the virtual address of the memory to which the program segment needs to be loaded, p _ paddr is the physical address of the memory to which the program segment needs to be loaded, and p _ filesz is the length of the program segment. For the program segment with the length p _ filesz >0, reading the segment content from Flash to the physical memory address specified by p _ paddr, and completing the loading of the program segment.

typedef struct{

Elf32_Word p_type；

Elf32_Off p_offset；

Elf32_Addr p_vaddr；

Elf32_Addr p_paddr；

Elf32_Word p_filesz；

Elf32_Word p_memsz；

Elf32_Word p_flags；

Elf32_Word p_align；

}Elf32_Phdr；

Step four: after the second-level Bootloader loads the program segment of the main core operating system, jumping to an entry address pointed by the e _ entry of the ELF head to continue executing; after the main core operating system loads the program segment of the slave core, the BOOT _ MAGIC _ ADDRESS ADDRESS of the slave core is set as the e _ entry value of the ELF head of the slave core bare-metal program, IPC interruption is sent to the slave core, and the slave core is enabled to run. And (6) ending.

The processes of programming the secondary Bootloader, the operating system mirror image of the master core and the bare machine programs of the 7 slave cores are consistent, and only the programming addresses and the lengths are different. For either of them, the programming steps are as follows:

the method comprises the following steps: loading a file to be programmed into a determined memory by using a JTAG simulator;

step two: and (4) running a programming function to complete erasing, writing, reading and verifying.

And executing the programming function for multiple times in the self-defined programming project, and loading the file to be programmed into the memory through single-step execution of the JTAG simulator in cooperation with manual operation, so that all contents can be programmed by executing one project.

The programming environment variable is executed through a special function, and the value of each member of the environment variable is set before Flash is programmed. In particular, which slave cores are started and loaded, and the programming addresses of the operating system of the master core and the bare machine programs of the slave cores in Flash may be set. When the programming function is called, the address parameter of the programming function needs to be consistent with the setting of the environment variable, and the length parameter and the data source address parameter need to be consistent with the size of the file to be programmed and the address loaded to the memory.

Through the self-defined programming engineering, the code can be modified conveniently, only partial content can be programmed at one time, for example, only one bare computer program of a slave core can be programmed, and the method is very flexible.

Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the utility model. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A multi-core programming starting method of a DSP on a Flash is characterized by comprising the following steps:

2. The multi-core programming starting method of the DSP on the Flash according to claim 1, wherein the DSP is a TMS320C6678 chip or a domestic substitute chip; the Flash is SPI Flash or EMIF Flash.

3. The DSP multi-core programming starting method on Flash according to claim 1, wherein the step S1 comprises:

4. The multi-core programming starting method of the DSP on the Flash according to claim 3, wherein spaces respectively occupied by the planning environment variables, the secondary BootLoader, the operating system image of the primary core and the bare computer programs of the preset number of secondary cores in the Flash are not overlapped with each other; the preset number of slave bare computer programs occupy the preset number of Flash spaces.

5. The DSP multi-core programming starting method on Flash according to claim 1, wherein the step S2 comprises: and the file format generated by compiling the secondary Bootloader is converted according to the requirement of a ROM Bootloader loading program built in the DSP.

6. The DSP multi-core programming starting method on Flash according to claim 1, wherein the burning of the environment variable into Flash comprises: burning the environment variable to a corresponding address in Flash, and setting the operating system mirror image of the main core and the burning addresses of the bare computer programs of the preset number of secondary cores in Flash according to the environment variable; and according to the environment variable setting, selecting to load and start the corresponding bare metal program of the corresponding slave core.

7. The DSP multi-core programming starting method on Flash according to claim 1, wherein the main core operating system image and the preset number of slave core bare computer programs are in an ELF format, and the ELF format is generated by default compiling of a CCS development environment and a Rede development environment without format conversion.

8. The DSP multi-core programming starting method on Flash according to claim 7, wherein the secondary Bootloader and the primary core operating system image perform file parsing and loading ELF format files according to ELF V1.2 standard.

9. A multi-core programming starting system of DSP on Flash is characterized by comprising:

10. The DSP on Flash multi-core programming start system according to claim 9, wherein the module M1 comprises:

the module M2 includes: the file format generated by compiling the secondary Bootloader is converted according to the requirement of a ROM Bootloader loading program built in the DSP;

the DSP is a TMS320C6678 chip or a domestic substitute chip; the Flash is SPI Flash or EMIF Flash;