CN109032938A - Multi-core DSP program development adjustment method, documentation of program and loading method - Google Patents
Multi-core DSP program development adjustment method, documentation of program and loading method Download PDFInfo
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Abstract
The invention discloses a kind of multi-core DSP program development adjustment methods, and steps are as follows: the first step, carry out chip number to each dsp chip by fpga chip, obtain the core number of each DSP core inside dsp chip；Second step, physical address of the DSP core in DDR is divided according to the logical address of DSP core private room in DDR, by DSP core each in same dsp chip, the logical address of private room is changed to same logical address in DDR again, establishes the mapping relations of logical address and physical address；Third step writes multi-core DSP documentation of program, divides the logical address of the kernel function and kernel function of each DSP core in DDR private room by chip number, core number in multi-core DSP documentation of program.By the code fusion of multiple DSP cores in a source code file, the function of each DSP core is distinguished the present invention by core number and chip number, improves exploitation debugging efficiency.
Description
Technical field
The present invention relates to a kind of realization multicore digital signal processor (Digital Signal Processor, below letters
Claim DSP) program Efficient Development, adjustment method.
Background technique
In synthetic aviation electronic system, the radio frequency systems such as radar, electronic warfare, communication, navigation, identification gradually adopt logical
Signal and data processing is completed with the processor of change, synthesization.Processor includes field programmable gate array (Field
Programmable Gate Array, hereinafter referred to as FPGA), DSP, central processing unit (Central Processing Unit,
Hereinafter referred to as CPU) etc. processing apparatus, be respectively completed the timing control of system, algorithm is realized and condition managing, DSP usually undertake
The main operation of entire signal processor, completes the realization of radio frequency system core Processing Algorithm.Multi-core DSP is due to powerful
Fixed point, floating-point operation ability, can satisfy avlomcs system integration degree promoted bring performance requirement, substantially
Monokaryon DSP is replaced to be widely used.
It is compared with monokaryon DSP, the development process of multi-core DSP is more complicated.The processing core of multi-core DSP is mutually indepedent, passes through
Internal bus and shared storage area are interconnected intercommunication, can execute function parallel.The exploitation of multi-core DSP needs to complete each
Processing core function write, debug and program load.With most common Texas Instruments (Texas Instruments, below
Abbreviation TI) for KeyStone framework multi-core DSP, development process are as follows:
1. each DSP core individually establishes documentation of program, carries out function and realize and debug；
2. multiple cores access same section of memory simultaneously when in order to avoid program execution, in the shared memory space of DSP, need
Privately owned memory headroom is divided for each core, for storing variable, data segment etc.；
3. image file needed for the documentation of program of pair each core generates load executes multi-core program load.
The above process be also for the multi-core DSP exploitation of other companies it is similar, only specifically execute details difference,
But in the large complicated multi-core DSP functional development of progress avionics system, this traditional development scheme has great lack
It falls into.Large complicated function usually requires to be split as multiple functional modules, is assigned to multiple DSP cores or multi-DSP is handled,
Traditional development scheme needs to safeguard too many DSP documentation of program, is inconvenient.By taking Radar Signal Processing function as an example, due to data
It measures very big, it usually needs use multi-disc multi-core DSP.If then needing to establish using traditional development scheme using 48 core DSP
At least 32 DSP documentation of programs, this is very difficult for the exploitation and maintenance of program.
Summary of the invention
Goal of the invention one of the invention is to provide a kind of multi-core DSP program development adjustment method, solves multi-core DSP chip and passes
The defect for development scheme of uniting improves development efficiency, meets synthetic aviation electronic system functional requirement, and the present invention is based on address weights
Mapping techniques, the method for carrying out exploitation debugging using single DSP documentation of program, substantially increase multi-core DSP development efficiency.
The purpose of invention of the invention is achieved through the following technical solutions:
A kind of multi-core DSP program development adjustment method, the multi-core DSP program are applied to multi-nuclear DSP system, multi-core DSP
System includes more than one multi-core DSP chip, DDR chip and a fpga chip, is more than one multi-core DSP chip
A fpga chip is configured, is that every multi-core DSP chip configures a DDR chip, multi-core DSP program development adjustment method step
It is as follows:
The first step carries out chip number to each dsp chip by fpga chip, and the core for obtaining each DSP core inside dsp chip is compiled
Number；
Second step divides physical address of the DSP core in DDR according to the logical address of DSP core private room in DDR,
By DSP core each in same dsp chip, the logical address of private room is changed to same logical address in DDR again, establishes logically
The mapping relations of location and physical address；
Third step writes multi-core DSP documentation of program, is divided in multi-core DSP documentation of program by chip number, core number
Logical address of the kernel function and kernel function of each DSP core in DDR private room.
Preferably, in the first step, chip number, chip are carried out to each dsp chip according to pin state by fpga chip
Number is sent to each dsp chip by data/address bus, and dsp chip obtains itself chip number.
Preferably, second step comprises the following steps:
1) confirm and divide the logical address of each DSP core private room in DDR chip；
2) logical address divided according to each DSP core, confirms and divides physical address of each DSP core in DDR chip；
3) keep each DSP core physical address constant, by the logic of DSP core private room in DDR each in same dsp chip
Address is changed to same logical address；
4) the MPAX register of configuration XMC carries out the mapping of the logical address and physical address of each DSP core.
Goal of the invention two of the invention is to provide a kind of multi-core DSP documentation of program, by above-mentioned multi-core DSP program
Adjustment method is developed to generate.
Goal of the invention three of the invention is to provide the loading method of above-mentioned multi-core DSP documentation of program, comprising including as follows:
1) the default Starting mode of dsp chip is set by fpga chip for external memory interface starting；
2) dsp chip starts, and the initial address for the FLASH being directed toward according to external memory interface is from FLASH restarting
After completing hardware initialization, the default Starting mode of dsp chip is changed to start by DDR chip, and is sent out to fpga chip
Send reset instruction；
3) after fpga chip receives reset instruction, by each DSP core function in multi-core DSP documentation of program according to DSP core function
The chip number and logical address of energy send the program segment of the DSP core function in corresponding DDR memory, and reset DSP core
Piece；
4) DSP is restarted from DDR after the reset, and the program segment of each DSP core in DDR memory is moved the main core of DSP
On the physical address of the private room of DDR, main core first carries out the program segment for belonging to main core in program segment according to core number, then
It will belong to further according to core number and be respectively individually copied to physical address from the private room of core from the program segment of core, and sent out to from core
Interrupt message is sent, prompts to execute respective program from core, so far multi-core program document load is completed.
The invention has the advantages that when carrying out large complicated multi-core DSP program development, if having used multi-DSP,
Then the program of each core of DSP can be concentrated in a documentation of program developing, the documentation of program for needing to safeguard is greatly reduced
Quantity improves development efficiency.
It by taking 48 core DSP as an example, needs to safeguard 32 DSP documentation of programs using traditional development scheme, and uses based on ground
The mode that location remaps then only needs to safeguard that at most 4 DSP documentation of programs (by periphery circuit design appropriate, can also incite somebody to action
Multiple DSP documentation of programs are integrated, thus only with 1 DSP documentation of program of maintenance), all cores of each DSP are using same
A image file is loaded, and the development efficiency of complicated multicore application program is substantially increased.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of multi-nuclear DSP system；
Fig. 2 is the load schematic diagram of multi-core DSP program file；
Fig. 3 is MPAX register configuration process；
Fig. 4 is the MPAX register words segment description of XMC；
Fig. 5 is the load of dsp chip, programming process.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
Multi-core DSP bottom layer driving can all provide the variable for identifying each DSP core, support multiple DSP cores with a set of journey
Sequence code development, the function that each DSP core complete independently is divided by core serial number and is completed jointly, for using single documentation of program into
The program development of row multi-core DSP, debugging provide the foundation.But each core of DSP is parallel execution function, it is common for multiple cores
The code segment of execution, wherein the definition with use of variable and function are identical, therefore after program loading operation, it may appear that
Multiple DSP cores access identical memory headroom simultaneously, and program is caused to execute error.Therefore traditional multi-core DSP development scheme is led to
It crosses and individual documentation of program is established to each core, divide the addressing space of each core in advance, to avoid the occurrence of multicore while occupy
The case where same memory.
And fundamentally, as long as solving the problems, such as multiple DSP core run-time memory space access conflicts, so that it may so that
Multicore functional development is carried out with a DSP documentation of program.The memory space of DSP is identified using logical address and physical address, is patrolled
There are the mapping relations one by one of default in volume address and physical address, operation logic address when programming, debugging, in load and execution
When be eventually mapped in corresponding physical address.By default, multiple cores execute identical code segment (defined variable, letter
Number etc.) when causing to access same memory headroom, the same logical address can be operated simultaneously and is mapped on the same physical address,
Lead to access conflict.If having changed this default mapping relations, it is ensured that when each DSP core operates same logical address, finally
It is mapped on different physical address, so that it may solve collision problem.
The present embodiment by using DSP extended address management function, the logical address that multi-core DSP is accessed jointly according to
DSP core serial number is remapped to different physical address, and DSP core each in this way can use identical program code to carry out journey
Sequence exploitation debugging.
The structure of the multi-nuclear DSP system that the present embodiment uses as shown in Figure 1, multi-nuclear DSP system include a piece of FPGA core and
Four dsp chips, DSP model are the multi-core DSP chip TMS320C6678 of TI company, have 8 high-performance treatments cores, can
With execution function independent of each other.The peripheral circuit of each dsp chip further includes dual rate synchronous DRAM
(Double Data Rate SDRAM, hereinafter referred to as DDR) and flash memory (FLASH EEPROM Memory, hereinafter referred to as
FLASH)。
In most of sophisticated functions platforms such as avionics system, the function that dsp chip executes is complex, Ge Gehe
Space requirement for storing private variable and data is larger, therefore this system divides the privately owned operation sky of each core in DDR
Between for storing code segment, data segment.FLASH has cured Bootloader when DSP is powered on, and FPGA is for controlling DSP's
Peripheral pin state determines that DSP defaults loading method, controls DSP that in the scene using multi-DSP, FPGA is also needed
The chip number of each DSP is provided, program development is used for.This system carries out multi-core DSP using single documentation of program to realize
Efficient Development, need the private room to core each in DDR to remap.
It elaborates, comprises the following steps to multi-core DSP program development adjustment method below:
The first step carries out chip number to each dsp chip by fpga chip, and the core for obtaining each DSP core inside dsp chip is compiled
Number.When developing DSP program file using single documentation of program, need to pass through the program integration of each core in a documentation of program
DSP core number and dsp chip number divide respective processing function.This system DSP uses CCS5.5 (Code Composer
Studio5.5) software is developed based on SYS/BIOS operating system, is specifically included:
1) the number g_myCoreID of current DSP core is obtained by CSL_chipReadReg () function, function return value is
0~7, respectively represent 0~core of core 7.
2) each dsp chip is numbered according to pin state by FPGA, each DSP is sent to by data/address bus,
DSP obtains itself number g_myDevId.
Second step divides physical address of the DSP core in DDR according to the logical address of DSP core private room in DDR,
By DSP core each in same dsp chip, the logical address of private room is changed to same logical address in DDR again, establishes logically
The mapping relations of location and physical address.TMS320C6678 uses extended address controller (Extended Memory
Controller, hereinafter referred to as XMC) in address protection and extension (Memory Protection and Address
EXtension, hereinafter referred to as MPAX) unit carries out memory space protection and address extension, the logical address of 32bit can be reflected
The physical address for 36bit is penetrated, the addressing range of DSP is expanded.For this system, deposited between different dsp chips
Space access conflict is stored up, therefore the MPAX of XMC needs the space DDR accessed when each core of dsp chip is executed same operation to patrol
Address is collected, is mapped as in the space DDR, the different privately owned physical address of each DSP core.Matching with the MPAX of a dsp chip below
The process of setting is illustrated, and the logical address and physical address of the other three dsp chip configuration are identical as this dsp chip, ginseng
As shown in Figure 3, steps are as follows:
1) confirm and divide logical address space of each DSP core in DDR chip.This system is distributed to each core of DSP
The privately owned memory headroom of 16MB, since DDR initial address 0x80000000, the logical address space of each core actual division are as follows:
(1) core 0:0x80000000~0x80FFFFFF；
(2) core 1:0x81000000~0x81FFFFFF；
(3) core 2:0x82000000~0x82FFFFFF；
(4) core 3:0x83000000~0x83FFFFFF；
(5) core 4:0x84000000~0x84FFFFFF；
(6) core 5:0x85000000~0x85FFFFFF；
(7) core 6:0x86000000~0x86FFFFFF；
(8) core 7:0x87000000~0x87FFFFFF.
2) according to the logical address space of each core actual division, confirm and divide each DSP core in DDR physically
Location.By consulting TI official manual, available DDR logical address space is 0x80000000~0xFFFFFFFF, corresponding
Physical address space is 0x800000000~0x87FFFFFFF, size 2GB.It, can according to the logical address that previous step divides
Corresponding physical address space is defaulted to obtain each core are as follows:
(1) core 0:0x800000000~0x800FFFFFF；
(2) core 1:0x801000000~0x801FFFFFF；
(3) core 2:0x802000000~0x802FFFFFF；
(4) core 3:0x803000000~0x803FFFFFF；
(5) core 4:0x804000000~0x804FFFFFF；
(6) core 5:0x805000000~0x805FFFFFF；
(7) core 6:0x806000000~0x806FFFFFF；
(8) core 7:0x807000000~0x807FFFFFF.
3) according to the use demand of real system, (i.e. multiple cores can be empty in the identical logical address of code level operations
Between, and hardware instruction is mapped to different physical address spaces in system operation), 1) and 2) it needs on the basis of, keeps
Each actual physical address space of core is constant, and changes actual logical address space.In this system, by the logical address of each core
Space is changed are as follows: 0x80000000~0x8FFFFFFF.
4) the MPAX register for configuring XMC carries out each DSP core address of cache.This system is needed by DDR start logical
Location 0x80000000 is mapped as the start physical address of each core private room.The MPAX register of XMC is divided into MPAXH and MPAXL
Two parts, each section explanation are as shown in Figure 4.In MPAXH, BADDR is the high 20bit of logical address, i.e. 0x80000, RSV are to retain
Position, filling out 0, SEGSZ is allocation space size, i.e. 16MB, corresponding control word is 0x17.Therefore, each core MPAXH is configured to
0x80000017.In MPAXL, RADDR is that the physical address high 24bit, PERM of mapping are address access permission information, is made here
All permission flag positions of energy, are configured to 0x3f.The MPAX register of each core configures in order are as follows:
(1) core 0:MPAXH is 0x80000017, MPAXL 0x8000003f；
(2) core 1:MPAXH is 0x80000017, MPAXL 0x8010003f；
(3) core 2:MPAXH is 0x80000017, MPAXL 0x8020003f；
(4) core 3:MPAXH is 0x80000017, MPAXL 0x8030003f；
(5) core 4:MPAXH is 0x80000017, MPAXL 0x8040003f；
(6) core 5:MPAXH is 0x80000017, MPAXL 0x8050003f；
(7) core 6:MPAXH is 0x80000017, MPAXL 0x8060003f；
(8) core 7:MPAXH is 0x80000017, MPAXL 0x8070003f.
Third step writes multi-core DSP documentation of program, in multi-core DSP documentation of program by chip number g_myCoreID,
G_myDevId core number divides the logical address of the kernel function and kernel function of each DSP core in DDR private room.
Multi-core DSP program file is produced by above three step, is next exactly to be loaded into multi-core DSP program file
On DSP.With reference to the mode that TI handbook provides, each DSP core is loaded using identical image file.Complete MPAX configuration
Afterwards, multi-core program can be solidificated in progress local boot load in FLASH, FPGA can also be passed through upon power-up of the system by journey
DDR is written in preface part, carries out distal end load from DDR.In view of avionics system is according to functional requirement, need do not powering off feelings
Switch the function that DSP is executed under condition, dynamically load unloading is realized to DSP program, therefore this system is loaded by using distal end
Mode, detailed process are as shown in Figure 5:
It 1) is external memory interface (External by the default Starting mode that dsp chip is arranged in fpga chip
Memory Interface, hereinafter referred to as EMIF) starting.
2) after DSP electrification reset, operation TI official is solidificated in the on piece that on piece ROM is located at address 0x20b00000 first
Loader (RBL) program, the level-one for carrying out DSP are booted up, (are controlled by FPGA, at this time hardware according to DSP hardware pin status
State is the EMIF starting of default), judgement currently carries out second level from EMIF to FLASH and is booted up, second level bootloader is run,
It will indicate present procedure operating statusProgrammed counting (Program Counter, hereinafter referred to as PC) pointerIt is directed toward rising for FLASH
Beginning address 0x70000000.Dsp chip starting, the initial address for the FLASH being directed toward according to external memory interface is from FLASH bis-
After secondary start completion hardware initialization, the default Starting mode of dsp chip is changed to start by DDR chip, and gives FPGA
Chip sends reset instruction.
3) shown in Figure 2 after fpga chip receives reset instruction, by each DSP core function in multi-core DSP documentation of program
It is sent the program segment of the DSP core function in corresponding DDR memory according to the chip number of DSP core function and logical address,
And reset dsp chip.
4) DSP is restarted from DDR after the reset, has been changed to start from DDR due to being currently up mode, level-one
Bootstrap can execute new second level bootloader, and second level bootloader is instructed by memory copying, by the multicore in DDR memory
Program code is moved on the physical address of the private room of the main core of DSP (core 0).Main core first carries out in code according to core number to be belonged to
In the program segment of main core, the object being respectively individually copied to from the program segment of core (core 1 to core 7) from the private room of core then will be belonged to
It manages on address, and sends interrupt message to from core, prompt to execute respective program from core, so far multi-core program load is completed.
Invention is suitable for large complicated multi-nuclear DSP system and develops, and by the address extension management function of DSP, patrols same
Collecting address of cache is the different physical address of addressing space, when solving multicore while operation function, to a piece of shared storage
The access conflict problem in space realizes multi-core DSP program writing, debug and loading under single documentation of program, mentions significantly
High complication system development efficiency.It is understood that for those of ordinary skills, it can be with technology according to the present invention
Scheme and its inventive concept are subject to equivalent substitution or change, and all these changes or replacement all should belong to power appended by the present invention
The protection scope that benefit requires.
Claims (5)
1. a kind of multi-core DSP program development adjustment method, the multi-core DSP program is applied to multi-nuclear DSP system, multi-core DSP system
System includes more than one multi-core DSP chip, DDR chip and a fpga chip, is matched for more than one multi-core DSP chip
A fpga chip is set, is that every multi-core DSP chip configures a DDR chip, multi-core DSP program development adjustment method step is such as
Under:
The first step carries out chip number to each dsp chip by fpga chip, obtains the core number of each DSP core inside dsp chip；
Second step divides physical address of the DSP core in DDR according to the logical address of DSP core private room in DDR, then will
Each DSP core logical address of private room in DDR is changed to same logical address in same dsp chip, establish logical address with
The mapping relations of physical address；
Third step writes multi-core DSP documentation of program, is divided respectively in multi-core DSP documentation of program by chip number, core number
Logical address of the kernel function and kernel function of DSP core in DDR private room.
2. a kind of multi-core DSP program development adjustment method according to claim 1, it is characterised in that in the first step, by
Fpga chip carries out chip number to each dsp chip according to pin state, and chip number is sent to each by data/address bus
Dsp chip, dsp chip obtain itself chip number.
3. a kind of multi-core DSP program development adjustment method according to claim 1, it is characterised in that the second step includes such as
Lower step:
1) confirm and divide the logical address of each DSP core private room in DDR chip；
2) logical address divided according to each DSP core, confirms and divides physical address of each DSP core in DDR chip；
3) keep each DSP core physical address constant, by the logical address of DSP core private room in DDR each in same dsp chip
It is changed to same logical address；
4) the MPAX register of configuration XMC carries out the mapping of the logical address and physical address of each DSP core.
4. a kind of multi-core DSP documentation of program, it is characterised in that opened by a kind of any multi-core DSP program of claim 1-3
Adjustment method is sent out to generate.
5. a kind of loading method for loading multi-core DSP documentation of program as claimed in claim 4, comprising including as follows:
1) the default Starting mode of dsp chip is set by fpga chip for external memory interface starting；
2) dsp chip starts, and the initial address for the FLASH being directed toward according to external memory interface is completed from FLASH restarting
After hardware initialization, the default Starting mode of dsp chip is changed to start by DDR chip, and is sent again to fpga chip
Bit instruction；
3) after fpga chip receives reset instruction, by each DSP core function in multi-core DSP documentation of program according to DSP core function
Chip number and logical address send the program segment of the DSP core function in corresponding DDR memory, and reset dsp chip；
4) DSP is restarted from DDR after the reset, and the program segment of each DSP core in DDR memory is moved the main core of DSP in DDR
Private room physical address on, main core is first carried out according to core number belongs to the program segment of main core in program segment, then will belong to
In being respectively individually copied to the physical address from the private room of core from the program segment of core, and interrupt message is sent to from core, prompted
Respective program is executed from core, so far multi-core program document load is completed.
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| CN117215664A (en) * | 2023-08-21 | 2023-12-12 | 白盒子(上海)微电子科技有限公司 | Quick starting method for multi-core DSP of system on chip |
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