CN111666104A - DSP processor design method supporting starting from RapidO - Google Patents
DSP processor design method supporting starting from RapidO Download PDFInfo
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- CN111666104A CN111666104A CN202010531125.2A CN202010531125A CN111666104A CN 111666104 A CN111666104 A CN 111666104A CN 202010531125 A CN202010531125 A CN 202010531125A CN 111666104 A CN111666104 A CN 111666104A
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- 238000013461 design Methods 0.000 title claims abstract description 22
- 238000013507 mapping Methods 0.000 claims description 9
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- 239000004744 fabric Substances 0.000 claims description 3
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- 238000012545 processing Methods 0.000 abstract description 8
- 238000011161 development Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
Abstract
The invention discloses a design method of a DSP (digital signal processor) supporting slave RapidO starting, which comprises the steps of setting a DSP main processor and a DSP slave processor, configuring starting modes of the DSP main processor and the DSP slave processor, and setting Boot _ sel configuration options of the DSP main processor and the DSP slave processor. Compared with a DSP processor boot mode only supporting boot from an EMIF single interface, the boot mode from a RapidIO interface is added. In the system design of a multi-chip master-slave DSP processor, the using amount of a nonvolatile memory is reduced by more than half. The DSP loads programs from the memory of the remote shared main processor, so that the board level design of the system can be simplified, the density and the design difficulty of system design components are reduced, and the development cost of a system processing board card is reduced.
Description
Technical Field
The invention relates to the technical field, in particular to a DSP processor design method supporting starting from RapidO.
Background
Home and abroad DSP processors are usually booted from an External Memory Interface (EMIF), and the start and the operation of the processors are realized by externally hanging a Norflash loading program and data through the interface. To simplify chip design and verification complexity, DSP processors typically support only this single boot mode. On the board card carrying a plurality of DSP processors on board, each DSP processor needs to be independently hung with Norflash, the density of system design components and board card design difficulty is increased, and the development cost of the system processing board card is increased.
The External Memory Interface (EMIF) is a special interface used by the DSP processor for loading programs and data, and the booting and starting of the DSP processor can be realized through the Norflash hung outside the interface. Due to the adoption of the parallel port transmission interface, the data reading rate of the Norflash can usually reach several MB/s, which is higher than the access rate of other low-speed interfaces such as SPI or LPC. On the board card of an onboard single-chip or double-chip DSP processor, the density of components of the processing board card is generally low, the layout and wiring space of the board card is large, even if each DSP independently hooks the Norflash to start from local boot, the problem is not great, and the design of the DSP processor, the design of the system board card and the software development are facilitated.
However, in the application of the actual embedded high-performance electronic information device, in order to improve the processing performance of the signal processing board card, the board card is generally formed by four or more DSP processors interconnected in a ring or through a switching chip, and the board card is additionally provided with necessary peripheral components such as on-board DC-DC, FPGA, DDR and the like, so that the density of the components of the processing board card is extremely high. If each DSP is started from local boot by local connection of the Norflash, great challenges are brought to the layout and wiring design of the processing board card.
Disclosure of Invention
The present invention is directed to a design method of a DSP processor supporting booting from RapidO, so as to solve the problems mentioned in the above background art.
In order to achieve the purpose, the invention provides the following technical scheme:
the first step, set up DSP treater, DSP treater includes: and the DSP main processor and the DSP slave processor configure the starting modes of the DSP main processor and the DSP slave processor.
And secondly, setting Boot _ sel configuration options of the DSP main processor and the DSP auxiliary processor.
Thirdly, after the board card is powered on and reset, the DSP main processor is started from the EMIF interface first; after a board-level RapidIO link is established, the DSP slave processor is started from RapidIO through Norflash sharing an EMIF interface of the DSP master processor, and then Host configures a RapidIO start (RapidIO _ Boot _ Ready) register in an EP register space so as to release a reset signal of the DSP slave processor.
Preferably, the operation of the first step specifically comprises the following steps: configuring a DSP main processor into an EMIF interface starting mode, and setting a RapidIO interface thereof as a Host port; and configuring the DSP slave processor into a RapidIO starting mode, and setting the DSP slave processor into an EP port supporting an Inbound NREAD read request. By setting RPIO AMAP mapping of the DSP slave processor, after an EP end sends an NREAD request, a RapidIO controller in the DSP master processor maps the request into an AXI request of an Norflash address space of an EMIF interface.
Preferably, the operation of the second step comprises the following specific steps: allocating address spaces for the DSP main processor and the DSP slave processor, remapping 0 addresses to the addresses of the DSP main processor and the DSP slave processor according to the value of a Boot _ sel control signal, and allocating a section of address space starting from 0x1000_0000 to the EMIF interface when the DSP main processor and the DSP slave processor are both DSP processors which simultaneously support the starting of the EMIF interface and the RapidIO interface; a fragment of address space starting at 0x1a80_0000 is allocated to the RapidIO interface.
Preferably, when the DSP processor is configured to boot from the EMIF interface, then 0 addresses are remapped to 0x1000 — 0000, and when the DSP processor is configured to boot from the RapidIO interface, then 0 addresses are remapped to 0x1a80 — 0000.
Preferably, during the process of starting the DSP processor, the multiplexing EMIF interface data pin is used as a boot starting mode.
Preferably, the third operation comprises the following specific steps: the DSP finishes resetting after receiving a RapidIO _ Boot _ Ready signal from the processor, and takes a first instruction from the address of 0x0000_0000, but in the RapidIO starting mode, the address of 0 is remapped to the address of 0x1a80_0000 and is routed to Host. The DSP slave processor sends an AXI request through the RapidIO, because the AXI AMAP of the DSP slave processor is set at the moment, the RapidIO controller maps the AXI AMAP into an NREAD request to be sent to the Host, and the DSP slave processor is guided and started by the EMIF loader of the DSP master processor.
Preferably, in the DSP processor, the RapidIO and EMIF interfaces are interconnected by an on-chip bus, and the starting and initializing of the RapidIO structure includes: the method comprises the steps of system initialization, device enumeration, routing table configuration and memory mapping, and an EMIF interface is mapped to a RapidIO access space through the memory mapping. Once configured, RapidIO may pass I/O transactions transparently in the RapidIO interconnect fabric.
Preferably, there are two interconnection modes, point-to-point and switch bridge, between the DSP main processor and the RapidIO of the DSP slave processor.
Preferably, when a plurality of DSP slave processors are arranged, the RapidIO of each DSP slave processor is configured after the DSP master processor is started, and the DSP slave processors finish booting in a rotating mode according to the sequence of configuration.
Compared with the prior art, the invention has the beneficial effects that: a design method of a DSP processor supporting starting from a RapidO interface is added with a boot starting mode from the RapidO interface compared with a boot mode of the DSP processor only supporting starting from an EMIF single interface. In the system design of a multi-chip master-slave DSP processor, the using amount of a nonvolatile memory is reduced by more than half. The DSP loads programs from the memory of the remote shared main processor, so that the board level design of the system can be simplified, the density and the design difficulty of system design components are reduced, and the development cost of a system processing board card is reduced.
The design is based on the existing data transmission channel of Rapidlo to carry out function expansion, and DSP is directly converted from AXI access of a processor core into NREAD access of Host; the configuration pins are designed in a pin multiplexing mode; the remapping mechanism of the 0 address space and the boot starting address is simple; the hardware logic resource overhead of the whole realization is small.
Compared with a method for realizing master-slave multiprocessor boot through a PCI or other interfaces, the transmission rate of the RapidlO is higher by one order of magnitude, boot startup is carried out through the RapidlO, and the program loading time is shorter.
Drawings
FIG. 1 is a boot flow diagram of the present invention.
FIG. 2 is a BOOT mode selection diagram according to the present invention.
Fig. 3 is a block diagram of the RapidIO and EMIF interface interconnect structure in the present invention.
FIG. 4 is a block diagram of a RapidIO point-to-point interconnect for DSP processors in accordance with the present invention.
FIG. 5 is a schematic diagram of the RapidIO bridge interconnection of the DSP processors in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, the present invention provides a technical solution: the first step, set up DSP treater, DSP treater includes: and the DSP main processor and the DSP slave processor configure the starting modes of the DSP main processor and the DSP slave processor.
And secondly, setting Boot _ sel configuration options of the DSP main processor and the DSP auxiliary processor.
Thirdly, after the board card is powered on and reset, the DSP main processor is started from the EMIF interface first; after a board-level RapidIO link is established, the DSP slave processor is started from RapidIO through Norflash sharing an EMIF interface of the DSP master processor, and then Host configures a RapidIO start (RapidIO _ Boot _ Ready) register in an EP register space so as to release a reset signal of the DSP slave processor.
The first operation comprises the following specific steps: two interconnection modes, namely point-to-point interconnection and bridge chip exchange interconnection, are usually adopted between the DSP main processor and the RapidIO of the DSP slave processor, and in any interconnection mode, the DSP main processor is configured to be in an EMIF interface starting mode, and the DSP slave processor is configured to be in a RapidIO starting mode; the RapidIO interface of the DSP main processor is configured as Host, and the slave processor is configured as Endpoint. In the interconnection mode through the switching bridge chip, the port of the RapiaIO bridge chip and the port of the DSP slave processor are configured as Host, and the port of the RapiaIO bridge chip and the port of the DSP master processor are configured as Endpoint. After the board card is powered on and reset, the DSP main processor is started from the EMIF interface first; after a board-level RapidIO link is established, the DSP slave processor is started from RapidIO through Norflash sharing an EMIF interface of the DSP master processor, the DSP master processor is configured into an EMIF interface starting mode, and the RapidIO interface is set as a Host port; and configuring the DSP slave processor into a RapidIO starting mode, and setting the DSP slave processor into an EP port supporting an Inbound NREAD read request. Through setting RPIO AMAP mapping of the DSP slave processors, after an EP end sends an NREAD request, a RapidIO controller in the DSP master processor maps the request into an AXI request of an Norflash address space of an EMIF interface, when the DSP slave processors are provided with a plurality of, the RapidIO of each DSP slave processor is configured after the DSP master processor is started, the DSP slave processors finish boot starting in a rotating mode according to the sequence of configuration, the specific flow chart is shown in figure 1, DSP _0 is the master processor started from the EMIF, and DSP _1 is the slave processor started from the RapidIO.
The operation of the second step comprises the following specific steps: allocating address spaces for the DSP main processor and the DSP slave processor, remapping 0 addresses to the addresses of the DSP main processor and the DSP slave processor by adopting a multiplexing EMIF interface data pin as a Boot starting mode in the starting process of the DSP processor according to the value of a Boot _ sel control signal, and allocating a section of address space starting from 0x1000_0000 to the EMIF interface when the DSP main processor and the DSP slave processor are both DSP processors simultaneously supporting the starting of the EMIF interface and the RapidIO interface; a fragment of address space starting at 0x1a80_0000 is allocated to the RapidIO interface.
When the DSP processor is configured to boot from the EMIF interface, then 0 addresses are remapped to 0x1000 — 0000, and when the DSP processor is configured to boot from the RapidIO interface, then 0 addresses are remapped to 0x1a80 — 0000.
The third operation comprises the following specific steps: the DSP finishes resetting after receiving a RapidIO _ Boot _ Ready signal from the processor, and takes a first instruction from the address of 0x0000_0000, but in the RapidIO starting mode, the address of 0 is remapped to the address of 0x1a80_0000 and is routed to Host. The DSP slave processor sends an AXI request through the RapidIO, because the AXI AMAP of the DSP slave processor is set at the moment, the RapidIO controller maps the AXI AMAP into an NREAD request to be sent to the Host, and the DSP slave processor is guided and started by the EMIF loader of the DSP master processor.
In a DSP processor, RapidIO and an EMIF interface are interconnected through an on-chip bus, and the starting and initialization of a RapidIO structure comprises the following steps: the method comprises the steps of system initialization, device enumeration, routing table configuration and memory mapping, and an EMIF interface is mapped to a RapidIO access space through the memory mapping. Once configured, RapidIO may pass I/O transactions transparently in the RapidIO interconnect fabric.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. A DSP processor design method supporting starting from RapidO is characterized by comprising the following technical process characteristics:
the first step, set up DSP treater, DSP treater includes: and the DSP main processor and the DSP slave processor configure the starting modes of the DSP main processor and the DSP slave processor.
And secondly, setting Boot _ sel configuration options of the DSP main processor and the DSP auxiliary processor.
Thirdly, after the board card is powered on and reset, the DSP main processor is started from the EMIF interface first; after a board-level RapidIO link is established, the DSP slave processor is started from RapidIO through Norflash sharing an EMIF interface of the DSP master processor, and then Host configures a RapidIO start (RapidIO _ Boot _ Ready) register in an EP register space so as to release a reset signal of the DSP slave processor.
2. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: the first operation comprises the following specific steps: configuring a DSP main processor into an EMIF interface starting mode, and setting a RapidIO interface thereof as a Host port; and configuring the DSP slave processor into a RapidIO starting mode, and setting the DSP slave processor into an EP port supporting an InboundREAD reading request. By setting RPIO AMAP mapping of the DSP slave processor, after an EP end sends an NREAD request, a RapidIO controller in the DSP master processor maps the request into an AXI request of an Norflash address space of an EMIF interface.
3. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: the operation of the second step comprises the following specific steps: allocating address spaces for the DSP main processor and the DSP slave processor, remapping 0 addresses to the addresses of the DSP main processor and the DSP slave processor according to the value of a Boot _ sel control signal, and allocating a section of address space starting from 0x1000_0000 to the EMIF interface when the DSP main processor and the DSP slave processor are both DSP processors which simultaneously support the starting of the EMIF interface and the RapidIO interface; a fragment of address space starting at 0x1a80_0000 is allocated to the RapidIO interface.
4. A method of designing a DSP processor that supports boot-up from RapidO according to claim 3, wherein: when the DSP processor is configured to boot from the EMIF interface, then 0 addresses are remapped to 0x1000 — 0000, and when the DSP processor is configured to boot from the RapidIO interface, then 0 addresses are remapped to 0x1a80 — 0000.
5. A method of designing a DSP processor that supports boot-up from RapidO according to claim 3, wherein: in the process of starting the DSP processor, the multiplexing EMIF interface data pin is used as a boot starting mode.
6. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: the third operation comprises the following specific steps: the DSP finishes resetting after receiving a RapidIO _ Boot _ Ready signal from the processor, and takes a first instruction from the address of 0x0000_0000, but in the RapidIO starting mode, the address of 0 is remapped to the address of 0x1a80_0000 and is routed to Host. The DSP slave processor sends an AXI request through the RapidIO, because the AXIAMAP of the DSP slave processor is set at the moment, the RapidIO controller maps the AXIAMAP into an NREAD request to be sent to the Host, and the DSP slave processor is guided and started by the EMIF loader of the DSP master processor.
7. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: in a DSP processor, RapidIO and an EMIF interface are interconnected through an on-chip bus, and the starting and initialization of a RapidIO structure comprises the following steps: the method comprises the steps of system initialization, device enumeration, routing table configuration and memory mapping, and an EMIF interface is mapped to a RapidIO access space through the memory mapping. Once configured, RapidIO may pass I/O transactions transparently in the RapidIO interconnect fabric.
8. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: there are typically two types of interconnections between RapidIO of the DSP host processor and the DSP slave processor, point-to-point and through switch bridges.
9. A method of designing a DSP processor that supports boot-up from RapidO according to claim 1, wherein: when the number of the DSP slave processors is multiple, the RapidIO of each DSP slave processor is configured after the DSP master processor is started, and the DSP slave processors finish boot starting in a rotating mode according to the sequence of configuration.
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