CN102646045A - Multiprocessor system and parallel startup method thereof - Google Patents
Multiprocessor system and parallel startup method thereof Download PDFInfo
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Abstract
The invention relates to a multiprocessor computer system, and discloses a multiprocessor system and a parallel startup method thereof. The parallel startup of a main processor and an auxiliary processor is realized, the startup loading speed of a multiprocessor is accelerated, and the user waiting time is reduced. The multiprocessor system comprises at least two processors which are connected with each other through a bus, wherein one is the main processor and the other one is the auxiliary processor. The method comprises the following steps of: starting a main bootstrap program by the main processor, and enumerating the auxiliary processor on the bus; loading a startup file for the auxiliary processor by the main bootstrap program, and then starting the auxiliary processor; and while the auxiliary processor is started, loading a mirror image document of an operating system kernel of the main processor and starting the main processor.
Description
Technical field
The present invention relates to multiprocessor computer system, particularly a kind of multicomputer system start-up technique.
Background technology
Based on interconnected (the Peripheral Component Interconnect of peripheral components; Be called for short " PCI ") interconnected (the Peripheral Component Interconnect Express of bus/peripheral components high speed; Abbreviation " PCI-E ") in the multicomputer system start-up course of bus, the method for generally taking at present is, after primary processor starts completion; Download each successively through the PCI/PCI-E bus and start required binary file to its internal memory from processor, completion starts from processor.Mostly improving one's methods of seeing now is to download the file into from this angle of processor memory from shortening starts with, such as:
1) multithreading is downloaded each binary file from processor;
2) primary processor starts group leader's processor of every group earlier dividing into groups from processor, starts the processor of respectively organizing other more respectively by group leader's processor then;
3) primary processor is accomplished each download from processor group binary file dividing into groups from processor through the multicast function of PCI-E interchanger (or PCI-E Switch);
Inventor of the present invention finds; Said method all is after primary processor is downloaded completion; Set about initialization again from processor; Therefore primary processor and be that serial starts from processor, total system will be primary processor start-up times, download from the processor binary file time with from processor three's start-up time sum start-up time.
How to let each processor accomplish initialization as early as possible, most important for the startup of accelerating multicomputer system.
Summary of the invention
The object of the present invention is to provide a kind of multicomputer system and parallel starting method thereof, realized primary processor and started parallelization, accelerated multicomputer system start-up loading speed, reduced period of reservation of number from processor.
For solving the problems of the technologies described above, embodiment of the present invention discloses a kind of multicomputer system parallel starting method, and multicomputer system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor;
Processor system parallel starting method may further comprise the steps:
Primary processor starts main bootstrap program, and enumerate on the bus from processor;
Main bootstrap program is after loading startup file from processor, to start from processor;
Starting in processor, primary processor loads the operating system nucleus image file of self and starts.
Embodiment of the present invention also discloses a kind of multicomputer system, and system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor;
Primary processor; Be used at first starting main bootstrap program, and enumerate on the bus secondly from processor; After main bootstrap program is to load startup file from processor; Startup is starting in processor from processor at last, and primary processor loads the operating system nucleus image file of self and starts.
Embodiment of the present invention compared with prior art, the key distinction and effect thereof are:
Primary processor is when also starting from processor from processor loading startup file through main bootstrap program; Load self operating system nucleus image file and startup; Realized primary processor and started parallelization from processor; Accelerate multicomputer system startup file loading velocity, reduced period of reservation of number.
Further, through according to slot number from processor place, for this from the corresponding PCI-E of processor distribution address to accomplish initialization procedure from processor, can guarantee the regularity of bus address space, be convenient to revise bus address space.
Further; According to the classification from processor, the startup file that need load when confirm starting is then according to the classification of startup file; To sort out grouping from processor; When main bootstrap program loads startup file, can load in batches like this, improve the loading timeliness, be convenient to the expansion of multicomputer system structure simultaneously.
Further; Main bootstrap program is earlier to load from boot from processor; Start from processor self in boot, main bootstrap program reloads this operating system nucleus image file and file system from processor, make main bootstrap program to load from the operating system nucleus image file of processor and file system with from processor self from boot startup executed in parallel; Further reduce the system start-up time, reduced period of reservation of number.
Description of drawings
Fig. 1 is the schematic flow sheet of a kind of multicomputer system parallel starting method in the first embodiment of the invention;
Fig. 2 is the schematic flow sheet of a kind of multicomputer system parallel starting method in the second embodiment of the invention;
Fig. 3 is that the operating system nucleus image file of a kind of multicomputer system in the second embodiment of the invention is downloaded synoptic diagram;
Fig. 4 is that a kind of parallel and serial of multicomputer system starts the contrast synoptic diagram in the second embodiment of the invention;
Fig. 5 is the structural representation of a kind of multicomputer system in the third embodiment of the invention.
Embodiment
In following narration, many ins and outs have been proposed in order to make the reader understand the application better.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on the many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that embodiment of the present invention is done to describe in detail further below.
First embodiment of the invention relates to a kind of multicomputer system parallel starting method.Fig. 1 is the schematic flow sheet of this multicomputer system parallel starting method.This multicomputer system parallel starting method system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor.
Specifically, as shown in Figure 1, multicomputer system parallel starting method may further comprise the steps:
In step 101, primary processor starts main bootstrap program.
After this get into step 102, primary processor enumerate on the bus from processor.
After this get into step 103, main bootstrap program is to load startup file from processor.
After this get into step 104, start from processor.
After this get into step 105, starting in processor, primary processor loads the operating system nucleus image file of self and starts, after this process ends.
Above-mentioned steps 104 and 105 is carried out simultaneously, and the difference because of step number does not cause carrying out difference successively.
In addition, above-mentioned processor is central processing unit (Central Processing Unit, be called for short " CPU "), a kind of in the processor types such as digital signal processor (Digital Signal Processor is called for short " DSP ") and single-chip microcomputer or some kinds.
Second embodiment of the invention relates to a kind of multicomputer system parallel starting method.Fig. 2 is the schematic flow sheet of this multicomputer system parallel starting method.
Second embodiment improves on the basis of first embodiment; Main improvements are: belong to slot number through basis from processor; For this from the corresponding PCI-E of processor distribution address to accomplish initialization procedure from processor; Can guarantee the regularity of bus address space, be convenient to revise bus address space.According to the classification from processor, the startup file that need load when confirm starting is then according to the classification of startup file; To sort out grouping from processor; When main bootstrap program loads startup file, can load in batches like this, improve the loading timeliness, be convenient to the expansion of multicomputer system structure simultaneously.Main bootstrap program is earlier to load from boot from processor; Start from processor self in boot; Main bootstrap program reloads this operating system nucleus image file and file system from processor; Make main bootstrap program to load from the operating system nucleus image file of processor and file system with from processor self start executed in parallel from boot, further reduced the system start-up time, reduced period of reservation of number.
Specifically:
Bus is the PCI-E bus.
Enumerate on the bus from the processor step, also comprise following substep:
According to slot number from processor place, for this from the corresponding PCI-E of processor distribution address, with the bus address space of initialization system.
In addition; In some other embodiments of the present invention; Bus also can be in the buses such as industrial standard (Industry Standard Architecture, be called for short " ISA ") bus, peripheral components interconnected (Peripheral Component Interconnect is called for short " PCI ") bus a kind of; Be not limited to peripheral components high speed interconnected (Peripheral Component Interconnect Express is called for short " PCI-E ") bus.
Enumerate the step on the bus, also comprise following substep from processor:
Visit the functional processor information that each is preserved from the configuration space of processor according to the order of sequence successively, this functional processor information comprises EIC equipment identification code (or being called device id) and manufacturer ID (or being called vendor id).
Whether the pairing processor of functional processor information that the detection configuration space is preserved is legal.
As if legal, then carry out the step of the bus address space of initialization system.
In addition, each comprises EIC equipment identification code and manufacturer ID from functional processor information, by (Bus number bus_num; Device number device_num, function function_num) unique definite, 0＜=device_num＜32; 0＜=function_num＜8; Wherein (0,0,0) is the main bridge device of primary processor end.
Further comprising the steps of:
According to the startup file classification of required loading when processor starts, will sort out grouping from processor in advance;
At main bootstrap program is to load from processor the step of startup file, and main bootstrap program is according to the classification from processor, for loading startup file in batches from processor in affiliated group.
Startup file comprise compression from boot, operating system nucleus image file and file system.
Main bootstrap program is after loading startup file from processor, to start the step from processor, also comprises following substep:
Main bootstrap program is to load from boot from processor.
From processor start self from the boot initiating hardware.
Start from processor self in the boot initiating hardware, main bootstrap program loads the operating system nucleus image file and the file system of this processor.
Treat that operating system nucleus image file and file system load completion, the main bootstrap program setting is from the internal memory zone bit of processor.
After being set up from the internal memory zone bit that is polled to self from boot of processor, start the file system of self operating system nucleus image file and carry self.
As a preferred implementation of the present invention, as shown in Figure 2, multicomputer system parallel starting method may further comprise the steps:
Above-mentioned main bootstrap program is after loading startup file from processor, to start the step 104 from processor, also comprises following substep:
In step 201, for multicomputer system powers on.
After this get into step 202, primary processor starts main bootstrap program.
After this get into step 203, main bootstrap program is to load from boot from processor.
After this get into step 204, from processor start self from the boot initiating hardware, start from processor self in the boot initiating hardware, main bootstrap program loads the operating system nucleus image file and the file system of this processor.
After this get into step 205, treat that operating system nucleus image file and file system load to be accomplished after, the main bootstrap program setting is from the internal memory zone bit of processor.
After this get into step 206, whether effective from the internal memory zone bit from boot poll self of processor.
If effectively, then get into step 207; Otherwise return step 206, continue poll and detect.
In step 207, after being set up from the internal memory zone bit that is polled to self from boot of processor, start the operating system nucleus image file of self from processor.
After this get into step 208, from the file system of processor carry self, after this process ends.
Carrying out above-mentioned steps 206 in 208, also carry out following steps 209 and 210.
In step 209, primary processor starts the operating system nucleus image file of self.
After this get into step 210, the file system of primary processor carry self, after this process ends.
As a preferred implementation of the present invention, Fig. 3 is that a kind of operating system nucleus image file of multicomputer system is downloaded synoptic diagram.After host CPU powers on; Start main bootstrap program BootLoader; Wherein can enumerate PCI-E equipment; Form the PCI-E device tree, and according to the suitable PCI-E address of BAR (or being called base address register) space size configure of PCI-E equipment, the address of acquiescence is in the interval PCI-E of distribution of fixed address address according to the order of enumerating.In actual the use, often hope this address space to be revised according to characteristic and actual demand from CPU.For example, can distribute corresponding PCI-E address, like this can guarantee the regularity of address according to slot number from the CPU place.The internal memory of the BAR1 mapping 256MB of certain PCI-E equipment, the actual space of several MB that only needs is used to download the required binary file of this device start.
The configuration space of PCI-E equipment (or processor) has been preserved the essential information of these functions of the equipments, and the work of enumerating of host CPU all is to carry out through visiting each configuration space from CPU successively.Specifically, in the PCI-E system, each PCI-E functions of the equipments can be passed through Bus number, and device number and function are number well-determined, i.e. (bus_num, device_num, function_num) unique function of confirming a PCI-E equipment.A PCI-E system can have 256 buses (bus_num＜=256) at most, and every bus at most can 32 equipment of carry (device_num＜=32), and an equipment has 8 functions (function_num＜=8) at most.When enumerating beginning; Always since No. 0 bus; Attempt reading each device number and function number combination on this bus successively,, will further accomplish the setting of BAR address if read significant register value in the configuration space; In addition, for the uplink and downlink port of PCI-E interchanger (or Switch) simple Bus number, secondary bus number and subordinate's Bus number to be set also.But enumeration process should be got rid of the main bridge device (0,0,0) that connects host CPU.
As shown in Figure 3, be divided into some groups according to the startup file classification from CPU: from CPU0, from CPU m, wherein m is a positive integer from CPU1......, and every group identical from the CPU startup file.Host CPU at first reads different memory headrooms to all startup files from the CPU group, and this memory headroom can be by other PCI-E device accesses as BAR (or being called base address register) space of host CPU.
Scanning PCI-E device tree according to each device id and vendor id from the CPU group, therefrom finds this group from CPU member, and from the host CPU memory headroom of correspondence, reads the scale-of-two startup file to from the CPU internal memory, realizes the startup from CPU.Then, all are carried out this process from the CPU group, all start completion up to all CPU.
In general, the startup file from CPU comprises from boot BootLoader operating system nucleus image file ulmage and file system ramdisk.After all startup files are downloaded and are accomplished; Host CPU need be provided with from CPU internal memory zone bit; For example be written as 0x12345678 to internal memory 0x403fffc place, from the value of this address of boot BootLoader meeting poll, in case zone bit is set up; To start ulmage at memory address from CPU, and load ramdisk at last and accomplish startup from CPU.
As a preferred implementation of the present invention; Fig. 4 is that a kind of parallel and serial of multicomputer system starts the contrast synoptic diagram, specifically, can accelerate the total system toggle speed in order to prove the said startup method of this patent; Describe the multi-CPU system start-up course through Fig. 4 below; Comprise the start-up time of total system: t0 (host CPU starts main bootstrap program or BootLoader), t1 (host CPU startup kernel), t2 (host CPU is downloaded from CPU and started required binary file or startup file); T3 (starting from BootLoader and kernel) from CPU; Traditional serial start from the time of cpu mode be t0+t1+t2+t3, and parallel starting from time of CPU be t0+t2+max (t1, t3).The contrast of formula can be found out from start-up time, the time that parallel starting can be saved be min (t1, t3).
First embodiment is and the corresponding method embodiment of this embodiment, this embodiment can with the enforcement of working in coordination of first embodiment.The correlation technique details of mentioning in first embodiment is still effective in this embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in this embodiment also can be applicable in first embodiment.
Each method embodiment of the present invention all can be realized with modes such as software, hardware, firmwares.No matter the present invention be with software, hardware, or the firmware mode realize; Instruction code can be stored in the storer of computer-accessible of any kind (for example permanent or revisable; Volatibility or non-volatile; Solid-state or non-solid-state, fixing perhaps removable medium or the like).Equally; Storer can for example be programmable logic array (Programmable Array Logic; Abbreviation " PAL "), RAS (Random Access Memory; Abbreviation " RAM "), programmable read only memory (Programmable Read Only Memory is called for short " PROM "), ROM (read-only memory) (Read-Only Memory is called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM; Abbreviation " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc is called for short " DVD ") or the like.
Third embodiment of the invention relates to a kind of multicomputer system.
This multicomputer system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor.
Primary processor; Be used at first starting main bootstrap program, and enumerate on the bus secondly from processor; After main bootstrap program is to load startup file from processor; Startup is starting in processor from processor at last, and primary processor loads the operating system nucleus image file of self and starts.
Primary processor is when also starting from processor from processor loading startup file through main bootstrap program; Load self operating system nucleus image file and startup; Realized primary processor and started parallelization from processor; Accelerate multicomputer system start-up loading speed, reduced period of reservation of number.
In addition, above-mentioned processor is central processing unit (Central Processing Unit, be called for short " CPU "), a kind of in the processor types such as digital signal processor (Digital Signal Processor is called for short " DSP ") and single-chip microcomputer or some kinds.
Multicomputer system structure as shown in Figure 5 can be used as a preferred embodiment of multicomputer system structure of the present invention.
Four embodiment of the invention relates to a kind of multicomputer system.
The 4th embodiment improves on the basis of the 3rd embodiment; Main improvements are: belong to slot number through basis from processor; For this from the corresponding PCI-E of processor distribution address to accomplish initialization procedure from processor; Can guarantee the regularity of bus address space, be convenient to revise bus address space.According to the classification from processor, the startup file that need load when confirm starting is then according to the classification of startup file; To sort out grouping from processor; When main bootstrap program loads startup file, can load in batches like this, improve the loading timeliness, be convenient to the expansion of multicomputer system structure simultaneously.Main bootstrap program is earlier to load from boot from processor; Start from processor self in boot; Main bootstrap program reloads this operating system nucleus image file and file system from processor; Make main bootstrap program to load from the operating system nucleus image file of processor and file system with from processor self start executed in parallel from boot, further reduced the system start-up time, reduced period of reservation of number.Specifically:
Bus is the PCI-E bus.
Primary processor enumerate on the bus from processor the time, according to slot number from processor place, for this from the corresponding PCI-E of processor distribution address, with the bus address space of initialization system.
In addition; In some other embodiments of the present invention; Bus also can be in the buses such as industrial standard (Industry Standard Architecture, be called for short " ISA ") bus, peripheral components interconnected (Peripheral Component Interconnect is called for short " PCI ") bus a kind of; Be not limited to peripheral components high speed interconnected (Peripheral Component Interconnect Express is called for short " PCI-E ") bus.
Primary processor enumerate on the bus from processor the time; Visit earlier the functional processor information that each is preserved from the configuration space of processor according to the order of sequence successively; This functional processor information comprises EIC equipment identification code and manufacturer ID; Whether detect the pairing processor of functional processor information that configuration space preserves again legal, if legal, and the bus address space of initialization system then.
In addition, each comprises EIC equipment identification code and manufacturer ID from functional processor information, by (Bus number bus_num; Device number device_num, function function_num) unique definite, 0＜=device_num＜32; 0＜=function_num＜8; Wherein (0,0,0) is the main bridge device of primary processor end.
Primary processor also is used for the startup file classification according to required loading when processor starts, and will sort out grouping from processor in advance.
At main bootstrap program is when processor loads startup file, and main bootstrap program is according to the classification from processor, for loading startup file in batches from processor in affiliated group.
Startup file comprise compression from boot, operating system nucleus image file and file system.
Main bootstrap program is after loading startup file from processor, to start the step from processor, also comprises following substep:
Main bootstrap program is to load from boot from processor.
From processor start self from boot.
Start from processor self in boot, main bootstrap program loads the operating system nucleus image file and the file system of this processor.
Treat that operating system nucleus image file and file system load completion, the main bootstrap program setting is from the internal memory zone bit of processor.
After being set up from the internal memory zone bit that is polled to self from boot of processor, start the file system of self operating system nucleus image file and carry self.
Second embodiment is and the corresponding method embodiment of this embodiment, this embodiment can with the enforcement of working in coordination of second embodiment.The correlation technique details of mentioning in second embodiment is still effective in this embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in this embodiment also can be applicable in second embodiment.
Need to prove; Each unit of mentioning in each equipment embodiment of the present invention all is a logical block, and physically, a logical block can be a physical location; It also can be the part of a physical location; Can also realize that the physics realization mode of these logical blocks itself is not most important with the combination of a plurality of physical locations, the combination of the function that these logical blocks realized is the key that just solves technical matters proposed by the invention.In addition, for outstanding innovation part of the present invention, above-mentioned each the equipment embodiment of the present invention will not introduced with solving the not too close unit of technical matters relation proposed by the invention, and this does not show that there is not other unit in the said equipment embodiment.
Though through reference some preferred implementation of the present invention; The present invention is illustrated and describes; But those of ordinary skill in the art should be understood that and can do various changes to it in form with on the details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. multicomputer system parallel starting method is characterized in that said system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor;
Said method comprising the steps of:
Primary processor starts main bootstrap program, and enumerate on the bus from processor;
Said main bootstrap program is after loading startup file from processor, to start from processor;
Starting in processor, primary processor loads the operating system nucleus image file of self and starts.
2. multicomputer system parallel starting method according to claim 1 is characterized in that said bus is the PCI-E bus;
Said enumerate on the bus from the processor step, also comprise following substep:
According to slot number from processor place, for this from the corresponding PCI-E of processor distribution address, with the bus address space of the said system of initialization.
3. multicomputer system parallel starting method according to claim 2 is characterized in that, the said step of enumerating on the bus from processor also comprises following substep:
Visit the functional processor information that each is preserved from the configuration space of processor according to the order of sequence successively, this functional processor information comprises EIC equipment identification code and manufacturer ID;
Whether detect the pairing processor of functional processor information that said configuration space preserves legal;
As if legal, then carry out the step of the bus address space of said initialization system.
4. multicomputer system parallel starting method according to claim 1 is characterized in that, and is further comprising the steps of:
According to the startup file classification of required loading when processor starts, will sort out grouping from processor in advance;
At said main bootstrap program is to load from processor the step of startup file, and main bootstrap program is according to the classification from processor, for loading startup file in batches from processor in affiliated group.
5. according to each described multicomputer system parallel starting method in the claim 1 to 4, it is characterized in that, said startup file comprise compression from boot, operating system nucleus image file and file system;
Said main bootstrap program is after loading startup file from processor, to start the step from processor, also comprises following substep:
Main bootstrap program is to load from boot from processor;
From processor start self from the boot initiating hardware;
Start from processor self in the boot initiating hardware, main bootstrap program loads the operating system nucleus image file and the file system of this processor;
Treat that operating system nucleus image file and file system load completion, the main bootstrap program setting is from the internal memory zone bit of processor;
After the said internal memory zone bit that is polled to self from boot from processor is set up, start the file system of self operating system nucleus image file and carry self.
6. a multicomputer system is characterized in that, said system comprises: by at least two processors that bus connects, one of them is a primary processor, and other are from processor;
Primary processor; Be used at first starting main bootstrap program, and enumerate on the bus secondly from processor; After main bootstrap program is to load startup file from processor; Startup is starting in processor from processor at last, and primary processor loads the operating system nucleus image file of self and starts.
7. multicomputer system according to claim 6 is characterized in that, said bus is the PCI-E bus;
Said primary processor enumerate on the bus from processor the time, according to slot number from processor place, for this from the corresponding PCI-E of processor distribution address, with the bus address space of the said system of initialization.
8. multicomputer system according to claim 7; It is characterized in that, said primary processor enumerate on the bus from processor the time, visit earlier the functional processor information that each is preserved from the configuration space of processor according to the order of sequence successively; This functional processor information comprises EIC equipment identification code and manufacturer ID; Whether detect the pairing processor of functional processor information that said configuration space preserves again legal, if legal, and the bus address space of initialization system then.
9. multicomputer system according to claim 6 is characterized in that, said primary processor also is used for the startup file classification according to required loading when processor starts, and will sort out grouping from processor in advance;
At said main bootstrap program is when processor loads startup file, and main bootstrap program is according to the classification from processor, for loading startup file in batches from processor in affiliated group.
10. according to each described multicomputer system in the claim 6 to 9, it is characterized in that, said startup file comprise compression from boot, operating system nucleus image file and file system;
Said main bootstrap program is after loading startup file from processor, to start the step from processor, also comprises following substep:
Main bootstrap program is to load from boot from processor;
From processor start self from boot;
Start from processor self in boot, main bootstrap program loads the operating system nucleus image file and the file system of this processor;
Treat that operating system nucleus image file and file system load completion, the main bootstrap program setting is from the internal memory zone bit of processor;
After the said internal memory zone bit that is polled to self from boot from processor is set up, start the file system of self operating system nucleus image file and carry self.
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