CN114122202A - Chip and preparation method thereof - Google Patents
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- CN114122202A CN114122202A CN202111331993.7A CN202111331993A CN114122202A CN 114122202 A CN114122202 A CN 114122202A CN 202111331993 A CN202111331993 A CN 202111331993A CN 114122202 A CN114122202 A CN 114122202A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000000059 patterning Methods 0.000 claims abstract description 19
- 229910002601 GaN Inorganic materials 0.000 claims description 15
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 13
- 229910052594 sapphire Inorganic materials 0.000 claims description 12
- 239000010980 sapphire Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 238000010146 3D printing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 12
- 230000002427 irreversible effect Effects 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Electroluminescent Light Sources (AREA)
Abstract
The invention relates to a chip and a preparation method thereof. The chip preparation method comprises the following steps: providing a substrate; forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises: the first epitaxial layer, the light emitting layer and the second epitaxial layer are sequentially stacked from bottom to top; patterning the laminated structure, and forming a first isolation region in the laminated structure, wherein the first isolation region is exposed out of the first surface of the first epitaxial layer; forming a transparent conductive layer and a first electrode which are sequentially stacked from bottom to top on the top of the laminated structure; preparing a transfer substrate on top of the first electrode; patterning the substrate, forming a second isolation region corresponding to the first isolation region in the substrate, wherein the second isolation region exposes the second surface of the first epitaxial layer, and the second surface is arranged opposite to the first surface; stripping the substrate by adopting a laser stripping process; and patterning the first epitaxial layer, and forming a second electrode on the surface of the first epitaxial layer. The chip preparation method can reduce the influence of heat and stress generated by the laser stripping process on the electrical performance of the chip.
Description
Technical Field
The invention relates to the field of chip manufacturing, in particular to a chip and a preparation method thereof.
Background
In the preparation process of the LED chip, the substrate is usually peeled off by using a laser lift-off process, and the gallium nitride at the interface of the sapphire substrate absorbs laser energy and decomposes, so that the gallium nitride layer and the sapphire epitaxial substrate are separated. The sapphire substrate will generate instantaneous high temperature and release stress when being separated, and the generated instantaneous high temperature and the released compressive stress not only affect the electrical and optical characteristics of the device, but also affect the reliability and stability of the device.
Therefore, how to solve the adverse effect of the laser lift-off process on the chip performance is a problem that needs to be solved urgently.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a chip and a method for manufacturing the same, which aims to solve the adverse effect of the laser lift-off process on the performance of the chip.
A method of chip preparation comprising: providing a substrate; forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises: the first epitaxial layer, the light emitting layer and the second epitaxial layer are sequentially stacked from bottom to top; patterning the laminated structure, and forming a first isolation region in the laminated structure, wherein the first isolation region exposes the first surface of the first epitaxial layer; forming a transparent conductive layer and a first electrode which are sequentially stacked from bottom to top on the top of the laminated structure; preparing a transfer substrate on top of the first electrode; patterning the substrate, and forming a second isolation region corresponding to the first isolation region in the substrate, wherein the second isolation region exposes a second surface of the first epitaxial layer, and the second surface is opposite to the first surface; stripping the substrate by adopting a laser stripping process; and patterning the first epitaxial layer, and forming a second electrode on the surface of the first epitaxial layer.
According to the chip preparation method, the isolation regions are formed on the first surface and the second surface of the epitaxial layer, the chip is divided into relatively independent regions, and the superposition of heat and stress generated by a laser stripping process can be reduced, so that the influence of the laser stripping process on the electrical performance of the chip is reduced, and the reliability and the stability of the chip are improved.
Optionally, the patterning the stacked structure further includes: and forming a groove in the laminated structure, wherein the groove divides the laminated structure into a plurality of chip structures and exposes the first surface.
Optionally, a width of the first isolation region is greater than a width of the trench.
Optionally, the step of preparing a transfer substrate on top of the first electrode comprises: filling a sacrificial layer in the groove and the first isolation region, wherein the top of the sacrificial layer is flush with the top of the first electrode; forming the transfer substrate on top of the sacrificial layer and the first electrode using a 3D printing technique; and removing the sacrificial layer.
Through adopting 3D printing technique to replace traditional metal bonding technology, the irreversible damage that the high temperature that produces when can avoid metal bonding caused epitaxial layer to promote the chip performance. In addition, a metal bonding process is not needed, so that a metal layer does not need to be prepared on the transfer substrate, materials are saved, and the cost is reduced.
Optionally, the material forming the transfer substrate comprises graphene.
Optionally, before forming the second isolation region corresponding to the first isolation region in the substrate, the method further includes: and thinning the substrate.
Optionally, the patterning the first epitaxial layer includes: and etching the first epitaxial layer to expose the groove and the first isolation region and retain the first epitaxial layer on the surface of the light-emitting layer.
Optionally, after forming the second electrode, the method further includes: and scribing the transfer substrate along the grooves to obtain a plurality of independent chips.
Optionally, the substrate comprises a sapphire substrate, the first epitaxial layer comprises an N-type gallium nitride layer, the light emitting layer comprises a multi-quantum well layer, the second epitaxial layer comprises a P-type gallium nitride layer, the transparent conductive layer comprises an ITO layer, the first electrode comprises a P-type electrode, and the second electrode comprises an N-type electrode.
Based on the same inventive concept, the application also provides a chip, and the chip can be prepared by adopting the chip preparation method in any one of the embodiments. The chip is provided with the isolation region in the preparation process, so that heat and stress generated when the substrate is stripped by laser cannot be accumulated, and the influence of the laser stripping process on the performance of the chip is greatly reduced. Therefore, compared with the chip prepared by the traditional method, the chip has higher reliability and better stability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a flow chart of a chip manufacturing method according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional view of a semiconductor structure formed by forming a stacked structure on a substrate according to an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first isolation region according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first isolation region and a trench in an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure obtained after forming a transparent conductive layer and a first electrode according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure obtained after forming a sacrificial layer according to an embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a semiconductor structure obtained after forming a transfer substrate in an embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of a semiconductor structure obtained after removing a sacrificial layer according to an embodiment of the present application.
Fig. 9 is a schematic cross-sectional view of a semiconductor structure obtained by thinning a substrate according to an embodiment of the present application.
Fig. 10 is a cross-sectional view of a semiconductor structure resulting from the formation of a second isolation region in an embodiment of the present application.
FIG. 11 is a schematic cross-sectional view of a semiconductor structure obtained after peeling off a substrate according to an embodiment of the present application.
Fig. 12 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second electrode according to an embodiment of the present application.
Fig. 13 is a schematic cross-sectional view of a chip disclosed in an embodiment of the present application.
Description of reference numerals:
100-a substrate; 101-a first epitaxial layer; 102-a light emitting layer; 103-a second epitaxial layer; 104-a first isolation region; 105-a trench; 106-transparent conductive layer; 107-a first electrode; 108-a sacrificial layer; 109-a transfer substrate; 110-a second isolation region; 111-a second electrode.
It should be noted that these drawings are intended to illustrate the general nature of the methods, structures, and/or materials used in the example embodiments, and to supplement the written description provided below. The drawings, however, are not to scale, may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting the scope of values or properties encompassed by example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of the same reference numbers in various figures is intended to indicate the presence of the same elements or features.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.
Embodiments of the application are described herein with reference to cross-sectional structural illustrations that are idealized embodiments (and/or intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In the preparation process of the LED chip, a growth substrate of the chip is usually stripped by a laser stripping process. However, the instantaneous high temperature and stress generated by the laser lift-off process can have an impact on the performance of the chip.
Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.
As shown in fig. 1, an embodiment of the present application provides a method for manufacturing a chip, which specifically includes:
s10: providing a substrate;
s20: forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises: the first epitaxial layer, the light emitting layer and the second epitaxial layer are sequentially stacked from bottom to top;
s30: patterning the laminated structure, and forming a first isolation region in the laminated structure, wherein the first isolation region is exposed out of the first surface of the first epitaxial layer;
s40: forming a transparent conductive layer and a first electrode which are sequentially stacked from bottom to top on the top of the laminated structure;
s50: preparing a transfer substrate on top of the first electrode;
s60: patterning the substrate, forming a second isolation region corresponding to the first isolation region in the substrate, wherein the second isolation region exposes the second surface of the first epitaxial layer, and the second surface is arranged opposite to the first surface;
s70: stripping the substrate by adopting a laser stripping process;
s80: and patterning the first epitaxial layer, and forming a second electrode on the surface of the first epitaxial layer.
Specifically, as shown in fig. 2, the substrate 100 provided in step S10 may be, for example, a sapphire substrate, a silicon substrate, or other substrates.
In step S20, with reference to fig. 2, a first epitaxial layer 101, a light emitting layer 102 and a second epitaxial layer 103 are sequentially formed on the surface of the substrate 100. Illustratively, the first epitaxial layer 101 may be an N-type gallium nitride layer, the light emitting layer 102 may be a Multi Quantum Well (MQW), and the second epitaxial layer 103 may be a P-type gallium nitride layer. As an example, the chip prepared in this example may be an LED chip, for example, a GaN-based LED chip. The GaN-based LED has the advantages of high luminous efficiency, energy conservation, environmental protection, long service life, small volume and the like.
In step S30, a schematic cross-sectional structure of the semiconductor structure obtained after patterning the stacked structure is shown in fig. 3. A first isolation region 104 is formed in the stacked structure, and the first isolation region 104 penetrates through the second epitaxial layer 103 and the light emitting layer 102 to expose the first surface of the first epitaxial layer 101. In this embodiment, a surface of the first epitaxial layer 101 away from the substrate 100 is used as a first surface.
Optionally, in an embodiment, as shown in fig. 4, the step of patterning the stacked structure further includes: a trench 105 is formed in the stacked structure, the stacked structure is divided into a plurality of chip structures by the trench 105, and the first surface is exposed by the trench 105. As an example, when fabricating chips on a wafer, the trenches 105 may be used to divide the wafer into a number of dies arranged in an array.
For example, the number of the first isolation regions 104 may be multiple, and the width of the first isolation region 104 is greater than the width of the trench 105, so as to form multiple relatively independent chip regions on the substrate 100, thereby reducing the superposition of high temperature and stress generated when the substrate is stripped by laser, and reducing the influence of the high temperature and the stress on the chip performance.
In step S40, as shown in fig. 5, the transparent conductive layer 106 and the first electrode 107 are formed on the top of the stacked structure in this order from bottom to top. Illustratively, the transparent conductive layer 106 may be an ITO layer (Indium Tin Oxide film). ITO is a transparent electrode material with high conductivity, high transmittance, high mechanical hardness and good chemical stability. As an example, the ITO layer may be prepared using a metal organic vapor deposition (MOCVD) process. Illustratively, the first electrode 107 may be a P-type electrode. Alternatively, the material forming the P-type electrode may include, but is not limited to, one or a combination of Ti, Pt, Au, Cr, Al, and Ni.
In step S50, as shown in fig. 6-8, the step of preparing the transfer substrate 109 on top of the first electrode 107 includes:
s51: the trench 105 and the first isolation region 104 are filled with a sacrificial layer 108, and the top of the sacrificial layer 108 is flush with the top of the first electrode 107, as shown in fig. 6.
For example, the sacrificial layer 108 filled in the trench 105 and the first isolation region 104 may be a photoresist layer. In order to ensure the flatness of the transfer substrate 109, the top surface of the photoresist layer formed in this step is in conformity with the height of the top surface of the first electrode 107.
S52: a transfer substrate 109 is formed on top of the sacrificial layer 108 and the first electrode 107 using 3D printing techniques, as shown in fig. 7.
S53: the sacrificial layer 108 is removed as shown in fig. 8.
Illustratively, the material forming the transfer substrate 109 may be graphene.
In a conventional chip preparation process, a metal bonding process is usually adopted to bond a chip and a transfer substrate silicon wafer, and the metal bonding process needs to be performed under high temperature and high pressure, but the high temperature and high pressure can cause irreversible damage to an epitaxial layer in the chip. In addition, the metal bonding process needs to manufacture a layer of metal on the transfer substrate, so that the cost is high, and the requirements on the warping degree and the alignment precision of the gallium nitride epitaxy and the transfer substrate are high. In this embodiment, a transfer substrate 109 is formed on the tops of the sacrificial layer 108 and the first electrode 107 by using a 3D printing technology, instead of a conventional metal bonding process, so that irreversible damage to the epitaxial layer due to high temperature generated during metal bonding can be avoided, and the performance of the chip can be improved. In addition, a metal bonding process is not needed, so that a metal layer does not need to be prepared on the transfer substrate, materials are saved, and the cost is reduced.
After the transfer substrate 109 is formed, the sacrificial layer 108 is removed, resulting in the structure shown in fig. 8.
In step S60, the substrate 100 is patterned to form a second isolation region corresponding to the first isolation region 104 in the substrate 100, wherein the second isolation region exposes a second surface of the first epitaxial layer 101, and the second surface is opposite to the first surface.
Optionally, before forming the second isolation region 110 corresponding to the first isolation region 104 in the substrate 100, a step of thinning the substrate 100 may be further included. For example, as shown in fig. 9, taking a sapphire substrate as an example, the sapphire substrate may be thinned first for the convenience of laser beam injection.
After the sapphire substrate is thinned, as shown in fig. 10, a second isolation region 110 may be formed in the thinned sapphire substrate through a photolithography process and an ICP etching process (Inductively coupled Plasma Etch). The second isolation region 110 is disposed corresponding to the first isolation region 104, exposing the second surface of the first epitaxial layer 101. The second surface is a surface of the first epitaxial layer 101 near the substrate 100.
In step S70, the substrate 100 is peeled off using a laser lift-off process, as shown in fig. 11.
Illustratively, after forming the second isolation region 110, the first epitaxial layer 101 in contact with the sapphire substrate is decomposed using laser energy to separate the sapphire substrate from the first epitaxial layer 101, resulting in the structure shown in fig. 11. Because the first surface and the second surface of the first epitaxial layer 101 are both provided with the isolation regions, the isolation regions divide each chip structure into relatively independent regions, thereby reducing the accumulation of high temperature and stress in the process of laser stripping the substrate 100, and relieving the influence of the laser stripping process on the chip performance to a certain extent.
As an example, in the preparation process of a batch of LED chips, since the first isolation region 104 and the second isolation region 110 divide the stacked structure into different sub-regions, when the substrate 100 is removed by a laser lift-off process, the high temperature and stress generated between the substrate 100 and the first epitaxial layer 101 by the laser can be localized in each sub-region, so as to reduce the accumulation of high temperature and stress, and reduce the influence thereof on the electrical and optical performance of the LED chips.
In step S80, as shown in fig. 12, the first epitaxial layer 101 is patterned, and a second electrode 111 is formed on the surface of the first epitaxial layer 101. The step of patterning the first epitaxial layer 101 includes: the first epitaxial layer 101 is etched to expose the trenches 105 and the first isolation regions 104, leaving the first epitaxial layer 101 on the surface of the light emitting layer 102.
Illustratively, the first epitaxial layer 101 may be an N-type gallium nitride layer, and the second electrode 111 may be an N-type electrode. The N-type gallium nitride layer may be etched by photolithography and/or ICP etching, leaving only the portion on the surface of the light emitting layer 102, resulting in an N region. And then preparing an N-type electrode on the surface of the N region by adopting photoetching and evaporation processes. Alternatively, the material forming the N-type electrode may include, but is not limited to, one or a combination of Ti, Pt, Au, Cr, Al, and Ni.
In one embodiment, after forming the second electrode 111, the method further includes: the transfer substrate 109 is scribed along the trenches 105 to obtain a number of individual chips. To obtain individual chips, the transfer substrate 109 may be scribed along the trenches 105, resulting in an LED chip as shown in fig. 13. Illustratively, the LED chip shown in fig. 13 is a vertical LED chip.
The present application further provides a chip, as shown in fig. 13, which can be prepared by the chip preparation method in any of the above embodiments. Specifically, the chip includes: a first electrode 107, a transparent conductive layer 106, a second epitaxial layer 103, a light emitting layer 102, a first epitaxial layer 101, and a second electrode 111. As an example, the first electrode 107 may be a P-type electrode, the transparent conductive layer 106 may include, but is not limited to, an ITO layer, the second epitaxial layer 103 may be a P-type gallium nitride layer, the light emitting layer 102 may include, but is not limited to, an MQW layer, the first epitaxial layer 101 may be an N-type gallium nitride layer, and the second electrode may be an N-type electrode.
The chip is prepared by the chip preparation method in any embodiment, so that irreversible damage to the epitaxial layer caused by high-temperature and high-pressure environments in a metal bonding process is avoided, and the isolation region is arranged in the preparation process, so that heat and stress generated when the substrate is stripped by laser cannot be accumulated, and the influence on the performance of the chip is greatly reduced. Therefore, compared with the chip prepared by the traditional method, the chip has higher reliability and better stability.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a chip, comprising:
providing a substrate;
forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises: the first epitaxial layer, the light emitting layer and the second epitaxial layer are sequentially stacked from bottom to top;
patterning the laminated structure, and forming a first isolation region in the laminated structure, wherein the first isolation region exposes the first surface of the first epitaxial layer;
forming a transparent conductive layer and a first electrode which are sequentially stacked from bottom to top on the top of the laminated structure;
preparing a transfer substrate on top of the first electrode;
patterning the substrate, and forming a second isolation region corresponding to the first isolation region in the substrate, wherein the second isolation region exposes a second surface of the first epitaxial layer, and the second surface is opposite to the first surface;
stripping the substrate by adopting a laser stripping process;
and patterning the first epitaxial layer, and forming a second electrode on the surface of the first epitaxial layer.
2. The method for preparing a chip of claim 1, wherein said patterning said stack further comprises:
and forming a groove in the laminated structure, wherein the groove divides the laminated structure into a plurality of chip structures and exposes the first surface.
3. The method of manufacturing a chip of claim 2, wherein a width of the first isolation region is greater than a width of the trench.
4. The method for preparing a chip according to claim 2, wherein preparing a transfer substrate on top of the first electrode comprises:
filling a sacrificial layer in the groove and the first isolation region, wherein the top of the sacrificial layer is flush with the top of the first electrode;
forming the transfer substrate on top of the sacrificial layer and the first electrode using a 3D printing technique;
and removing the sacrificial layer.
5. The chip preparation method of claim 4, wherein a material forming the transfer substrate comprises graphene.
6. The method for preparing a chip according to claim 1, wherein before forming the second isolation region corresponding to the first isolation region in the substrate, the method further comprises:
and thinning the substrate.
7. The method of preparing a chip of claim 2, wherein said patterning said first epitaxial layer comprises:
and etching the first epitaxial layer to expose the groove and the first isolation region and retain the first epitaxial layer on the surface of the light-emitting layer.
8. The method for preparing a chip according to claim 2, wherein forming the second electrode further comprises:
and scribing the transfer substrate along the grooves to obtain a plurality of independent chips.
9. The method of fabricating a chip of any of claims 1-8, wherein the substrate comprises a sapphire substrate, the first epitaxial layer comprises an N-type gallium nitride layer, the light emitting layer comprises a multiple quantum well layer, the second epitaxial layer comprises a P-type gallium nitride layer, the transparent conductive layer comprises an ITO layer, the first electrode comprises a P-type electrode, and the second electrode comprises an N-type electrode.
10. A chip produced by the method for producing a chip according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111331993.7A CN114122202B (en) | 2021-11-11 | 2021-11-11 | Chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111331993.7A CN114122202B (en) | 2021-11-11 | 2021-11-11 | Chip and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN114122202A true CN114122202A (en) | 2022-03-01 |
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