CN114089171B - Chip measurement and control system and test method for integrated circuit electrical failure analysis - Google Patents
Chip measurement and control system and test method for integrated circuit electrical failure analysis Download PDFInfo
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- CN114089171B CN114089171B CN202210058696.8A CN202210058696A CN114089171B CN 114089171 B CN114089171 B CN 114089171B CN 202210058696 A CN202210058696 A CN 202210058696A CN 114089171 B CN114089171 B CN 114089171B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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Abstract
The invention discloses a chip measurement and control system and a test method for integrated circuit electrical failure analysis, the system realizes flexible and reliable optical signal coupling between failure chips to be tested in different packaging forms and a photoelectric detector, and provides a triggering means for entering and maintaining a specific failure state for the failure chips to be tested through interaction among an upper computer, a failure chip card assembly and a failure chip measurement and control assembly; and secondly, the failure representation working current of the failure chip to be detected is continuously sampled and detected in real time, so that the identification and monitoring of the failure state of the failure chip to be detected are ensured. And finally, real-time monitoring of the detection environment of the to-be-detected failure chip is realized through the environment variable sensing module.
Description
Technical Field
The invention relates to the technical field of chip measurement and control, in particular to a chip measurement and control system and a test method for integrated circuit electrical failure analysis.
Background
The Integrated Circuit (Integrated Circuit) industry is the core of the electronic information technology industry, is strategic, basic and pioneering industry for supporting the development of the economy and society and guaranteeing the national security, and the Integrated Circuit industry development planning suggestion of thirteen five in China indicates that the difference between the Integrated Circuit industry and the international advanced level is gradually reduced in 2020, the mass production of 16-14 nanometer manufacturing process is realized, and the international advanced level is reached in the major link of the Integrated Circuit industry chain in 2030, so that the spanning development is realized; in fact, the development of the integrated circuit industry is systematic, the development of the design, process, test and application techniques contained in the integrated circuit industry is carried out synchronously, the four techniques are also key techniques in several stages from the design to the manufacture and to the application of a Chip (Chip), and corresponding Chip products are produced in each stage, including a Chip layout and a simulation model Chip in the design stage, a prototype Chip in the manufacturing stage and a commodity Chip in the application stage. However, the chips at each stage exhibit certain variations in functionality, performance, reliability, environmental suitability, etc. of the chips. These deviations are commonly referred to as "failure problems". In order to locate, trace the source and explore the mechanism of the Failure problem, people need to deeply analyze the Failure problem, namely the Failure analysis (Failure analysis).
Electrical Failure Analysis (EFA) requires not only cross-discipline theoretical Analysis, but also the rational use of various advanced instruments. With the rapid development of chip design level and manufacturing process, besides the traditional visual inspection instruments (such as optical microscope and optical measuring instrument), failure analysis instruments with more advanced principles are also needed. Among such failure analyzers, photoelectric detectors have been in a unique position, such as a near-Infrared photon Emission detector (EMMI) based on the PN junction leakage Emission photon principle, an Infrared Beam Induced Resistance Change detector (IR-OBIRCH) based on the failure conductor conductance gradient principle, an Electro-optic probe detector (EOP) based on the principle that the switching state of a transistor is correlated with an Optical signal, a High-sensitivity mid-Infrared thermal imaging analyzer (High-sensitivity mid-Infrared camera for thermal analysis) based on the Infrared photon principle in hot spot radiation, and the like. The instrument can cover most photoelectric physical mechanisms related to failure, and is a reliable and necessary tool for analyzing electrical failure.
However, the above photoelectric detector is applicable on the premise that: the chip sample to be tested needs to be subjected to necessary pretreatment (such as unsealing sampling), and the chip is in an active working state in the testing process, and meanwhile, the failure state is required to be maintained all the time. In addition, since the optical detector uses a micro-optical lens to collect optical signals, the DIE area (DIE) of the sample to be tested needs to be fixedly placed within the working distance and the field of view of the lens, and any slight displacement or dragging during the test will cause the chip to deviate from the optimal detection range. However, the advanced optical detectors proposed at home and abroad do not fully consider the requirements from the aspect of the tested failure chip to be tested, so that there is no software and hardware test guarantee platform which is matched and flexible and has the functions of installing and clamping the failure chip to be tested, triggering and maintaining the failure state, monitoring the failure state and the like.
In the traditional method, a probe is generally adopted to apply power supply and control signals to a chip, or a to-be-detected failure chip is kept in situ on a printed circuit board of a whole hardware system and is placed in a sample bin of a detector, so that the problems that in the failure analysis process, the coupling difficulty of the to-be-detected chip and an advanced measurement system is high, the space of the sample bin is limited, the reproducibility of the failure state of a complex chip is low, the reliability of original data acquisition is poor, the potential risk of secondary damage to the to-be-detected failure chip is high and the like are finally caused; moreover, although the types of the photoelectric detectors for analyzing the chip failure are rich, there is no hardware system and corresponding measurement and control method which can provide reliable card installation for the chip and can also ensure the failure triggering requirement of the chip, and the above problems become technical problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the foregoing problems, an embodiment of the present invention provides a chip measurement and control system for analyzing an electrical failure of an integrated circuit, including: the device comprises a failure chip clamping assembly, a failure chip measurement and control assembly, a photoelectric detector and an upper computer; the failure chip card assembly component is connected with the failure chip measurement and control component through a board-level interconnection connector and is coupled with the photoelectric detector, and the upper computer is in communication connection with the photoelectric detector and the failure chip measurement and control component;
the failure chip clamping assembly is used for fixing a failure chip to be tested, acquiring the working current of the failure chip to be tested, and transmitting the working current of the failure chip to be tested to the failure chip measurement and control assembly in real time through the board-level interconnection connector; the failure chip measurement and control assembly is used for collecting the working current of the failure chip to be detected and sending the working current to the upper computer; the upper computer is used for comparing the working current with a preset failure current, judging whether the failure chip to be detected is in a failure state or not based on a comparison result, and sending a control signal to the photoelectric detector if the failure chip to be detected is in the failure state; the photoelectric detector is used for collecting optical signals of a failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer; and the upper computer collects the optical signal of the failure chip to be detected and generates a failure chip control strategy based on the optical signal.
In one embodiment, the failed chip-in-card assembly includes: the chip card seat is fixed and the external power interface is connected with the chip card seat;
the fixed chip clamping seat is used for fixing the to-be-detected failure chip, acquiring the working current of the to-be-detected failure chip and transmitting the working current of the to-be-detected failure chip to the chip measurement and control assembly in real time through the board-level interconnection connector;
the external power supply interface is connected with an external power supply and used for providing working voltage for the to-be-tested failure chip.
In one embodiment, the upper computer is further configured to generate a logic level switching instruction according to the failed chip control strategy, and transmit the logic level switching instruction to the failed chip measurement and control component.
In one embodiment, the failure chip measurement and control component includes: the device comprises a microprocessor module, a communication module, a current acquisition module and a level type hot switching module;
the current acquisition module is used for acquiring the working current of the failure chip to be detected in real time and transmitting the working current to the microprocessor module;
the microprocessor module is connected with the current acquisition module and the level type hot switching module, is connected with the upper computer through the communication module, and is used for sending the working current to the upper computer through the communication module and transmitting the logic level switching instruction to the level type hot switching module;
and the level type hot switching module is used for switching an output level according to the logic level switching instruction and sending the output level to the failed chip card assembly.
In one embodiment, the current collection module comprises: the gain controller and the transimpedance amplification circuit;
the gain controller is connected with the microprocessor and the transimpedance amplification circuit and is used for acquiring feedback network impedance and generating current amplification times based on the feedback network impedance;
the transimpedance amplification circuit is used for amplifying the working current based on the current amplification factor and transmitting the amplified working current to the microprocessor module.
In one embodiment, the measurement and control component for the to-be-tested failure chip further includes: a power supply module;
the power module is connected with the microprocessor module, is connected with the failure chip card assembly through the board-level interconnection connector and is used for providing working voltage for the microprocessor module and the failure chip to be tested.
In one embodiment, the measurement and control component for the to-be-tested failure chip further includes: an environment variable sensing module;
the environment variable sensing module is connected with the microprocessor module and used for monitoring the temperature and the humidity of a detection environment, generating an environment variable and sending the environment variable to the microprocessor module.
In view of the above, in a second aspect of the present application, a chip measurement and control method for electrical failure analysis of an integrated circuit is further provided, including:
the failure chip clamping assembly fixes a failure chip to be tested, obtains the working current of the failure chip to be tested, and transmits the working current of the failure chip to be tested to the failure chip measurement and control assembly in real time through the board-level interconnection connector;
the failure chip measurement and control assembly collects the working current of the failure chip to be measured and sends the working current to an upper computer;
the upper computer compares the working current with a preset failure current, judges whether the failure chip to be detected is in a failure state or not based on a comparison result, and sends a control signal to the photoelectric detector if the failure chip to be detected is in the failure state;
the photoelectric detector is used for collecting optical signals of a failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer;
and the upper computer collects the optical signal of the failure chip to be detected and generates a failure chip control strategy based on the optical signal.
In one embodiment, further comprising:
and the upper computer generates a logic level switching instruction according to the failure chip control strategy and transmits the logic level switching instruction to the failure chip measurement and control assembly.
In one embodiment, the failure chip measurement and control component collects the working current of the failure chip to be tested, and sends the working current to an upper computer, and the method comprises the following steps:
the current acquisition module acquires the working current of the failure chip to be detected in real time and transmits the working current to the microprocessor module;
the microprocessor module sends the working current to the upper computer through the communication module and transmits the logic level switching instruction to the level type hot switching module;
and the level type hot switching module switches output levels according to the logic level switching instruction and sends the output levels to the failed chip card assembly.
The technical scheme provided by the embodiment of the invention has the beneficial effects that at least:
according to the chip measurement and control system and the test method for the electrical failure analysis of the integrated circuit, the failure chip to be tested is reliably coupled with the photoelectric detector through the fixation of the failure chip mounting component on the failure chip to be tested, the operation conditions required for triggering and maintaining the failure state are provided for the failure chip to be tested through the interaction among the upper computer, the failure chip mounting component and the failure chip measurement and control component, the real-time monitoring of the working current of the failure chip to be tested is realized, finally, according to the optical signal of the failure chip to be tested, the upper computer can provide a corresponding operation state control method for the chip to be tested according to the optical signal, the failure chip to be tested is ensured to enter and maintain the failure state, and the control precision and the test efficiency of the failure state of the failure chip to be tested are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a chip measurement and control system for electrical failure analysis of an integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a failed chip card mounting assembly according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a measurement and control assembly of a failed chip according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a current collection module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a three-track floating power supply method according to an embodiment of the present invention;
fig. 6 is a flowchart of a test of a to-be-tested failure chip provided in embodiment 1;
FIG. 7 is a flowchart of a chip measurement and control method for electrical failure analysis of an integrated circuit according to an embodiment of the present invention;
fig. 8 is a flowchart of step S702 according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Referring to fig. 1, a chip measurement and control system for electrical failure analysis of an integrated circuit according to an embodiment of the present invention includes: the device comprises a failure chip clamping component 1, a failure chip measurement and control component 2, a photoelectric detector 3 and an upper computer 4; the failure chip card assembly component 1 and the failure chip measurement and control component 2 are connected through a board-level interconnection connector and are coupled with the photoelectric detector 3, and the upper computer 4 is in communication connection with the photoelectric detector 3 and the failure chip measurement and control component 2;
the failure chip clamping assembly 1 is used for fixing a failure chip to be tested, acquiring the working current of the failure chip to be tested, and transmitting the working current of the failure chip to be tested to the failure chip measurement and control assembly 2 in real time through a board-level interconnection connector; the failure chip measurement and control assembly 2 is used for collecting the working current of the failure chip to be detected and sending the working current to the upper computer 4; the upper computer 4 is used for comparing the working current with a preset failure current, judging whether the failure chip to be detected is in a failure state or not based on a comparison result, and sending a control signal to the photoelectric detector 3 if the failure chip to be detected is in the failure state; the photoelectric detector 3 is used for collecting optical signals of a failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer 4; and the upper computer 4 collects the optical signal of the to-be-detected failure chip and generates a failure chip control strategy based on the optical signal.
Specifically, the upper computer 4 is further configured to generate a logic level switching instruction according to the failed chip control strategy, and transmit the logic level switching instruction to the failed chip measurement and control component 2.
Specifically, the transverse dimension of the failed chip card-loading assembly 1 is less than 5 inches, and the failed chip card-loading assembly can enter a sample bin of a conventional photoelectric detector 3, so that the photoelectric detector 3 collects optical signals related to the failed position and the failed degree of the chip, the photoelectric detector 3 is controlled by an upper computer 4, and the collected data (namely the optical signals) are sent to the upper computer 4 for processing and analyzing; in addition, the sample cabin of the photoelectric detector 3 also provides a closed external environment without stray light interference for a chip measurement and control system for the electrical failure analysis of the integrated circuit, and reduces noise interference of the measurement and control environment.
Furthermore, the failure chip card assembly 1 is used for mounting, unsealing and sampling failure chips to be tested, and can be compatible with chips packaged in different types, the failure chip card assembly 1 supports card mounting of chips placed in a forward direction and inverted in a turning manner by arranging different fixed chip card seats, and the fixed chip card seats can be compatible with various types of commonly packaged chips to be tested, so that the compatibility of the chips can be flexibly expanded; and the failure chip card assembly component 1 provides a required power supply environment and pin control signals for a failure chip to be detected, and transmits the total working current of the failure chip to the chip measurement and control component in real time through the board-level interconnection connector.
Furthermore, the failure chip measurement and control component 2 mainly comprises a microprocessor and various peripheral circuit devices and is a multifunctional component for providing required power supply, control signals, electrostatic protection and working current detection for the failure chip; the chip measurement and control assembly is interconnected with the upper computer 4 through a universal serial bus, can make correct response to a control command from the upper computer 4, and sends the working current and the environmental variable of the to-be-measured failure chip to the upper computer 4 in real time.
Further, board-level interconnection interfaces are respectively integrated on two sides of the printed circuit board in the failure chip card assembly 1 and the failure chip measurement and control assembly 2, and are connected with board-level interconnection connectors, so that the failure chip card assembly 1 is connected with the failure chip measurement and control assembly 2, and the number of interconnection channels of the board-level interconnection interfaces integrated on the failure chip card assembly 1 is enough to cover the number of pins of a failure chip to be measured, which are related to a failure state.
Further, the upper computer 4 adopts any one of the following: a general PC (Personal Computer), a high-performance workstation Computer or a Computer embedded in the advanced photoelectric detector 3.
Further, the upper computer 4 may further store a failure chip control strategy, generate a failure record document, extract an electrical relevant working point of the failure chip to be tested from the failure record document, compile a corresponding test program (for example, a current detection program) according to the electrical relevant working point, and control the microprocessor module in the failure chip measurement and control assembly 2 to provide the same operating condition as that of the failure site for the failure chip to be tested.
In the embodiment, the failure chip to be tested is reliably coupled with the photoelectric detector by fixing the failure chip to be tested through the failure chip clamping assembly, the operating conditions required for triggering and maintaining the failure state are provided for the failure chip to be tested through interaction among the upper computer, the failure chip clamping assembly and the failure chip measurement and control assembly, the real-time monitoring of the working current of the failure chip to be tested is realized, finally, according to the optical signal of the failure chip to be tested, which is acquired by the photoelectric detector, the upper computer can provide a corresponding operating state control method for the chip to be tested according to the optical signal, the failure chip to be tested is ensured to enter and maintain the failure state, and the control precision and the test efficiency of the failure state of the failure chip to be tested are improved.
In one embodiment, the failed chip-in-card assembly 1 includes: a fixed chip card seat 5 and an external power supply interface 6;
the fixed chip card seat 5 is used for fixing the failure chip to be detected, acquiring the working current of the failure chip to be detected, and transmitting the working current of the failure chip to be detected to the chip measurement and control assembly in real time through the board-level interconnection connector.
Specifically, referring to fig. 2, the failed chip card assembly 1 has different fixed chip card seats 5 to hold chips of different package types, wherein the fixed chip card seats 5 include an upright chip card seat and an inverted chip card seat.
Further, the structure of the failed chip card assembly 1 mainly depends on the packaging type and the unsealing sample preparation process of the tested failed chip, and can be divided into the following two parts according to the windowing direction of the fixed chip card seat 5: the fixed chip card seat 5 with a window on the top layer is suitable for a to-be-tested failure chip unsealed on the top layer (indicating a packaging area on one side of a chip tube core with a graph); because the top layer packaging material of the chip subjected to top layer unsealing treatment is removed, and an optical signal is emitted from the top of the chip, the top layer of the fixed chip clamping seat 5 also needs to be kept open, and then the chip clamping seat is placed upright to serve as the fixed chip clamping seat 5, so that the detection analysis of an infrared beam induced resistance change detector and a photoelectric probe detector (two types of photoelectric detectors 3) can be matched, the detection is specific to the failure of an upper conductive metal material of an integrated circuit, and the top layer unsealing sample preparation treatment needs to be carried out on the failed chip to be detected. Secondly, a fixed chip clamping seat 5 with a bottom layer windowing is adopted, the fixed chip clamping seat is suitable for a to-be-tested failure chip unsealed on the bottom layer (indicating a packaging area on the side, without a graph, of a to-be-tested failure chip tube core), besides the turnover inversion chip clamping seat without bottom shielding is adopted, windowing processing needs to be carried out on a printed circuit board below the turnover inversion chip clamping seat, photon radiation caused by chip failure can be ensured to enter an objective lens of an advanced photoelectric detector 3, detection and analysis of a near infrared photon emission detector (one type of the photoelectric detector 3) can be matched, the detection is carried out on failure aiming at a semiconductor junction material on the lower layer of an integrated circuit, and therefore bottom layer unsealing sample preparation processing needs to be carried out on the to-be-tested failure chip.
Specifically, the working current of the to-be-tested failure chip is transmitted to the chip measurement and control assembly in real time through the board-level interconnection connector by adopting a current acquisition channel, wherein the current acquisition channel adopts a printed circuit board wiring without crosstalk and impedance matching.
And the external power supply interface 6 is connected with an external power supply and used for providing working voltage for the to-be-tested failure chip.
Specifically, the external power supply interface 6 is a standby power supply interface, and when the power supply provided by the failure chip measurement and control assembly 2 cannot meet the requirements of the failure chip, an external power supply device can be used for supplying power to the failure chip.
In one embodiment, referring to fig. 3, the failure chip measurement and control component 2 includes: the system comprises a microprocessor module 7, a communication module 8, a current acquisition module 9 and a level type hot switching module 10;
the current collection module 9 is used for collecting the working current of the to-be-detected failure chip in real time and transmitting the working current to the microprocessor module 7.
The microprocessor module 7 is connected with the current acquisition module 9 and the level type hot switching module 10, is connected with the upper computer 4 through the communication module 8, and is used for sending the working current to the upper computer 4 through the communication module 8 and transmitting the logic level switching instruction to the level type hot switching module 10.
Specifically, the microprocessor module 7 adopts a general microcontroller, and can also adopt a digital signal processor or a programmable multi-channel data acquisition card to realize the acquisition and monitoring of the working current.
Further, the communication module 8 adopts a serial port communication chip to realize the interconnection of the microprocessor module 7 and the upper computer 4 through a USB interface.
The level type hot switch module 10 is configured to switch an output level according to the logic level switch instruction, and send the output level to the disabled chip card assembly 1.
Specifically, the level type hot switch module 10 utilizes the bus transceiver to realize switching (i.e., logic level switching) between a TTL level (transistor-transistor logic level) and a CMOS level (Complementary Metal Oxide Semiconductor PMOS + NMOS, voltage controller level), the upper computer 4 sends a logic level switching instruction to the microprocessor, and the microprocessor module 7 adjusts the transmission polarity of the bus transceiver accordingly and sends a logic level switching instruction to the level type hot switch module 10, so that the level type hot switch module 10 realizes hot switching.
In one embodiment, the current collection module 9 includes: a gain controller 11 and a transimpedance amplifier circuit 12;
the gain controller 11 is connected to the microprocessor and the transimpedance amplification circuit 12, and is configured to obtain a feedback network impedance and generate a current amplification factor based on the feedback network impedance.
Specifically, referring to fig. 4, based on a current detection program transmitted by the upper computer 4, the microprocessor module 7 sends an adjustment instruction to the gain controller 11 according to the amplitude of the current in the current detection program, and the gain controller 11 adjusts the impedance of the feedback network through the analog gate and generates the current amplification factor based on the impedance of the feedback network.
Further, the microprocessor module 7 may also perform data preprocessing on the acquired data based on a current detection program, including converting an ADC (analog-to-digital converter) digital value into a current value, performing digital filtering, and connecting the gain controller 11 through a GPIO (General-purpose input/output) interface.
The transimpedance amplification circuit 12 is configured to amplify the working current based on the current amplification factor, and transmit the amplified working current to the microprocessor module 7.
In one embodiment, the measurement and control component 2 of the to-be-tested failure chip further includes: a power supply module 13;
the power module 13 is connected with the microprocessor module 7, connected with the failure chip card assembly 1 through the board-level interconnection connector and used for providing working voltage for the microprocessor module 7 and the failure chip to be tested.
Specifically, the power module 13 is connected to the fixed chip card holder 5 in the failed chip card assembly 1 through the board-level interconnection connector, so as to provide a required power supply environment for the failed chip to be tested.
Further, the power module 13 uses a linear voltage regulator or a DC/DC conversion chip, and provides common chip operating voltages including 3.3V, 5V, and the like and voltages required by the microprocessor module 7 by a three-rail floating power supply method, and the power module 13 may also adjust the voltages by a three-rail floating power supply method.
Further, referring to fig. 5, the power supply voltages of the three power supply rails in the three-rail floating ground power supply method are respectively: VDD _ H, VDD _ L and GND; wherein VDD _ H is a supply voltage greater than 3.3V, typically 5V; VDD _ L is a low power supply voltage required by a part of failure chips to be tested, and is usually between 1V and 2V; GND is a common potential; VDD _ H required by a to-be-tested failure chip is directly introduced by a board-level interconnection connector so as to meet the variable power supply requirement of a customer; VDD _ L can be switched between the two power supply channels by selector SW _ L: channel VDD _ L or channel LDO to VDD _ L; wherein, LDO to VDD _ L adopts LDO (Low drop out Regulator), which regulates VDD _ H to the required VDD _ L, thereby simplifying the number of power supply connections; the 3.3V supply required by the microprocessor module 7 is switched between the two channels by the selector SW _ 3.3: channel VDD _ H or channel LDO3.3V, where LDO3.3V converts VDD _ H to a 3.3V voltage with LDO.
Further, due to the fact that the power supply voltages required by the to-be-tested failure chips are different, the power supply requirement of the conventional to-be-tested failure chip is that
5V, the power supply requirement of the power supply of the partial failure chip to be detected is 3.3V or 1V-2V, so that the power supply is carried out through an independent power supply track, different power supply voltages are provided for the failure chips to be detected of different types, only the different failure chips to be detected need to be replaced, the whole circuit does not need to be replaced, the detection cost is reduced, and the detection efficiency is improved.
In one embodiment, the measurement and control component 2 of the to-be-tested failure chip further includes: an environmental variable sensing module 14;
the environment variable sensing module 14 is connected to the microprocessor module 7, and configured to monitor the temperature and humidity of the detected environment, generate an environment variable, and send the environment variable to the microprocessor module 7.
Specifically, the environment variable sensing module 14 employs a sensor chip, and collects environment variables (including but not limited to temperature, humidity, air pressure, vibration, light intensity, and the like, which may affect the collection accuracy of weak signals related to failure) through Peripheral communication interfaces (for example, SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) built in the general-purpose microprocessor in the microprocessor module 7).
Further, the environment variable sensing module 14 may also be used for acquisition by a hand-held instrument connected to the USB interface of the microprocessor.
Referring to fig. 6, the operation of the chip measurement and control system for integrated circuit electrical failure analysis is described in a specific embodiment.
Example 1:
the embodiment is suitable for the situation that the to-be-tested failure chip is correctly mounted and placed in the sample bin, and the upper computer control method and the test routine compile a failure record document according to the to-be-tested failure chip.
Step 1: extracting electrical relevant working points of the failure chip to be detected from the failure record document, wherein the electrical relevant working points include but are not limited to working voltage, power consumption and logic level of a digital pin when the failure chip to be detected fails;
step 2: writing a corresponding test program according to the working point information, wherein the program can control the microprocessor module to provide the same operating conditions as the failure site for the failure chip to be tested;
and step 3: sending a command to a microprocessor module according to a predefined instruction set in an upper computer, and supplying power to a failure chip to be tested by the microprocessor module in sequence;
and 4, step 4: sending a control command, and executing the test program in the step 2 by the microprocessor module to complete the related configuration of the to-be-tested failure chip;
and 5: if the failure state trigger of the failure chip to be tested depends on external excitation, corresponding excitation is applied to the failure chip to be tested, and the excitation includes but is not limited to: electromagnetic wave pulse, heat radiation, vibration, short circuit;
step 6: judging whether the failure chip to be tested enters a failure state or not; the determination methods include, but are not limited to: checking the real-time working current of the failure chip to be detected from the upper computer, and if the current is not greatly different from the current in the failure site of the failure chip to be detected, judging that the chip enters a failure state; if the to-be-tested failure chip is judged to be in the failure state, entering the step 7, and if the to-be-tested failure chip is not successfully in the failure state, returning to the step 1 to execute the flow again in sequence;
and 7: controlling a photoelectric detector in the upper computer, waiting for the completion of optical signal sampling, and generating a failure chip control strategy based on the optical signal; in addition, in order to ensure the reproducibility of the test, the microcontroller module is required to send and store the environment variables of the test process to the upper computer.
Referring to fig. 7, the chip measurement and control method for analyzing the electrical failure of the integrated circuit includes:
s701, the failure chip clamping assembly fixes a failure chip to be detected, working current of the failure chip to be detected is obtained, and the working current of the failure chip to be detected is transmitted to the failure chip measurement and control assembly in real time through the board-level interconnection connector.
Specifically, the failure chip card-loading component is used for loading, unsealing and sampling failure chips to be tested, can be compatible with chips packaged in different types, enables the failure chip card-loading component to support card loading of chips placed in the forward direction and turned upside down through arranging different fixed chip card seats, can be compatible with various types of commonly packaged chips to be tested through the fixed chip card seats, and flexibly expands the compatibility of the chips; and the failure chip card assembly component provides a required power supply environment and a pin control signal for a failure chip to be detected, and transmits the total working current of the failure chip to the chip measurement and control component in real time through the board-level interconnection connector.
S702, the failure chip measurement and control assembly collects the working current of the failure chip to be detected and sends the working current to an upper computer.
Specifically, the failure chip measurement and control component is used for providing a multifunctional component for a required power supply, a control signal, electrostatic protection and working current detection for the failure chip; the chip measurement and control assembly is interconnected with the upper computer through a universal serial bus, can make correct response to a control command from the upper computer, and sends the working current and the environmental variable of the to-be-measured failure chip to the upper computer in real time.
And S703, the upper computer compares the working current with a preset failure current, judges whether the failure chip to be detected is in a failure state or not based on the comparison result, and sends a control signal to the photoelectric detector if the failure chip to be detected is in the failure state.
Specifically, the upper computer generates a logic level switching instruction according to the failure chip control strategy, and transmits the logic level switching instruction to the failure chip measurement and control assembly.
And S704, the photoelectric detector is used for collecting optical signals of the failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer.
Specifically, the photoelectric detector collects optical signals related to the failure position and failure degree of the chip, is controlled by the upper computer, and sends the collected data (namely the optical signals) to the upper computer for processing and analyzing; in addition, the sample cabin of the photoelectric detector also provides a closed external environment without stray light interference for a chip measurement and control system for electrical failure analysis of the integrated circuit, and reduces noise interference of the measurement and control environment.
S705, the upper computer collects the optical signals of the to-be-detected failure chip and generates a failure chip control strategy based on the optical signals.
Furthermore, the upper computer can also store a failure chip control strategy, generate a failure record document, extract the electrical relevant working points of the failure chip to be tested from the failure record document, compile a corresponding test program (for example, a current detection program) according to the electrical relevant working points, and control the microprocessor module in the failure chip measurement and control assembly to provide the same operating conditions as the failure site for the failure chip to be tested.
In an embodiment, referring to fig. 8, in step S702, that is, the failure chip measurement and control component collects a working current of the failure chip to be tested, and sends the working current to an upper computer, the method includes:
s7021, the current acquisition module acquires the working current of the to-be-detected failure chip in real time and transmits the working current to the microprocessor module.
Specifically, based on a current detection program transmitted by the upper computer, the microprocessor module sends an adjustment instruction to the gain controller according to the amplitude of current in the current detection program, and the gain controller adjusts the impedance of the feedback network through the analog gate and generates a current amplification factor based on the impedance of the feedback network.
S7022, the microprocessor module sends the working current to the upper computer through the communication module and transmits the logic level switching instruction to the level type hot switching module.
Further, the microprocessor module may also perform data preprocessing on the acquired data based on a current detection program, including converting an ADC (analog-to-digital converter) digital value into a current value, digital filtering, and the like.
And S7023, switching an output level by the level type hot switching module according to the logic level switching instruction, and sending the output level to the failed chip card installing component.
Specifically, the level type hot switch module utilizes the bus transceiver to realize the switching (i.e., the logic level switching) between a transistor-transistor logic level (TTL) and a CMOS level (Complementary Metal Oxide Semiconductor PMOS + NMOS, voltage controller level), the upper computer sends a logic level switching instruction to the microprocessor, and the microprocessor module adjusts the transmission polarity of the bus transceiver accordingly and sends the logic level switching instruction to the level type hot switch module, so that the level type hot switch module realizes the hot switch.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A chip system of observing and controling for integrated circuit electrical property failure analysis, its characterized in that includes: the device comprises a failure chip clamping assembly, a failure chip measurement and control assembly, a photoelectric detector and an upper computer; the failure chip card assembly component is connected with the failure chip measurement and control component through a board-level interconnection connector and is coupled with the photoelectric detector, and the upper computer is in communication connection with the photoelectric detector and the failure chip measurement and control component;
the failure chip measurement and control assembly comprises: the device comprises a microprocessor module, a communication module, a current acquisition module and a level type hot switching module;
the current acquisition module is used for acquiring the working current of the failure chip to be detected in real time and transmitting the working current to the microprocessor module;
the microprocessor module is connected with the current acquisition module and the level type hot switching module, is connected with the upper computer through the communication module, and is used for sending the working current to the upper computer through the communication module and transmitting a logic level switching instruction to the level type hot switching module;
the level type hot switching module is used for switching an output level according to the logic level switching instruction and sending the output level to the failed chip card assembly;
the upper computer extracts the electrical relevant working points of the failure chip to be tested from the failure record document, writes a corresponding test program according to the working point information, and controls the microprocessor module to provide the same operating conditions as the failure site for the failure chip to be tested; sending a command to a microprocessor module according to a predefined instruction set in an upper computer, and supplying power to a failure chip to be tested by the microprocessor module in sequence; sending a control command, and executing a test program by the microprocessor module to complete the related configuration of the to-be-tested failure chip; if the failure state trigger of the failure chip to be tested depends on external excitation, applying corresponding excitation to the failure chip to be tested;
the failure chip clamping assembly is used for fixing a failure chip to be tested, acquiring the working current of the failure chip to be tested, and transmitting the working current of the failure chip to be tested to the failure chip measurement and control assembly in real time through the board-level interconnection connector; the failure chip measurement and control assembly is used for collecting the working current of the failure chip to be detected and sending the working current to the upper computer; the upper computer is used for comparing the working current with a preset failure current, judging whether the failure chip to be detected is in a failure state or not based on a comparison result, and sending a control signal to the photoelectric detector if the failure chip to be detected is in the failure state; the photoelectric detector is used for collecting optical signals of a failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer; the upper computer collects an optical signal of the failure chip to be detected and generates a failure chip control strategy based on the optical signal;
and the upper computer is also used for generating a logic level switching instruction according to the failure chip control strategy and transmitting the logic level switching instruction to the failure chip measurement and control assembly.
2. The chip measurement and control system for integrated circuit electrical failure analysis of claim 1, wherein the failed chip card assembly comprises: the chip card seat is fixed and the external power interface is connected with the chip card seat;
the fixed chip clamping seat is used for fixing the to-be-detected failure chip, acquiring the working current of the to-be-detected failure chip and transmitting the working current of the to-be-detected failure chip to the failure chip measurement and control assembly in real time through the board-level interconnection connector;
the external power supply interface is connected with an external power supply and used for providing working voltage for the to-be-tested failure chip.
3. The chip measurement and control system for integrated circuit electrical failure analysis of claim 1, wherein the current collection module comprises: the gain controller and the transimpedance amplification circuit;
the gain controller is connected with the microprocessor and the transimpedance amplification circuit and is used for acquiring feedback network impedance and generating a current amplification factor based on the feedback network impedance;
the transimpedance amplification circuit is used for amplifying the working current based on the current amplification factor and transmitting the amplified working current to the microprocessor module.
4. The chip measurement and control system for integrated circuit electrical failure analysis of claim 1, wherein the failed chip measurement and control assembly further comprises: a power supply module;
the power module is connected with the microprocessor module, is connected with the failure chip card assembly through the board-level interconnection connector and is used for providing working voltage for the microprocessor module and the failure chip to be tested.
5. The chip measurement and control system for integrated circuit electrical failure analysis of claim 1, wherein the failed chip measurement and control assembly further comprises: an environment variable sensing module;
the environment variable sensing module is connected with the microprocessor module and used for monitoring the temperature and the humidity of a detection environment, generating an environment variable and sending the environment variable to the microprocessor module.
6. A chip measurement and control method for integrated circuit electrical failure analysis is characterized by comprising the following steps:
the upper computer generates a logic level switching instruction according to the failure chip control strategy and transmits the logic level switching instruction to the failure chip measurement and control assembly;
the upper computer extracts electrical relevant working points of the failure chip to be tested from the failure record document, writes a corresponding test program according to the working point information, and controls the microprocessor module to provide the same operating conditions as the failure site for the failure chip to be tested; sending a command to a microprocessor module according to a predefined instruction set in an upper computer, and supplying power to a failure chip to be tested by the microprocessor module in sequence; sending a control command, and executing a test program by the microprocessor module to complete the related configuration of the to-be-tested failure chip; if the failure state trigger of the failure chip to be tested depends on external excitation, applying corresponding excitation to the failure chip to be tested;
the failure chip clamping assembly fixes a failure chip to be tested, obtains the working current of the failure chip to be tested, and transmits the working current of the failure chip to be tested to the failure chip measurement and control assembly in real time through the board-level interconnection connector;
the failure chip measurement and control assembly collects the working current of the failure chip to be measured and sends the working current to an upper computer;
the upper computer compares the working current with a preset failure current, judges whether the failure chip to be detected is in a failure state or not based on a comparison result, and sends a control signal to a photoelectric detector if the failure chip to be detected is in the failure state;
the photoelectric detector is used for collecting optical signals of a failure chip to be detected and transmitting the optical signals of the failure chip to be detected to the upper computer;
the upper computer collects an optical signal of the failure chip to be detected and generates a failure chip control strategy based on the optical signal;
the failure chip measurement and control assembly collects the working current of the failure chip to be detected and sends the working current to the upper computer, and the failure chip measurement and control assembly comprises:
the current acquisition module acquires the working current of the failure chip to be detected in real time and transmits the working current to the microprocessor module;
the microprocessor module sends the working current to the upper computer through a communication module and transmits the logic level switching instruction to a level type hot switching module;
and the level type hot switching module switches output levels according to the logic level switching instruction and sends the output levels to the failed chip card assembly.
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| CN102253325B (en) * | 2010-05-21 | 2013-07-31 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN102751202B (en) * | 2012-06-29 | 2014-12-31 | 工业和信息化部电子第五研究所 | Ball grid array (BGA) packaging device chip-scale invalidation positioning fixture and method |
| CN104049199A (en) * | 2014-06-16 | 2014-09-17 | 武汉新芯集成电路制造有限公司 | Failure analysis system |
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| CN109725246B (en) * | 2017-10-31 | 2021-05-11 | 无锡华润上华科技有限公司 | Failure analysis method and system for integrated circuit |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN113406484B (en) * | 2021-08-19 | 2021-11-09 | 华芯半导体研究院(北京)有限公司 | Device and method for failure analysis of chip |
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