CN114080100A - Circuit board and method for forming holes thereof - Google Patents

Circuit board and method for forming holes thereof Download PDF

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Publication number
CN114080100A
CN114080100A CN202010849277.7A CN202010849277A CN114080100A CN 114080100 A CN114080100 A CN 114080100A CN 202010849277 A CN202010849277 A CN 202010849277A CN 114080100 A CN114080100 A CN 114080100A
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CN
China
Prior art keywords
hole
pad
layer
circuit board
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010849277.7A
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Chinese (zh)
Inventor
杨凯铭
林晨浩
林伯诚
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Unimicron Technology Corp
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Unimicron Technology Corp
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Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to CN202010849277.7A priority Critical patent/CN114080100A/en
Publication of CN114080100A publication Critical patent/CN114080100A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • H05K1/116Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0023Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via

Abstract

The invention relates to a circuit board and a method for forming holes of the circuit board. The circuit board comprises a photosensitive insulating layer and a first circuit layer. The photosensitive insulating layer is provided with a hole, a first surface and a second surface which are opposite to each other. The hole has a first port formed on the first surface, a second port formed on the second surface, a shaft center, and a hole wall surrounding the shaft center. Portions of the bore wall extend toward the axial center to form at least one annular flange. The first circuit layer is disposed on the first surface and includes a first pad, wherein the hole exposes the first pad. At least one concave cavity is arranged between the annular flange and the first connecting pad. The minimum width of the annular flange is less than the maximum width of the recessed cavity.

Description

Circuit board and method for forming holes thereof
Technical Field
The invention relates to a circuit board and a method for forming holes of the circuit board.
Background
An insulating layer (e.g., a solder mask layer or an inter-board dielectric layer) of a conventional circuit board has one or more holes, such as blind vias or solder mask openings, which are usually filled with a conductive material connected to pads (pads) of the circuit layer. For example, the blind holes of the dielectric layer in the circuit board are usually filled with the conductive pillars, and the solder-proof openings of the solder-proof layer are usually filled with the solder, wherein the conductive pillars and the solder are connected to the pads underneath to electrically connect the circuit layer.
Generally, the shape of the hole (e.g., a blind hole or a solder-mask opening), i.e., the shape of the inner space of the hole, is substantially a frustum (frustum), so that the hole mostly has a relatively flat hole wall, so that the insulating layer has a limited ability to fix the conductive material (e.g., a conductive post or solder) in the hole, which may cause the conductive material to be separated from the underlying pad to generate cracks (crack), thereby reducing the reliability (reliability) of the circuit board.
Disclosure of Invention
The invention provides a circuit board, which comprises a photosensitive insulating layer capable of helping to fix the conductive material.
The invention also provides a hole forming method of the circuit board.
At least one embodiment of the present invention includes a wiring board including a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer is provided with a hole and a first surface and a second surface which are opposite to each other, wherein the hole is provided with a first port formed on the first surface, a second port formed on the second surface, a shaft center and a hole wall surrounding the shaft center, and part of the hole wall extends towards the shaft center to form at least one annular flange. The first circuit layer is disposed on the first surface and includes a first pad, wherein the hole exposes the first pad. At least one recessed cavity is formed between the annular flange and the first pad, and the minimum width of the annular flange is smaller than the maximum width of the recessed cavity.
In at least one embodiment of the present invention, the difference between the inner diameter of the first port and the inner diameter of the second port is within 10 microns.
In at least one embodiment of the present invention, the annular flange is connected to the recessed cavity, and the annular flange and the recessed cavity form a double curved surface (ogee).
In at least one embodiment of the present invention, a portion of the hole wall extends toward the axis to form a plurality of annular flanges, and a plurality of recessed cavities are formed between one of the annular flanges and the first pad. One of the recessed cavities is formed between two adjacent annular flanges.
In at least one embodiment of the present invention, the wall of the hole in each recessed cavity has a concave curved surface, and each annular flange has a rim, wherein at least one rim is formed between two adjacent recessed cavities.
In at least one embodiment of the present invention, the circuit board further includes a conductive material, which fills the hole and the cavity and is connected to the first pad.
In at least one embodiment of the present invention, the conductive material protrudes from the second surface.
In at least one embodiment of the present invention, the photosensitive insulating layer does not contact the first pad.
In at least one embodiment of the present invention, the circuit board further includes a second circuit layer disposed on the second surface and including a second pad, wherein the conductive material is connected between the first pad and the second pad.
In at least one embodiment of the present invention, the wiring board further includes a conductive layer. The conductive layer covers the hole wall of the hole in a full-face manner and does not fill the hole.
In at least one embodiment of the present invention, the circuit board further includes a filling material. The filling material fills the hole, and the conductive layer covers the filling material.
In at least one embodiment of the present invention, an included angle is formed between the hole wall and the first pad of the photosensitive insulating layer, wherein the included angle is between 15 degrees and 45 degrees.
At least one embodiment of the present invention additionally provides a hole forming method of a circuit board. In the hole forming method, firstly, a photosensitive material and a first circuit layer are provided, wherein the photosensitive material covers the first circuit layer, and the first circuit layer comprises a first connecting pad. Next, the focused beam is caused to irradiate the predetermined region of the photosensitive material at least once, wherein a focal point of the focused beam is maintained above the first pad during irradiation of the predetermined region by the focused beam. After the focused light beam irradiates the photosensitive material, the photosensitive material is developed to form a photosensitive insulating layer having holes.
In at least one embodiment of the present invention, the focused beam of light irradiates the predetermined area of the photosensitive material a plurality of times. When the focused light beam irradiates the predetermined area for the nth time, the distance between the focus and the first connecting pad is D (n), wherein n is a positive integer. When the focused light beam irradiates the predetermined area for the (n +1) th time, the distance between the focal point and the first pad is D (n +1), where D (n) ≦ D (n + 1).
In at least one embodiment of the present invention, the method for forming holes further includes performing an electroplating process on the holes after developing the photosensitive material.
In at least one embodiment of the present invention, the method for forming a hole further includes filling a conductive material into the hole after developing the photosensitive material.
Based on the above, by using the annular flange and the recessed cavity formed in the hole, the photosensitive insulating layer can help to fix the conductive material located in the hole, so as to reduce the probability of cracks occurring between the conductive material and the pad (first pad) connected thereto due to separation, thereby contributing to improving the reliability of the circuit board.
Drawings
Fig. 1A to fig. 1C are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to at least one embodiment of the present invention.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to another embodiment of the invention.
Fig. 3A to 3B are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to another embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a wiring board of at least one embodiment of the invention.
[ description of main element symbols ]
100. 200, 300, 400: wiring board 103: photosensitive material
103c, 203a, 203b, 203 c: the modifying unit 110: first circuit layer
111. 211: first pads 112 and 122: wiring
120. 220, and (2) a step of: second circuit layer 121, 221: second pad
130. 230, 330, 430: photosensitive insulating layers 131, 231, 331, 431: first surface
132. 232, 332, 432: second surface 133, 233, 333, 433: hole(s)
133w, 233w, 333w, 433 w: aperture walls 134, 234, 334, 434: annular flange
140. 340, 440: conductive material 190, 390: insulating layer
234e, 334 e: edge 240: conductive layer
250: filler materials a13, a23, a 33: axial center
B1: focused light beams C13, C23, C33, C43: concave cavity
D21, D22, D23: distance DF 1: depth of focus
E11: first port E12: second port
F1: focal points R11, R12, R21, R22, R31, R32: inner diameter
TH1, TH 2: included angles W11, W21: maximum width
W12, W22: minimum width Z1: predetermined area
Detailed Description
In the following description, the dimensions (e.g., length, width, thickness, and depth) of elements (e.g., layers, films, substrates, regions, etc.) in the figures are exaggerated in various proportions for the sake of clarity. Accordingly, the following description and illustrations of the embodiments are not limited to the sizes and shapes of elements shown in the drawings, but are intended to cover deviations in sizes, shapes and both that result from actual manufacturing processes and/or tolerances. For example, the planar surfaces shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements shown in the drawings are for illustrative purposes only, and are not intended to accurately depict the actual shapes of the elements or to limit the scope of the claims.
Furthermore, the terms "about", "approximately" or "substantially" as used herein encompass not only the explicitly recited values and ranges of values, but also the allowable range of deviation as understood by those of ordinary skill in the art, wherein the range of deviation can be determined by the error in measurement, for example, due to limitations of both the measurement system and the process conditions. Furthermore, "about" can mean within one or more standard deviations of the above-described values, e.g., within ± 30%, 20%, 10%, or 5%. The terms "about," "approximately," or "substantially," as used herein, may be selected with an acceptable range of deviation or standard deviation based on optical, etching, mechanical, or other properties, and not all such properties may be applied with one standard deviation alone.
Fig. 1A to fig. 1C are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to at least one embodiment of the present invention. Referring to fig. 1A, in the method for forming a via hole of a circuit board of the present embodiment, first, a photosensitive material 103 and a first circuit layer 110 are provided, wherein the photosensitive material 103 is, for example, a photosensitive Dielectric (PID) material.
The first circuit layer 110 includes at least one first pad 111 and at least one trace 112. Taking fig. 1A as an example, the first circuit layer 110 includes a first pad 111 and a plurality of traces 112. However, in other embodiments, the first circuit layer 110 may also include a plurality of first pads 111 and a trace 112. Therefore, fig. 1A is only for illustration and does not limit the number of the first pads 111 and the traces 112.
The photosensitive material 103 covers the first circuit layer 110 and covers the first pads 111 and the traces 112 more completely. The photosensitive material 103 may be formed on the first circuit layer 110 by coating or attaching. For example, the photosensitive material 103 may be a patch or formed of a fluid material. When the photosensitive material 103 is formed of a fluid material, the photosensitive material 103 may be formed by coating, such as spraying, printing, or spin coating (spin coating). When the photosensitive material 103 is a patch, the photosensitive material 103 may be directly attached to the first circuit layer 110.
In the embodiment shown in fig. 1A, the photosensitive material 103 may be formed on a circuit substrate, wherein the circuit substrate includes the first circuit layer 110 and the insulating layer 190, and the photosensitive material 103 covers the first circuit layer 110 and the insulating layer 190 in a whole. The circuit substrate may be a semi-finished product of a circuit board, wherein the first circuit layer 110 is an outer layer circuit of the circuit substrate and is formed on the insulating layer 190, and the insulating layer 190 may be a dielectric layer of the circuit substrate.
The circuit substrate may further include other circuit layers besides the first circuit layer 110. For example, the circuit substrate may include two or more circuit layers (including the first circuit layer 110), wherein the other circuit layers except the first circuit layer 110 are located under the insulating layer 190. In other words, the photosensitive material 103 may be formed on a circuit substrate already having multiple circuit layers, and entirely covers the outer layer circuit (e.g., the first circuit layer 110) of the circuit substrate.
Next, exposure is performed such that the focused light beam B1 irradiates a predetermined region Z1 of the photosensitive material 103 at least once, and in fig. 1A, the predetermined region Z1 is located on the upper surface of the photosensitive material 103. Fig. 1A is an example in which the focused light beam B1 irradiates the predetermined region Z1 only once. However, in other embodiments (e.g., subsequent embodiments), the focused light beam B1 may illuminate the predetermined region Z1 of the photosensitive material 103 multiple times, i.e., the focused light beam B1 may illuminate the same region on the surface of the photosensitive material 103 multiple times. The focused light beam B1 has a Focus F1 and a Depth Of Focus (DOF) DF1, wherein the Focus F1 is located within the range Of the Depth Of Focus DF 1.
During the irradiation of the focused light beam B1 on the predetermined region Z1, the focal point F1 of the focused light beam B1 remains above the first pad 111 and does not fall on the surface and inside of the first pad 111. Taking fig. 1A as an example, the focal point F1 is located in the photosensitive material 103 directly above the first pad 111. When the focused light beam B1 irradiates the photosensitive material 103, the portion of the photosensitive material 103 irradiated by the focused light beam B1 is chemically changed, thereby forming the modified portion 103 c.
The width of the modified portion 103c is related to the width of the focused light beam B1. The larger the width of the focused light beam B1, the larger the width of the basic modified portion 103 c. Conversely, the smaller the width of the focused light beam B1, the smaller the width of the modified portion 103 c. Since the width of the focused light beam B1 is not uniform, and the focused light beam B1 has a minimum width at its depth of focus DF1, the minimum width of the modifying portion 103c is large to fall within the depth of focus DF 1.
It should be noted that although fig. 1A depicts the outline of the modifying portion 103c by a solid line, in actual situations, there is no obvious boundary (boundary) between the modifying portion 103c and other unmodified portions of the photosensitive material 103, so the outline of the modifying portion 103c depicted by a solid line in fig. 1A is for clarity of explanation and does not mean that there is an obvious boundary between the modifying portion 103c and other unmodified portions of the photosensitive material 103.
Referring to fig. 1A and 1B, after the photosensitive material 103 is irradiated by the focused light beam B1, the photosensitive material 103 is developed to remove the modified portion 103c, thereby forming the photosensitive insulating layer 130. Since the modified portion 103c is formed by irradiation with the focused light beam B1, only the portion of the photosensitive material 103 irradiated with the focused light beam B1 is removed and the portion not irradiated with the focused light beam B1 remains during development. Thus, the photosensitive material 103 may be substantially a negative photoresist.
The photosensitive insulating layer 130 has a hole 133 and a first surface 131 and a second surface 132 opposite to each other, wherein the hole 133 is formed by removing the modified portion 103c, so the hole 133 is formed at the original position of the modified portion 103 c. In other words, the hole 133 is formed where the photosensitive material 103 is illuminated by the previously focused light beam B1, i.e., the predetermined region Z1. In addition, the first circuit layer 110 is disposed on the first surface 131 of the photosensitive insulating layer 130, and the hole 133 exposes the first pad 111 of the first circuit layer 110. Taking fig. 1B as an example, the hole 133 partially exposes the first pad 111, and a portion of the first pad 111, especially a peripheral portion of the first pad 111, is covered by the photosensitive insulating layer 130.
The hole 133 has a center A13 and a hole wall 133w surrounding the center A13. Since the width of the modified portion 103c is related to the diameter of the focused light beam B1, and the focal point F1 of the focused light beam B1 remains above the first pad 111 during the irradiation of the photosensitive material 103 by the focused light beam B1, the hole 133 has a significantly uneven aperture. Compared to the conventional circuit board hole with a frustum shape, the hole wall 133w of the hole 133 is obviously uneven.
In the cavity 133, a portion of the cavity wall 133w extends toward the axis a13 to form at least one annular flange 134. For example, in FIG. 1B, a portion of the aperture wall 133w forms an annular flange 134. However, in other embodiments, the partial hole wall 133w may also form a plurality of annular flanges 134, and thus the annular flanges 134 shown in fig. 1B are for illustration only and do not limit the number of annular flanges 134 within the hole 133.
At least one recessed cavity C13 exists between the annular flange 134 and the first pad 111, and fig. 1B illustrates only one recessed cavity C13 as an example, wherein the recessed cavity C13 is annular, so that the cross-sectional view of the hole 133 (i.e., fig. 1B) looks like two recessed cavities C13. The minimum width W12 of the annular flange 134 is less than the maximum width W11 of the recessed cavity C13 so that the annular flange 134 protrudes from the aperture 133 at the aperture wall 133W of the recessed cavity C13. Further, the annular flange 134 is connected to the recessed cavity C13, and the annular flange 134 and the recessed cavity C13 form a double curved surface (ogee), as shown in fig. 1B.
The hole 133 is a through hole of the photosensitive insulating layer 130, so the hole 133 extends from the first surface 131 to the second surface 132. Therefore, the hole 133 further has a first port E11 and a second port E12, wherein the first port E11 is formed on the first surface 131, and the second port E12 is formed on the second surface 132. In the present embodiment, the inner diameter R11 of the first port E11 and the inner diameter R12 of the second port E12 may be within 10 microns.
However, in other embodiments, the difference between the inner diameter R11 and the inner diameter R12 may fall outside of the above-described range. Therefore, the difference between the inner diameter R11 and the inner diameter R12 is not limited to the above range. In addition, the photosensitive insulating layer 130 may have an included angle TH1 between the hole wall 133w and the first pad 111, wherein the included angle TH1 may be between 15 degrees and 45 degrees, but not limited thereto.
Referring to fig. 1C, after the photosensitive material 103 is developed to form the photosensitive insulating layer 130, a plating process is performed on the holes 133 to form the conductive material 140. The electroplating process may include electroless plating (electroless plating) and electro-plating (electro-plating), and the conductive material 140 may be a solid conductive pillar and fills the hole 133 and the hollow cavity C13, wherein the conductive material 140 is connected to the first pad 111 and may be a conductive blind via (blind via).
During the electroplating process, a metal may be deposited on the second surface 132 of the photosensitive insulating layer 130 and the conductive material 140 to form the second circuit layer 120. Therefore, the second circuit layer 120 can be formed by using electroless plating and electro-plating, and is disposed on the second surface 132. The second circuit layer 120 includes a second pad 121 and a plurality of traces 122, wherein the second pad 121 is disposed on the conductive material 140 and connected to the conductive material 140, so that the conductive material 140 is connected between the first pad 111 and the second pad 121. Thus, the first circuit layer 110 can be electrically connected to the second circuit layer 120 through the conductive material 140.
In the process of forming the second circuit layer 120, a thin metal layer may be formed on the second surface 132 of the photosensitive insulating layer 130 to serve as a seed layer. The thin metal layer can be formed by sputtering or evaporation. Alternatively, the thin metal layer may be a thinned metal foil (e.g., copper foil). The traces 122 of the second circuit layer 120 can be formed by depositing metal on the thin metal layer through electroplating, wherein the traces 122 can be formed by performing a semi-additive process using the thin metal layer. In addition, the trace 122 can also be formed by a subtractive method, and thus is not limited to being formed by a semi-additive method.
The second pads 121 may be formed by continuing the above-mentioned electroplating process after the conductive material 140 is formed. Therefore, the second pads 121 and the conductive material 140 can be integrally formed, so there is no gap (seam) between the second pads 121 and the conductive material 140. To this end, a wiring board 100 including a photosensitive insulating layer 130, a first wiring layer 110, a second wiring layer 120 and a conductive material 140 is generally manufactured.
It is noted that, in the embodiment shown in fig. 1C, the second circuit layer 120 includes a second pad 121 and a plurality of traces 122. However, in other embodiments, the second circuit layer 120 may also include a plurality of second pads 121 and a trace 122, so that fig. 1C is only for illustration and the number of the second pads 121 and the trace 122 included in the circuit board 100 is not limited.
The conductive material 140 may be embedded in the cavity 133 by the annular flange 134 and the recessed cavity C13 formed in the cavity 133, thereby being firmly fixed in the cavity 133. Therefore, compared to the conventional frustum-shaped hole, the hole 133 and the conductive material 140 embedded in the hole 133 have a structure similar to a rivet, so that the sidewall of the photosensitive insulating layer 130 hooks the conductive material to strengthen the fixation of the conductive material 140 in the hole 133, thereby reducing the probability of cracks occurring between the conductive material 140 and the first pad 111 due to separation, and further contributing to the improvement of the reliability of the circuit board 100.
It should be noted that the circuit board 100 in fig. 1C may also be a semi-finished product. In detail, additional circuit layers may be additionally formed on the second circuit layer 120 and the photosensitive insulating layer 130 in fig. 1C, wherein the circuit layers may be formed by build-up (build-up) or lamination. Taking the build-up method as an example, another layer of photosensitive material 103 may be formed on the second circuit layer 120 and the photosensitive insulating layer 130, covering the second circuit layer 120 and the photosensitive insulating layer 130.
Next, according to the method disclosed in fig. 1A to 1B, another photosensitive insulating layer 130 is formed on the second circuit layer 120, wherein another hole 133 is formed above the second pad 121. Then, the electroplating process is performed again to form a conductive material 140 in the hole 133 above the second pad 121, and another circuit layer is formed on the additionally formed photosensitive insulating layer 130, wherein the circuit layer can be electrically connected to the second pad 121 through the conductive material 140. Thus, additional circuit layers are formed on the second circuit layer 120 and the photosensitive insulating layer 130.
In addition, the photosensitive insulating layer 130 formed by the photosensitive material 103 may have rigidity or flexibility, so the circuit board 100 may be a flexible wiring board (fpc) or a rigid wiring board (fpc). Alternatively, the circuit board 100 may be a flexible circuit board or a rigid circuit board in a rigid-flex circuit board (RIGID-FLEX WIRING BOARD).
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to another embodiment of the invention. Referring to fig. 2A to 2C, the hole forming method of the present embodiment is similar to the hole forming method of the previous embodiment, but the main difference is: in the hole forming method shown in fig. 2A to 2E, the focused light beam B1 is irradiated on the predetermined region Z1 of the photosensitive material 103 a plurality of times. The differences between the present embodiment and the foregoing embodiments will be mainly described below.
After providing the photosensitive material 103 and the first wiring layer 110, the focused light beam B1 is made to irradiate a predetermined region Z1 of the photosensitive material 103 a plurality of times. During the time when the focused light beam B1 irradiates the predetermined region Z1 for multiple times, when the focused light beam B1 irradiates the predetermined region Z1 for the nth time, the distance between the focal point F1 of the focused light beam B1 and the first pad 111 is d (n), where n is a positive integer. When the focused light beam B1 irradiates the predetermined region Z1 for the (n +1) th time, the distance between the focal point F1 and the first pad 111 is D (n +1), where D (n) ≦ D (n + 1).
Fig. 2A to 2C illustrate that the focused light beam B1 irradiates the predetermined region Z1 three times. Referring to fig. 2A, when the focused light beam B1 irradiates the predetermined region Z1 of the photosensitive material 103 for the first time, the modified portion 203a is formed on the portion of the photosensitive material 103 irradiated by the focused light beam B1, and a distance D21 exists between the focal point F1 of the focused light beam B1 and the first pad 111. Referring to fig. 2B, when the focused light beam B1 irradiates the predetermined region Z1 for the second time, the modified portion 203B is formed by the portion of the photosensitive material 103 irradiated by the focused light beam B1 for the second time, and a distance D22 exists between the focal point F1 and the first pad 111, wherein a portion of the modified portion 203a is repeatedly irradiated by the focused light beam B1.
Comparing fig. 2A with fig. 2B, it can be seen that distance D21 is significantly less than distance D22. That is, the position of the focal point F1 is not fixed during the first and second irradiation of the predetermined region Z1 by the focused light beam B1, so that the portion of the photosensitive material 103 irradiated by the focused light beam B1 for the first time is significantly different from the portion of the photosensitive material 103 irradiated by the focused light beam B1 for the second time. During the second irradiation of the predetermined region Z1 by the focused light beam B1, the focused light beam B1 irradiates a portion of the photosensitive material 103 that was not irradiated previously, so the size of the modified portion 203B is larger than that of the modified portion 203a, and the modified portion 203B includes the modified portion 203a of the previous time.
Referring to fig. 2C, when the focused light beam B1 irradiates the predetermined region Z1 for the third time, the modified portion 203C is formed on the portion of the photosensitive material 103 irradiated by the focused light beam B1, and a distance D23 exists between the focal point F1 and the first pad 111. At this time, the focal point F1 may be near the second surface 232 of the photosensitive material 103, as shown in fig. 2C. Alternatively, the focal point F1 may also be inside the photosensitive material 103 below the second surface 232. Comparing fig. 2B with fig. 2C, it can be seen that distance D22 is significantly less than distance D23.
During the third irradiation of the predetermined region Z1 by the focused light beam B1, a part of each of the modified portions 203a and 203B is repeatedly irradiated by the focused light beam B1, and the focused light beam B1 is irradiated to the portion of the photosensitive material 103 that was not irradiated twice before. Therefore, the size of the modified portion 203c formed by the third irradiation is larger than that of either of the modified portions 203b and 203a formed by the second irradiation, and the modified portion 203c includes the modified portions 203a and 203b of the previous irradiation.
It can be seen that the position of the focal point F1 obviously changes with each irradiation of the photosensitive material 103 by the focused light beam B1 during the plural times of irradiation of the predetermined region Z1 by the focused light beam B1. When the focused light beam B1 irradiates the predetermined region Z1 for the first time, the focal point F1 is closest to the first pad 111. Thereafter, as the number of times the focused light beam B1 irradiates the predetermined region Z1 increases, the focal point F1 gradually moves away from the first pad 111. In addition, the focal point F1 may remain inside the photosensitive material 103 and the second surface 232 during the focused light beam B1 irradiates the predetermined region Z1 a plurality of times.
Referring to fig. 2C and 2D, after the photosensitive material 103 is irradiated by the focused light beam B1, the photosensitive material 103 is developed to remove the modified portion 203C, thereby forming the photosensitive insulating layer 230 having the hole 233, wherein the hole 233 is formed by removing the modified portion 203C, so that the hole 233 is formed at the position where the focused light beam B1 irradiates the photosensitive material 103, i.e., the predetermined region Z1.
The photosensitive insulating layer 230 further has a first surface 231 and a second surface 232 opposite to each other, wherein the first circuit layer 110 is disposed on the first surface 231. The hole 233 is a through hole of the photosensitive insulating layer 230, so the hole 233 extends from the second surface 232 to the first surface 231 to expose the first pad 111, wherein the hole 233 may partially expose the first pad 111. In addition, the photosensitive insulating layer 230 may have an included angle TH2 between the hole wall 233w and the first pad 111, wherein the included angle TH2 may be between 15 degrees and 45 degrees, but not limited thereto.
Since the hole 233 is formed by removing the modified portion 203c, and the modified portion 203c is formed by irradiating the photosensitive material 103 with the focused light beam B1 for a plurality of times, wherein the position of the focal point F1 changes with each irradiation of the predetermined region Z1 by the focused light beam B1, the hole 233 has a significantly uneven aperture, and the hole wall 233w of the hole 233 is significantly uneven, as shown in fig. 2D.
Aperture 233 has an axis a23, and a portion of aperture wall 233w extends toward axis a23 to form a plurality of annular flanges 234. A plurality of concave cavities C23 exist between one of the annular flanges 234 and the first pad 111, and one of the concave cavities C23 is formed between two adjacent annular flanges 234. Taking fig. 2D as an example, the hole wall 233w forms three annular flanges 234, and three recessed cavities C23 are formed between the uppermost annular flange 234 and the first pad 111, wherein two recessed cavities C23 are respectively formed between two adjacent annular flanges 234.
As seen in fig. 2D, aperture wall 233w within each recessed cavity C23 has a concave curvature, and each annular flange 234 has edges 234e, wherein at least one edge 234e is formed between two adjacent recessed cavities C23. The minimum width W22 of annular flanges 234 is less than the maximum width W21 of recessed cavity C23 so that each annular flange 234 protrudes from aperture 233 at aperture wall 233W of recessed cavity C23. Additionally, the inner diameter R21 of the first port (not shown) and the inner diameter R22 of the second port (not shown) of the bore 233 can be within 10 microns. However, the difference between the inner diameter R21 and the inner diameter R22 is not limited to the above range.
Referring to fig. 2E, after the photosensitive insulating layer 230 is formed, an electroplating process is performed on the holes 233, wherein the electroplating process of the present embodiment is substantially the same as that of the previous embodiment. However, unlike the previous embodiment, the electroplating process in this embodiment can form the conductive layer 240 in the hole 233, and the conductive layer 240 entirely covers the hole wall 233w but does not fill the hole 233. For example, the conductive layer 240 may conformally (conformamally) cover the hole walls 233 w. In other words, the conductive layer 240 may be a hollow conductive post, and may be a conductive blind via.
Since the conductive layer 240 entirely covering the hole wall 233w does not fill the hole 233, the top of the conductive layer 240 in fig. 2E has an opening (not labeled), and the filling material 250 can be filled into the hole 233 from the opening on the top of the conductive layer 240, so that the filling material 250 can fill the hole 233, wherein the filling material 250 can be ink. After the filling material 250 fills the hole 233, the conductive layer 240 covers the filling material 250, as shown in fig. 2E.
Similar to the electroplating process in the foregoing embodiment, in the process of performing the electroplating process on the holes 233, a metal may be deposited on the second surface 232 of the photosensitive insulating layer 230 to form the second circuit layer 220 disposed on the second surface 232, wherein the second circuit layer 220 includes at least one second pad 221 and a plurality of traces 122, and the conductive layer 240 is connected between the first pad 111 and the second pad 221. The second pads 221 and the conductive layer 240 may be formed by the same electroplating process, and the second pads 221 and the conductive layer 240 may be integrally formed, so that there is no gap between the second pads 221 and the conductive layer 240.
Unlike the second pads 121 of the previous embodiments, the second pads 221 have openings (not labeled), wherein the second circuit layer 220 is connected to the openings at the top of the conductive layer 240, so that the filling material 250 can fill the holes 233 from the openings of the second circuit layer 220. To this end, a wiring board 200 including a photosensitive insulating layer 230, a first wiring layer 110, a second wiring layer 220, a conductive layer 240 and a filling material 250 is generally manufactured.
It should be noted that, in the embodiment shown in fig. 2E, the second circuit layer 220 includes a second pad 221 and a plurality of traces 122. However, in other embodiments, the second circuit layer 220 may also include a plurality of second pads 221 and one trace 122, so fig. 2E is only for illustration and does not limit the number of the second pads 221 and the traces 122 included in the circuit board 200.
In particular, in the embodiment shown in fig. 2E, the hole 233 is filled with the filling material 250 and the conductive layer 240, and no other insulating layer and no other circuit layer are formed above the second circuit layer 220. However, in other embodiments, an insulating layer and a circuit layer may be additionally formed on the second circuit layer 220, wherein the insulating layer may be the photosensitive insulating layer 230, and the hole 233 may be filled with the photosensitive insulating layer 230 and the conductive layer 240. In addition, the insulating layer and the circuit layer on the second circuit layer 220 may be formed by a build-up process or a lamination process. The method of additionally forming an insulating layer and a circuit layer on the second circuit layer 220 will be described in detail below by taking the build-up method as an example.
As with the method for forming the void 233, under the condition of omitting the filling material 250, another layer of the photosensitive material 103 may be formed on the second circuit layer 220 and the photosensitive insulating layer 230 in fig. 2E, not only covering the second circuit layer 220, but also filling the void 233. Thus, the hole 233 can be filled with the photosensitive insulating layer 230 and the conductive layer 240. Of course, the filling material 250 in fig. 2E may remain, so that the photosensitive material 103 may cover the second circuit layer 220 and the filling material 250, but not fill the hole 233.
Then, the focused light beam B1 is irradiated to the photosensitive material 103 a plurality of times. Thereafter, the photosensitive material 103 irradiated by the focused light beam B1 is developed to form the hole 233 on the second wiring layer 220. Then, an electroplating process is performed to form the conductive material 140 or the conductive layer 240 in the hole 233. Thus, the hole 233 in fig. 2E can be filled with the photosensitive insulating layer 230 and the conductive layer 240, and other insulating layers and circuit layers can be fabricated on the second circuit layer 220. In addition, in the method of additionally forming the insulating layer and the circuit layer on the second circuit layer 220, the focused beam B1 may only irradiate the photosensitive material 103 on the second circuit layer 220 once to form the hole 133 as shown in fig. 1B.
As in the previous embodiments, the photosensitive insulating layer 230 formed by the photosensitive material 103 may also have rigidity or flexibility, so the circuit board 200 may be a flexible circuit board or a rigid circuit board, or a flexible circuit substrate or a rigid circuit substrate in a flexible circuit board or a rigid circuit substrate. Under the condition that the photosensitive insulating layer 230 has flexibility, since the conductive layer 240 is a hollow conductive pillar, the conductive layer 240 contributes to increasing the flexibility of the circuit board 200, so that the circuit board 200 is a flexible circuit board with good flexibility or a flexible circuit substrate in a flexible and hard circuit board.
It should be noted that, in the embodiments shown in fig. 1A to fig. 2E, since the circuit substrate including the first circuit layer 110 and the insulating layer 190 may include two or more than three circuit layers, the circuit board 100 or 200 may be a multilayer circuit board having more than three circuit layers (including the first circuit layer 110 and the second circuit layer 120 or 220). However, in other embodiments, the circuit board 100 may be a double-sided circuit board (double-sided wiring board) with only two circuit layers. Accordingly, fig. 1A to 1C and fig. 2A to 2E are only for illustration and do not limit the kinds of both the circuit boards 100 and 200 and the number of circuit layers included.
Next, in the void 233 shown in fig. 2E, both the conductive layer 240 and the filling material 250 can be replaced by solid conductive pillars (like the conductive material 140 shown in fig. 1C). Conversely, in the cavity 133 shown in fig. 1C, the conductive material 140 can be replaced by a hollow conductive pillar and a filling material (such as the conductive layer 240 and the filling material 250 shown in fig. 2E), wherein the filling material can be the photosensitive material 103. In other words, the holes 133, 233, the conductive material 140, the conductive layer 240 and the filling material 250 can be applied to the circuit boards 100 and 200.
Fig. 3A to 3B are schematic cross-sectional views illustrating a method for forming a hole in a circuit board according to another embodiment of the invention. Referring to fig. 3A and 3B, the present embodiment is similar to the previous embodiments. For example, the hole forming method shown in fig. 3A and 3B is similar to the hole forming method shown in fig. 2A to 2E. Therefore, the main difference between the present embodiment and the previous embodiments is mainly described below, i.e., the hole forming method shown in fig. 3A and 3B is used to form solder mask openings, and the photosensitive insulating layer 330 shown in fig. 3A and 3B is a solder mask layer.
Referring to fig. 3A, after developing the photosensitive material 103 irradiated at least once by the focused light beam B1 (not shown in fig. 3A), a photosensitive insulating layer 330 having a hole 333 is formed as a solder mask, wherein the photosensitive insulating layer 330 further has a first surface 331 and a second surface 332 opposite to each other. The holes 333 expose the first pads 211 of the first circuit layer, and the first circuit layer is disposed on the first surface 331 of the photosensitive insulating layer 330. The photosensitive insulating layer 330 covers traces (not shown) of the first circuit layer, and partially covers the first pads 211, especially covers the peripheral portions of the first pads 211, wherein the first circuit layer (including the first pads 211) is an outermost circuit layer, and the first pads 211 are Solder-Mask Defined (SMD).
After the formation of the holes 333, a wiring board 300 including the photosensitive insulating layer 330 and the first wiring layer (including the first pads 211) is substantially completed and may be ready for downstream manufacturers, such as a packaging and testing facility. In addition, the circuit board 300 may further include an insulating layer 390, wherein the first circuit layer is formed on the insulating layer 390, and the circuit board 300 may further include at least one circuit layer under the insulating layer 190.
Fig. 3A illustrates that the focused light beam B1 irradiates the photosensitive material 103A plurality of times, and the hole 333 shown in fig. 3A is formed by irradiating the photosensitive material 103 at the same position (i.e., the predetermined region Z1) twice with the focused light beam B1 and performing the subsequent development. Therefore, a portion of the hole wall 333w of the hole 333 extends toward the axial center a33 of the hole 333 to form a plurality of annular flanges 334, as shown in fig. 3A.
A plurality of recessed cavities C33 are formed between the uppermost annular flange 334 and the first pad 211, and an upper recessed cavity C33 is formed between two adjacent annular flanges 334, wherein each annular flange 334 has a rim 334e, and a lower rim 334e is formed between two adjacent recessed cavities C33. From FIG. 3A, the minimum width of the annular flange 334 is clearly less than the maximum width of the recessed cavity C13.
The bore 333 may have an inner diameter R31 of the first port (not labeled) and an inner diameter R32 of the second port (not labeled) that are within 10 microns of each other. However, the difference between the inner diameter R31 and the inner diameter R32 is not limited to the above range. In addition, the photosensitive insulating layer 330 may have an included angle between the hole wall 333w and the first pad 211, which may be between 15 degrees and 45 degrees, as in the aforementioned embodiments of the included angle TH1 or TH2, but not limited thereto.
Referring to fig. 3B, next, a conductive material 340 is filled in the hole 333, wherein the conductive material 340 may be solder and may be filled in the hole 333 by printing or spraying. After the conductive material 340 fills the hole 333, the conductive material 340 may be heated to melt the conductive material 340. In this way, the circuit board 300 may further include a conductive material 340, wherein the conductive material 340 can completely fill the entire hole 333 and protrude from the second surface 332.
Fig. 4 is a schematic cross-sectional view of a wiring board of at least one embodiment of the invention. Referring to fig. 4, the circuit board 400 shown in fig. 4 is similar to the circuit board 300 shown in fig. 3B. For example, the circuit board 400 includes a photosensitive insulating layer 430, a first pad 211 and a conductive material 440, wherein the photosensitive insulating layer 430 has a hole 433 and a first surface 431 and a second surface 432 opposite to each other, and the holes 433 and 333 are formed by the same method.
One or more annular flanges 434 are formed on the hole wall 433w of the hole 433, and in fig. 4, a plurality of recessed cavities C43 (two recessed cavities C43 are illustrated in fig. 4) are formed between the uppermost annular flange 434 and the first pad 211, and the uppermost recessed cavity C43 is formed between two adjacent annular flanges 434. The conductive material 340 is solder and can completely fill the entire hole 333, wherein the conductive material 340 protrudes from the second surface 432. Furthermore, in other embodiments, the wiring board 400 may not include the conductive material 340, i.e., the conductive material 340 in fig. 4 may be omitted.
However, unlike the circuit board 300, in the circuit board 400, the hole 433 of the photosensitive insulating layer 430 has a larger aperture than the width of the first pad 211, so that the photosensitive insulating layer 430 does not cover the first pad 211 and does not contact the first pad 211. Thus, unlike the first pads 211 of the Solder Mask-Defined (SMD) shown in fig. 3B, the first pads 211 shown in fig. 4 are Non-Solder Mask-Defined (NSMD).
It should be emphasized that in the above embodiments, the number of holes (e.g., the holes 133, 233, 333, or 433) shown in each figure is only one. However, in other embodiments, the number of the holes of the circuit board may be multiple. Therefore, the circuit boards 100 to 400 disclosed in the above embodiments may each have a plurality of holes, and the number of the holes of the circuit boards 100 to 400 is not limited by the above drawings.
In summary, with the annular flange and the recessed cavity, a conductive material (e.g., a conductive post or solder) can be embedded in the hole, so as to be firmly fixed in the hole. Therefore, the photosensitive insulating layer disclosed in at least one embodiment of the present invention can help fix the conductive material in the hole, so as to reduce the probability of cracks occurring between the conductive material and the first pad due to separation, thereby improving reliability. Therefore, compared with the conventional common circuit board, the circuit board of at least one embodiment of the invention has better reliability.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (16)

1. A circuit board, comprising:
the photosensitive insulating layer is provided with a hole and a first surface and a second surface which are opposite to each other, wherein the hole is provided with a first port formed on the first surface, a second port formed on the second surface, a shaft center and a hole wall surrounding the shaft center, and part of the hole wall extends towards the shaft center to form at least one annular flange; and
the first circuit layer is arranged on the first surface and comprises a first connecting pad, wherein the hole exposes the first connecting pad, at least one concave cavity is reserved between the at least one annular flange and the first connecting pad, and the minimum width of the at least one annular flange is smaller than the maximum width of the at least one concave cavity.
2. The cord plate of claim 1, wherein the difference between the inner diameter of the first port and the inner diameter of the second port is within 10 microns.
3. The circuit board of claim 1, wherein the annular flange is connected to the first pad, and the annular flange and the recessed cavity form a double curved surface.
4. The circuit board of claim 1, wherein a portion of the hole wall extends toward the axis to form a plurality of annular flanges, and wherein a plurality of recessed cavities exist between the annular flanges and the first pads, wherein the recessed cavities are formed between two adjacent annular flanges.
5. A wiring board according to claim 4, wherein the hole wall in each recessed cavity has a concave curved surface, and each annular flange has a rim, wherein at least one rim is formed between two adjacent recessed cavities.
6. The wiring board of claim 1, further comprising:
and the conductive material is filled in the hole and the concave cavity and is connected with the first connecting pad.
7. The wiring board of claim 6, wherein the conductive material protrudes from the second surface.
8. The circuit board of claim 6, wherein the photosensitive insulating layer does not contact the first pad.
9. The wiring board of claim 6, further comprising:
and the second circuit layer is arranged on the second surface and comprises a second connecting pad, wherein the conductive material is connected between the first connecting pad and the second connecting pad.
10. The circuit board of claim 1, further comprising a conductive layer, wherein the conductive layer covers the hole wall of the hole in a full-face manner, and the conductive layer does not fill the hole.
11. The circuit board of claim 10, further comprising a filler material, wherein the filler material fills the hole and the conductive layer covers the filler material.
12. The circuit board of claim 1, wherein the photosensitive insulating layer has an included angle between the hole wall and the first pad, wherein the included angle is between 15 degrees and 45 degrees.
13. A method for forming a hole in a circuit board, comprising:
providing a photosensitive material and a first circuit layer, wherein the photosensitive material covers the first circuit layer, and the first circuit layer comprises a first connecting pad;
irradiating a predetermined region of the photosensitive material with a focused beam at least once, wherein a focal point of the focused beam is maintained above the first pad during the irradiation of the predetermined region with the focused beam; and
after the focused light beam irradiates the photosensitive material, the photosensitive material is developed to form a photosensitive insulating layer having holes.
14. The method of claim 13, wherein the focused beam irradiates the predetermined area multiple times, and when the focused beam irradiates the predetermined area n times, the distance between the focal point and the first pad is d (n), where n is a positive integer; when the predetermined area is irradiated by the focused light beam for the (n +1) th time, the distance between the focal point and the first pad is D (n +1), where D (n) ≦ D (n + 1).
15. The method of claim 13, further comprising electroplating the hole after developing the photosensitive material.
16. The method of claim 13, further comprising filling a conductive material in the hole after developing the photosensitive material.
CN202010849277.7A 2020-08-21 2020-08-21 Circuit board and method for forming holes thereof Pending CN114080100A (en)

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Application Number Priority Date Filing Date Title
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW333742B (en) * 1995-08-08 1998-06-11 Ibm The improving & producing method for PCB with migration resistance
JP2005064259A (en) * 2003-08-13 2005-03-10 Cmk Corp Printed wiring board manufacturing method
CN101785103A (en) * 2007-07-05 2010-07-21 Aac微技术有限公司 Low resistance through-wafer via
KR20140021914A (en) * 2012-08-13 2014-02-21 삼성전기주식회사 Method of manufacturing a printed circuit board
CN103909351A (en) * 2013-01-04 2014-07-09 欣兴电子股份有限公司 Circuit board and laser drilling method for the same
CN105744739A (en) * 2014-12-26 2016-07-06 三星电机株式会社 Printed Circuit Board And Method Of Manufacturing The Same
US20200251351A1 (en) * 2019-01-31 2020-08-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Manufacturing Trapezoidal Through-Hole in Component Carrier Material

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW333742B (en) * 1995-08-08 1998-06-11 Ibm The improving & producing method for PCB with migration resistance
JP2005064259A (en) * 2003-08-13 2005-03-10 Cmk Corp Printed wiring board manufacturing method
CN101785103A (en) * 2007-07-05 2010-07-21 Aac微技术有限公司 Low resistance through-wafer via
KR20140021914A (en) * 2012-08-13 2014-02-21 삼성전기주식회사 Method of manufacturing a printed circuit board
CN103909351A (en) * 2013-01-04 2014-07-09 欣兴电子股份有限公司 Circuit board and laser drilling method for the same
CN105744739A (en) * 2014-12-26 2016-07-06 三星电机株式会社 Printed Circuit Board And Method Of Manufacturing The Same
US20200251351A1 (en) * 2019-01-31 2020-08-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Manufacturing Trapezoidal Through-Hole in Component Carrier Material

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