CN114078974A - SiO growth by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer - Google Patents

SiO growth by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer Download PDF

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CN114078974A
CN114078974A CN202010848774.5A CN202010848774A CN114078974A CN 114078974 A CN114078974 A CN 114078974A CN 202010848774 A CN202010848774 A CN 202010848774A CN 114078974 A CN114078974 A CN 114078974A
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sio
dielectric layer
gate dielectric
silicon nano
high temperature
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CN114078974B (en
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秦国轩
杨晓东
魏印龙
刘家立
魏俊青
游子璇
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Tianjin University
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors

Abstract

The invention discloses a method for growing SiO by high temperature2The preparation method of the silicon nanometer flexible thin film transistor of the gate dielectric layer sequentially comprises the steps of plating an ITO bottom gate electrode on the surface of a PET flexible plastic substrate, manufacturing a double-layer silicon laminating body formed by a porous silicon nanometer thin film and an SOI silicon substrate by adopting an SOI material, and manufacturing SiO grown at high temperature2The gate dielectric layer is connected with the surface of the hard silicon substrate after being turned over, N-type ions are injected into the surface of the doped porous silicon nano film to manufacture a source electrode and a drain electrode metal titanium electrode, and SiO grown at high temperature is utilized2The grid dielectric layer is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode; the invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The silicon nano flexible thin film transistor of the gate dielectric layer has the characteristics of good electrical property and high stability.

Description

SiO growth by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer
Technical Field
The invention relates to a method for growing SiO by high temperature2A preparation method of a silicon nanometer flexible thin film transistor of a gate dielectric layer is provided.
Background
Common SiO for traditional hard IC transistor2The gate dielectric layer is mostly prepared on the silicon single crystal substrate by a high temperature growth method, and the temperature is usually required to be more than 1000 ℃. The silicon nano flexible thin film transistor is mainly used in the design and manufacture of flexible integrated circuits, and due to the requirement of flexibility, the silicon nano flexible thin film transistor needs to be prepared on a flexible plastic substrate, but the maximum temperature resistance of the flexible plastic substrate is only 200 ℃, so that SiO is generated2The preparation of the silicon nano flexible thin film transistor of the gate dielectric layer can only grow SiO on the surface of the bottom gate electrode on the surface of the flexible substrate at low temperature2And a gate dielectric layer. SiO due to low temperature growth2The gate dielectric layer is compared with the SiO grown at high temperature2The gate dielectric layer has poor quality in the aspects of compactness, performance stability, breakdown voltage and the like, so that SiO grows at low temperature2Silicon nanometer flexible thin film transistor of grid dielectric layer and grid dielectric layer unit area capacitance less than 10nF/cm2The starting voltage is more than or equal to 5V, and the grid leakage current is more than or equal to 10-6A. The electron mobility at room temperature is less than or equal to 10cm2VS, service life less than 2000min, poor electrical property and low stability. Thus utilizing high temperature grown SiO2The preparation of silicon nano flexible thin film transistors by using gate dielectric layers is a development direction.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for growing SiO by using high temperature2A preparation method of a silicon nanometer flexible thin film transistor of a gate dielectric layer is provided.
The invention relates to a method for growing SiO by high temperature2The technical scheme of the preparation method of the silicon nano flexible thin film transistor of the gate dielectric layer is realized as follows:
growth of S by high temperatureiO2The preparation method of the silicon nanometer flexible thin film transistor of the gate dielectric layer sequentially comprises the following steps:
ITO (indium tin oxide) bottom grid electrode plated on surface of I, PET (polyethylene terephthalate) flexible plastic substrate
(1) Pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, putting a PET flexible plastic substrate with the length of 2cm, the width of 2cm and the thickness of 175 mu m into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
(2) pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the PET flexible plastic substrate cleaned in the step I (1), putting the PET flexible plastic substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
(3) taking out the PET flexible plastic substrate cleaned in the step I (2), washing with deionized water, drying by using an air gun, and putting the PET flexible plastic substrate into a clean 250ml polypropylene plastic beaker for later use;
(4) plating an ITO bottom gate electrode with the thickness of 200nm on the surface of the PET flexible plastic substrate in the step I (3) by adopting vacuum magnetron sputtering coating equipment under the room-temperature vacuum condition;
II, preparing a double-layer silicon laminating body consisting of the porous silicon nano film and the SOI silicon substrate by adopting the SOI material
(1) 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the insulator layer SiO with the length of 1cm, the width of 1cm, the thickness of 190-210 nm of the silicon nano film and the thickness of2Putting the SOI material with the thickness of 430-470 nm and the thickness of 660-690 mu m of the silicon substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
(2) pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the SOI material cleaned in the step (1) and putting the SOI material into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
(3) taking out the SOI material cleaned in the step (2), washing with deionized water, drying by using an air gun, and putting the SOI material into a clean 250ml polypropylene plastic beaker for later use;
(4) coating 1813 positive photoresist on the surface of the SOI material silicon nano film in the step II (3), and throwing and uniformly distributing the 1813 positive photoresist by sequentially setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
(5) baking and heating the SOI material silicon nano film prepared in the step II (4) for 90s at 115 ℃ by using a heating plate;
(6) aligning and photoetching 222 transverse square hole patterns and 222 longitudinal square hole patterns of 5 multiplied by 5 mu m which are uniformly distributed and arranged with the transverse spacing and the longitudinal spacing of 40 mu m on the surface of the SOI material silicon nano film manufactured in the step II (5) by using a photoetching machine and a mask plate manufactured according to the photoetching pattern, and forming 222 transverse square hole patterns and 222 longitudinal square hole patterns of 5 multiplied by 5 mu m which are uniformly distributed and arranged with the transverse spacing and the longitudinal spacing of 40 mu m on the surface of the SOI material silicon nano film after developing;
(7) etching for 5-10 min in a vacuum environment by adopting a reactive ion etching mode, and removing silicon in a square hole pattern of 5 multiplied by 5 microns on the surface of the SOI material silicon nano-film prepared in the step II (6) to form a porous silicon nano-film;
(8) firstly, 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, the porous silicon nano-film SOI material prepared in the step B (7) is put into the acetone solution to be cleaned for 5-10 min, and the residual 1813 positive photoresist on the surface of the porous silicon nano-film is removed; then pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the porous silicon nano-film SOI material cleaned by the acetone solution, and putting the porous silicon nano-film SOI material into the isopropanol solution for cleaning for 5-10 min; finally, taking out the porous silicon nano-film SOI material cleaned by the isopropanol solution, washing the material by deionized water, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
(9) pouring 50ml of hydrofluoric acid aqueous solution with the volume ratio of deionized water to hydrofluoric acid being 3:1 into a 250ml polypropylene plastic beaker, putting the porous silicon nano-film SOI material prepared in the step II (8) into the polypropylene plastic beaker, and after 2 hours, putting an insulator layer SiO in the SOI material2Is removed by etching to remove SiO in the insulator layer2The porous silicon nano film and the SOI silicon substrate depend on Van der Waals forceForming a double-layer silicon attaching body by attraction; taking out the double-layer silicon laminating body, washing the double-layer silicon laminating body by deionized water, and putting the double-layer silicon laminating body into a clean 250ml polypropylene plastic beaker for later use;
III, preparing SiO by high-temperature growth2The gate dielectric layer is connected with the surface of the hard silicon substrate after being turned over
(1) Putting the double-layer silicon laminating body manufactured in the step II (9) into a high-temperature heating furnace at 1100 ℃, introducing oxygen with the flow of 1000sccm for high-temperature oxidation for 45min, and forming SiO with the thickness of 30-40 nm and grown at high temperature on the surface of the porous silicon nano film2A gate dielectric layer;
(2) coating SU8 glue on the surface of a hard silicon substrate with the thickness of 290-310 mu m, and uniformly throwing the SU8 glue at the rotating speed of 500rpm, the rotating time of 10s, the rotating speed of 4000rpm and the rotating time of 30s of a spin coater;
(3) and growing SiO on the surface of the double-layer silicon laminating body porous silicon nano film prepared in the step III (1) by utilizing high temperature2The gate dielectric layer is turned over to make the SiO grown at high temperature2The gate dielectric layer is connected with the surface of the hard silicon substrate which is prepared in the step III (2) and coated with SU8 glue on the surface, and the SU8 glue and the SiO grown at high temperature are utilized2The adhesive force between the gate dielectric layers is larger than the Van der Waals force between the SOI silicon substrate and the porous silicon nano film in the double-layer silicon laminating body, so that the SOI silicon substrate and the porous silicon nano film in the double-layer silicon laminating body are separated, and SiO grown at high temperature is utilized2The gate dielectric layer and the upper porous silicon nano-film are transferred to the surface of the hard silicon substrate to realize the porous silicon nano-film and the SiO grown by high temperature2Turning the upper and lower positions of the gate dielectric layer;
IV, N type ion implantation doping porous silicon nano film surface making source and drain electrode metal titanium electrode
(1) Connecting SiO grown at high temperature on the surface of the hard silicon substrate in the step III (3)2Coating 1813 positive photoresist on the surface of the porous silicon nano film above the gate dielectric layer, and uniformly throwing the 1813 positive photoresist by setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
(2) and (3) connecting the surface of the hard silicon substrate in the step (IV) (1) by using a heating plateHigh temperature grown SiO2Baking and heating the porous silicon nano film above the gate dielectric layer for 90s at 115 ℃;
(3) connecting the surface of the hard silicon substrate in the step IV (2) with SiO grown at high temperature by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Photoetching the surface of the porous silicon nano film above the gate dielectric layer to form an N-type heavily doped region pattern, carrying out N-type ion implantation by using ion implantation equipment after developing, wherein the implantation energy is 40Kev, and the dosage is 4 multiplied by 1015cm-2Generating an N-type heavily doped region, and performing rapid thermal annealing at the temperature of 750 ℃ for 10s, wherein the undoped region comprises an undoped region at the middle position and undoped regions at the two sides, the length and the width of the undoped region at the middle position are respectively 10-50 microns and 50-500 microns, the length and the width of the undoped region at the two sides are respectively 10-50 microns and 50-500 microns, and the N-type heavily doped region is positioned between the undoped region at the middle position and the undoped regions at the two sides and has the length and the width of 10-50 microns and 50-500 microns;
(4) pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, and connecting the surface of the hard silicon substrate in the step IV (3) with SiO grown at high temperature2Placing the gate dielectric layer and the upper N-type ion implantation doped porous silicon nano-film material into the polypropylene plastic beaker for 2min, and removing 1813 positive photoresist on the surface of the N-type ion implantation doped porous silicon nano-film; the surface of the hard silicon substrate cleaned by the acetone solution is connected with SiO grown at high temperature2Taking out the grid dielectric layer 4 and the upper N-type ion implantation doped porous silicon nano film 3 material, taking out deionized water, washing, drying by using an air gun, and putting into a clean 250ml polypropylene plastic beaker for later use;
(5) connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step IV (4)2Coating 5214 negative photoresist on the surface of the N-type ion implantation doped porous silicon nano film above the gate dielectric layer, and uniformly throwing the 5214 negative photoresist at the rotating speed of 500rpm, the rotating time of 10s, the rotating speed of 4000rpm and the rotating time of 30s of a spin coater;
(6) and (3) connecting the surface of the hard silicon substrate obtained in the step (IV) (5) with SiO grown at high temperature by using a heating plate2N type above gate dielectric layerIon implantation is carried out on the doped porous silicon nano film, and the film is baked and heated for 90s at 115 ℃;
(7) and connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step IV (6) by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Injecting N-type ions above the gate dielectric layer into undoped regions at two sides of the doped porous silicon nano-film and above the adjacent N-type heavily doped regions, and photoetching the undoped regions at the two sides and the N-type heavily doped regions to form a source electrode pattern and a drain electrode pattern, wherein the lengths and the widths of the undoped regions at the two sides and the N-type heavily doped regions are respectively 10-50 microns and 50-500 microns, and the lengths of the source electrode pattern and the drain electrode pattern covered in the N-type heavily doped regions are both 5-25 microns;
(8) and (3) connecting the surface of the hard silicon substrate obtained in the step (IV) (7) with SiO grown at high temperature by using a heating plate2Injecting N-type ions with source electrode patterns and drain electrode patterns on the upper surface of the gate dielectric layer into the doped porous silicon nano film, and baking and heating the doped porous silicon nano film for 90s at 115 ℃;
(9) connecting the surface of the hard silicon substrate obtained in the step IV (8) with SiO grown at high temperature2Injecting N-type ions with source electrode patterns and drain electrode patterns on the upper surface of the gate dielectric layer into the doped porous silicon nano film and exposing the doped porous silicon nano film on a photoetching machine for 70 s;
(10) IV (9) connecting the surface of the hard silicon substrate with SiO grown at high temperature2After an N-type ion injection doped porous silicon nano film with a source electrode pattern and a drain electrode pattern etched on the surface above a gate dielectric layer is developed, evaporating a metal titanium electrode with the height of 0.5-20 nm above an undoped region and an N-type heavily doped region of two side positions of a source electrode and a drain electrode respectively by using vacuum electron beam coating equipment, then putting the metal titanium electrode into a 250ml polypropylene plastic beaker, pouring 200ml of acetone solution for soaking for 15min, washing 5214 negative photoresist and redundant metal titanium, and forming metal titanium electrodes of the source electrode and the drain electrode with the length of 10-50 mu m, the width of 50-500 mu m and the height of 0.5-20 nm;
v, SiO grown by high temperature2The grid dielectric layer is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode
(1) Pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, and connecting the surface of the hard silicon substrate in the step IV (10) by utilizing high temperatureGrown SiO2Injecting N-type ions of the gate dielectric layer and the titanium electrode with the source electrode and the drain electrode evaporated on the upper surface into the doped porous silicon nano film material, putting the material into the polypropylene plastic beaker for cleaning for 5-10 min, and putting the surface of the hard silicon substrate and the SiO grown at high temperature into the beaker2Cleaning the gate dielectric layer with SU8 glue, taking out, blowing with air gun, and injecting N-type ions of the hard silicon substrate and the metal titanium electrode with source and drain on the upper surface into the lower surface of the doped porous silicon nano film by using SiO grown at high temperature2Integrally separating the gate dielectric layers;
(2) injecting N-type ions of the titanium electrode with source and drain metals on the upper surface into the SiO grown on the lower surface of the doped porous silicon nano-film at high temperature under the action of electrostatic force adsorption2The gate dielectric layer is connected above the ITO bottom gate electrode to finish the growth of SiO by high temperature2And preparing the silicon nano flexible thin film transistor of the gate dielectric layer.
The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The silicon nano flexible thin film transistor of the gate dielectric layer has the characteristics of good electrical property and high stability.
Drawings
The invention is further described below with reference to the accompanying drawings and examples.
FIG. 1 is SiO2A silicon nano flexible thin film transistor profile of the gate dielectric layer;
in the figure: SiO of source 1, drain 2, silicon nano film 3 grown by high temperature2Undoped regions 7-2N type heavily doped regions 8 at two sides of undoped region 7-1 in middle of undoped region 7 of gate dielectric layer 4 ITO bottom gate electrode 5 PET flexible plastic substrate 6
FIG. 2 shows the growth of SiO by high temperature2A process flow chart of a preparation method of a silicon nano flexible thin film transistor of a gate dielectric layer.
Detailed Description
Example 1
1. Sources of materials and equipment
(1) Source of material
PET flexible plastic substrate 6: PET refers to polyethylene terephthalate, a commercially available product;
ITO bottom gate electrode 5: ITO refers to indium tin oxide, commercially available;
SOI material: SOI refers to silicon on insulator, commercially available;
oxygen: commercial product, 99.9% purity;
metal titanium: commercial product, 99.98% purity;
a hard silicon substrate: commercial product, 99.9999999% purity;
hydrofluoric acid: a commercial product, 30% mass percentage concentration;
acetone solution: commercial product, 99% mass percentage concentration;
isopropanol solution: commercial product, 95% mass percentage concentration;
deionized water: a commercially available product;
SU8 glue: a commercially available product;
1813 positive photoresist: a commercially available product;
5214 negative photoresist: a commercially available product;
heat release tape: a commercially available product;
250ml polypropylene plastic beaker: a commercially available product;
(2) source of equipment
An ultrasonic cleaner: commercial product, YQ-620C;
an air gun: a commercially available product;
heating plate: a commercially available product;
a spin coater: commercial products, KW-4C;
a photoetching machine: a commercially available product;
mask plate: a commercially available product;
high-temperature heating furnace: a commercially available product;
the reactive ion etching equipment comprises: a commercially available product;
an ion implantation apparatus: a commercially available product;
and (3) thermal annealing equipment: a commercially available product;
vacuum magnetron sputtering coating equipment: commercial product, JCPY 500;
vacuum electron beam coating equipment: commercially available product, VZZS-650.
2. The invention relates to a method for growing SiO by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer
As shown in FIGS. 1 and 2, a method for growing SiO by high temperature2The preparation method of the silicon nanometer flexible thin film transistor of the gate dielectric layer sequentially comprises the following steps:
ITO bottom grid electrode 5 is plated on surface of flexible plastic substrate 6 of PET (polyethylene terephthalate)
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, a PET flexible plastic substrate 6 with the length of 2cm, the width of 2cm and the thickness of 175 mu m is placed into the polypropylene plastic beaker, and the polypropylene plastic beaker is placed into an ultrasonic cleaner for cleaning for 5 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the PET flexible plastic substrate 6 cleaned in the step (I) and putting the PET flexible plastic substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5 min;
taking out the cleaned PET flexible plastic substrate 6 obtained in the step (I), washing with deionized water, drying with an air gun, and putting the PET flexible plastic substrate 6 into a clean 250ml polypropylene plastic beaker for later use;
plating an ITO bottom gate electrode 5 with the thickness of 200nm on the surface of the PET flexible plastic substrate 6 in the step (I) under the room temperature vacuum condition by adopting vacuum magnetron sputtering coating equipment;
(II) preparing a double-layer silicon laminating body consisting of the porous silicon nano-film 3 and the SOI silicon substrate by adopting the SOI material
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the silicon nano film 3 with the length of 1cm and the width of 1cm and the thickness of 190nm and the insulator layer SiO are poured into the beaker2Putting the SOI material with the thickness of 430nm and the thickness of the silicon substrate of 660 mu m into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the SOI material cleaned in the step (II) and putting the SOI material into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5 min;
taking out the cleaned SOI material obtained in the step (II), washing with deionized water, drying with an air gun, and putting the SOI material into a clean 250ml polypropylene plastic beaker for later use;
fourthly, coating 1813 positive photoresist on the surface of the silicon nano film 3 of the SOI material obtained in the step (II), and throwing and uniformly stirring the 1813 positive photoresist by sequentially setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
fifthly, baking and heating the SOI material silicon nano film 3 prepared in the step (II) for 90s at 115 ℃ by using a heating plate;
sixthly, using a photoetching machine and a mask plate manufactured according to photoetching patterns, carrying out alignment photoetching on the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the transverse spacing and the longitudinal spacing of 40 mu m which are uniformly distributed and arranged on the surface of the SOI material silicon nano film 3 manufactured in the step (II), and forming the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the longitudinal 5 mu m which are uniformly distributed and arranged with the transverse spacing and the longitudinal spacing of 40 mu m on the surface of the SOI material silicon nano film 3 after developing;
seventhly, etching for 5min in a vacuum environment by adopting a reactive ion etching mode, and removing silicon in a square hole pattern of 5 multiplied by 5 mu m on the surface of the SOI material silicon nano film 3 manufactured in the step (II) to form a porous silicon nano film 3;
eighthly, pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, putting the porous silicon nano-film 3SOI material prepared in the step (B) into the acetone solution, cleaning for 5min, and removing the residual 1813 positive photoresist on the surface of the porous silicon nano-film 3; then pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the porous silicon nano-film 3SOI material cleaned by the acetone solution, and putting the material into the isopropanol solution for cleaning for 5 min; finally, taking out the porous silicon nano-film 3SOI material cleaned by the isopropanol solution, washing the material by deionized water, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
ninthly, 50ml of hydrofluoric acid aqueous solution with the volume ratio of the deionized water to the hydrofluoric acid being 3:1 is poured into a 250ml polypropylene plastic beaker, and the step (II)) The porous silicon nano-film 3SOI material is put into the polypropylene plastic beaker, and after 2 hours, the insulator layer SiO in the porous silicon nano-film 3SOI material is2Is removed by etching to remove SiO in the insulator layer2The porous silicon nano film 3 and the SOI silicon substrate form a double-layer silicon laminating body by virtue of van der Waals attraction; taking out the double-layer silicon laminating body, washing the double-layer silicon laminating body by deionized water, and putting the double-layer silicon laminating body into a clean 250ml polypropylene plastic beaker for later use;
(III) production of SiO by high-temperature growth2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate after being turned over
Putting the double-layer silicon attaching body manufactured in the step (II) into a 1100 ℃ high-temperature heating furnace, introducing oxygen with the flow of 1000sccm, and oxidizing for 45min at high temperature to form SiO with the thickness of 30nm and grown at high temperature on the surface of the porous silicon nano film 32A gate dielectric layer 4;
secondly, coating SU8 glue on the surface of a hard silicon substrate with the thickness of 290 mu m, and uniformly throwing the SU8 glue by setting the rotating speed of a glue mixer to be 500rpm, the rotating time to be 10s, the rotating speed to be 4000rpm and the rotating time to be 30 s;
thirdly, growing SiO on the surface of the double-layer silicon laminating body porous silicon nano film 3 manufactured in the step (III) by utilizing high temperature2The gate dielectric layer 4 is turned over to make the SiO grown at high temperature2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate which is prepared in the step (III) and coated with SU8 glue on the surface, and the SU8 glue and the SiO grown at high temperature are used for connecting2The adhesive force between the gate dielectric layers 4 is larger than the Van der Waals force between the SOI silicon substrate and the porous silicon nano film 3 in the double-layer silicon laminating body, so that the SOI silicon substrate and the porous silicon nano film 3 in the double-layer silicon laminating body are separated, and SiO grown at high temperature is used2The gate dielectric layer 4 and the upper porous silicon nano-film 3 are transferred to the surface of the hard silicon substrate to realize the porous silicon nano-film 3 and the SiO grown by high temperature2Turning the upper position and the lower position of the gate dielectric layer 4;
(IV) manufacturing metal titanium electrodes of a source electrode 1 and a drain electrode 2 on the surface of the N-type ion implantation doped porous silicon nano film 3
Connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step (III)2Gate dielectric layerCoating 1813 positive photoresist on the surface of the porous silicon nano film 3 above the photoresist layer 4, and uniformly throwing the 1813 positive photoresist by setting the rotating speed of a spin coater to be 500rpm, the rotating time to be 10s, the rotating speed to be 4000rpm and the rotating time to be 30 s;
secondly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The porous silicon nano film 3 above the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
thirdly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Photoetching the surface of the porous silicon nano film 3 above the gate dielectric layer 4 to form an N-type heavily doped region 8 pattern, carrying out N-type ion implantation by using ion implantation equipment after developing, wherein the implantation energy is 40Kev, and the dosage is 4 multiplied by 1015cm-2Generating an N-type heavily doped region 8, and performing rapid thermal annealing at the temperature of 750 ℃ for 10s, wherein the undoped region 7 comprises an undoped region 7-1 at the middle position and undoped regions 7-2 at the two sides, the length and the width of the undoped region 7-1 at the middle position are respectively 10 micrometers and 50 micrometers, the length and the width of the undoped region 7-2 at the two sides are respectively 10 micrometers and 50 micrometers, and the N-type heavily doped region 8 is positioned between the undoped region 7-1 at the middle position and the undoped regions 7-2 at the two sides and has the length and the width of 10 micrometers and 50 micrometers;
fourthly, 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the surface of the hard silicon substrate obtained in the step IV is connected with SiO growing at high temperature2Placing the gate dielectric layer 4 and the upper N-type ion implantation doped porous silicon nano-film 3 material into the polypropylene plastic beaker for 2min, and removing 1813 positive photoresist on the surface of the N-type ion implantation doped silicon nano-film 3; the surface of the hard silicon substrate cleaned by the acetone solution is connected with SiO grown at high temperature2Injecting the grid dielectric layer 4 and the upper N-type ion into the doped porous silicon nano film 3 material, taking out the material, washing the material with deionized water, drying the material with an air gun, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
fifthly, connecting SiO grown at high temperature on the surface of the hard silicon substrate in the step (IV)25214 negative photoresist is coated on the surface of the N-type ion implantation doped porous silicon nano film 3 above the gate dielectric layer 4Setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30s, and uniformly throwing the 5214 negative photoresist;
sixthly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a heating plate2Injecting N-type ions above the gate dielectric layer 4 into the doped porous silicon nano film 3, and baking and heating for 90s at 115 ℃;
seventhly, connecting SiO grown at high temperature to the surface of the hard silicon substrate in step (IV) by using a photoetching machine and a mask plate manufactured according to photoetching patterns2N-type ions are injected into undoped regions 7-2 at two sides of the doped porous silicon nano film 3 above the gate dielectric layer 4 and above the adjacent N-type heavily doped region 8, photoetching is carried out to cover the N-type heavily doped region 8 and the undoped regions 7-2 at two sides with the length and width respectively being 10 mu m and 50 mu m to form a source electrode 1 pattern and a drain electrode 2 pattern, and the lengths of the source electrode 1 pattern and the drain electrode 2 pattern covering the N-type heavily doped region 8 are both 5 mu m;
eighthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern on the upper surface of the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
ninthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown by high temperature2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern engraved on the surface above the gate dielectric layer 4 is exposed and exploded on a photoetching machine for 70 s;
connection of surface of hard silicon substrate in R and step (IV) by using high-temperature grown SiO2After an N-type ion implantation doped porous silicon nano film 3 with a source electrode 1 pattern and a drain electrode 2 pattern etched on the surface above a gate dielectric layer 4 is developed, the source electrode 1 and the drain electrode 2 are respectively positioned above an undoped region 7-2 and an N-type heavily doped region 8 at two sides, the height of a metal titanium electrode is 0.5nm by adopting vacuum electron beam coating equipment through evaporation, then the metal titanium electrode is placed into a 250ml polypropylene plastic beaker, 200ml of acetone solution is poured into the polypropylene plastic beaker for soaking for 15min, 5214 negative photoresist and redundant metal titanium are washed off, and the metal titanium electrodes of the source electrode 1 and the drain electrode 2 with the length of 10 mu m, the width of 50 mu m and the height of 0.5nm are formed;
(V) SiO grown by high temperature2The grid dielectric layer 4 is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode 5
Adding 50ml acetone solution into 250ml polypropylene plastic beaker, connecting SiO grown at high temperature to surface of hard silicon substrate in step (IV)2Injecting N-type ions of the gate dielectric layer 4 and the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface into the doped porous silicon nano-film 3 material, putting the material into the polypropylene plastic beaker for cleaning for 5min, and putting the surface of the hard silicon substrate and the SiO grown at high temperature into the beaker2Cleaning the gate dielectric layer 4 by using SU8 glue, taking out, drying by using an air gun, and injecting N-type ions of the hard silicon substrate and the metal titanium electrodes with the source electrode 1 and the drain electrode 2 on the upper surface into the lower surface of the doped porous silicon nano film 3 by using SiO grown at high temperature2The gate dielectric layer 4 is integrally separated;
secondly, by means of electrostatic force adsorption, N-type ions of the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface are injected into the SiO grown on the lower surface of the doped porous silicon nano film 3 by high temperature2The gate dielectric layer 4 is connected above the ITO bottom gate electrode 5 to finish the high-temperature growth of SiO2And preparing the silicon nano flexible thin film transistor of the gate dielectric layer.
3. The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The performance of the silicon nano flexible thin film transistor of the gate dielectric layer is shown in Table 1
TABLE 1 growth of SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
Figure BDA0002644029490000141
Example 2
1. Sources of materials and equipment
(1) Source of material
PET flexible plastic substrate 6: the same as example 1;
ITO bottom gate electrode 5: the same as example 1;
SOI material: SOI refers to silicon on insulator, commercially available;
oxygen: the same as example 1;
metal titanium: the same as example 1;
a hard silicon substrate: the same as example 1;
hydrofluoric acid: the same as example 1;
acetone solution: the same as example 1;
isopropanol solution: the same as example 1;
deionized water: the same as example 1;
SU8 glue: the same as example 1;
1813 positive photoresist: the same as example 1;
5214 negative photoresist: the same as example 1;
heat release tape: the same as example 1;
250ml polypropylene plastic beaker: the same as example 1;
(2) source of equipment
An ultrasonic cleaner: the same as example 1;
an air gun: the same as example 1;
heating plate: the same as example 1;
a spin coater: the same as example 1;
a photoetching machine: the same as example 1;
mask plate: the same as example 1;
high-temperature heating furnace: the same as example 1;
the reactive ion etching equipment comprises: the same as example 1;
an ion implantation apparatus: the same as example 1;
and (3) thermal annealing equipment: the same as example 1;
vacuum magnetron sputtering coating equipment: the same as example 1;
vacuum electron beam coating equipment: the same as in example 1.
2. The invention relates to a method for growing SiO by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer
As shown in FIGS. 1 and 2, a method for growing SiO by high temperature2The preparation method of the silicon nanometer flexible thin film transistor of the gate dielectric layer sequentially comprises the following steps:
ITO bottom grid electrode 5 is plated on surface of flexible plastic substrate 6 of PET (polyethylene terephthalate)
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, a PET flexible plastic substrate 6 with the length of 2cm, the width of 2cm and the thickness of 175 mu m is placed into the polypropylene plastic beaker, and the polypropylene plastic beaker is placed into an ultrasonic cleaner for cleaning for 8 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the PET flexible plastic substrate 6 cleaned in the step (I) and putting the PET flexible plastic substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 8 min;
taking out the cleaned PET flexible plastic substrate 6 obtained in the step (I), washing with deionized water, drying with an air gun, and putting the PET flexible plastic substrate 6 into a clean 250ml polypropylene plastic beaker for later use;
plating an ITO bottom gate electrode 5 with the thickness of 200nm on the surface of the PET flexible plastic substrate 6 in the step (I) under the room temperature vacuum condition by adopting vacuum magnetron sputtering coating equipment;
(II) preparing a double-layer silicon laminating body consisting of the porous silicon nano-film 3 and the SOI silicon substrate by adopting the SOI material
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the silicon nano film 3 with the length of 1cm and the width of 1cm, the thickness of 200nm and the insulator layer SiO are poured2Putting the SOI material with the thickness of 450nm and the thickness of the silicon substrate of 675 mu m into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 8 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the SOI material cleaned in the step (II) and putting the SOI material into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 8 min;
taking out the cleaned SOI material obtained in the step (II), washing with deionized water, drying with an air gun, and putting the SOI material into a clean 250ml polypropylene plastic beaker for later use;
fourthly, coating 1813 positive photoresist on the surface of the silicon nano film 3 of the SOI material obtained in the step (II), and throwing and uniformly stirring the 1813 positive photoresist by sequentially setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
fifthly, baking and heating the SOI material silicon nano film 3 prepared in the step (II) for 90s at 115 ℃ by using a heating plate;
sixthly, using a photoetching machine and a mask plate manufactured according to photoetching patterns, carrying out alignment photoetching on the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the transverse spacing and the longitudinal spacing of 40 mu m which are uniformly distributed and arranged on the surface of the SOI material silicon nano film 3 manufactured in the step (II), and forming the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the longitudinal 5 mu m which are uniformly distributed and arranged with the transverse spacing and the longitudinal spacing of 40 mu m on the surface of the SOI material silicon nano film 3 after developing;
seventhly, etching for 8min in a vacuum environment by adopting a reactive ion etching mode, and removing silicon in a square hole pattern of 5 multiplied by 5 mu m on the surface of the SOI material silicon nano film 3 manufactured in the step (II) to form a porous silicon nano film 3;
eighthly, pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, putting the porous silicon nano-film 3SOI material prepared in the step (B) into the acetone solution, cleaning for 8min, and removing the residual 1813 positive photoresist on the surface of the porous silicon nano-film 3; then pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the porous silicon nano-film 3SOI material cleaned by the acetone solution, and putting the material into the isopropanol solution for cleaning for 8 min; finally, taking out the porous silicon nano-film 3SOI material cleaned by the isopropanol solution, washing the material by deionized water, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
ninthly, 50ml of hydrofluoric acid water with the volume ratio of the deionized water to the hydrofluoric acid being 3:1 is poured into a 250ml polypropylene plastic beakerPutting the porous silicon nano-film 3SOI material prepared in the step (II) into the polypropylene plastic beaker, and after 2h, putting an insulator layer SiO in the SOI material2Is removed by etching to remove SiO in the insulator layer2The porous silicon nano film 3 and the SOI silicon substrate form a double-layer silicon laminating body by virtue of van der Waals attraction; taking out the double-layer silicon laminating body, washing the double-layer silicon laminating body by deionized water, and putting the double-layer silicon laminating body into a clean 250ml polypropylene plastic beaker for later use;
(III) production of SiO by high-temperature growth2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate after being turned over
Putting the double-layer silicon attaching body manufactured in the step (II) into a 1100 ℃ high-temperature heating furnace, introducing oxygen with the flow of 1000sccm, and oxidizing for 45min at high temperature to form SiO with the thickness of 35nm and grown at high temperature on the surface of the porous silicon nano film 32A gate dielectric layer 4;
secondly, coating SU8 glue on the surface of a hard silicon substrate with the thickness of 300 mu m, and uniformly throwing the SU8 glue by setting the rotating speed of a glue homogenizing machine to be 500rpm, the rotating time to be 10s, the rotating speed to be 4000rpm and the rotating time to be 30 s;
thirdly, growing SiO on the surface of the double-layer silicon laminating body porous silicon nano film 3 manufactured in the step (III) by utilizing high temperature2The gate dielectric layer 4 is turned over to make the SiO grown at high temperature2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate which is prepared in the step (III) and coated with SU8 glue on the surface, and the SU8 glue and the SiO grown at high temperature are used for connecting2The adhesive force between the gate dielectric layers 4 is larger than the Van der Waals force between the silicon substrate and the porous silicon nano film 3 in the double-layer silicon binding body, so that the SOI silicon substrate and the porous silicon nano film 3 in the double-layer silicon binding body are separated, and SiO grown at high temperature is used2The gate dielectric layer 4 and the upper porous silicon nano-film 3 are transferred to the surface of the hard silicon substrate to realize the porous silicon nano-film 3 and the SiO grown by high temperature2Turning the upper position and the lower position of the gate dielectric layer 4;
(IV) manufacturing metal titanium electrodes of a source electrode 1 and a drain electrode 2 on the surface of the N-type ion implantation doped porous silicon nano film 3
Connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step (III)2On the gate dielectric layer 4Coating 1813 positive photoresist on the surface of the square porous silicon nano film 3, and uniformly throwing the 1813 positive photoresist by setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
secondly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The porous silicon nano film 3 above the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
thirdly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Photoetching the surface of the porous silicon nano film 3 above the gate dielectric layer 4 to form an N-type heavily doped region 8 pattern, carrying out N-type ion implantation by using ion implantation equipment after developing, wherein the implantation energy is 40Kev, and the dosage is 4 multiplied by 1015cm-2Generating an N-type heavily doped region 8, and performing rapid thermal annealing at the temperature of 750 ℃ for 10s, wherein the undoped region 7 comprises an undoped region 7-1 at the middle position and undoped regions 7-2 at the two sides, the length and the width of the undoped region 7-1 at the middle position are respectively 30 micrometers and 300 micrometers, the length and the width of the undoped region 7-2 at the two sides are respectively 30 micrometers and 300 micrometers, and the N-type heavily doped region 8 is positioned between the undoped region 7-1 at the middle position and the undoped regions 7-2 at the two sides, and the length and the width of the N-type heavily doped region are respectively 30 micrometers and 300 micrometers;
fourthly, 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the surface of the hard silicon substrate obtained in the step IV is connected with SiO growing at high temperature2Placing the gate dielectric layer 4 and the upper N-type ion implantation doped porous silicon nano-film 3 material into the polypropylene plastic beaker for 2min, and removing 1813 positive photoresist on the surface of the N-type ion implantation doped porous silicon nano-film 3; the surface of the hard silicon substrate cleaned by the acetone solution is connected with SiO grown at high temperature2Injecting the grid dielectric layer 4 and the upper N-type ion into the doped porous silicon nano film 3 material, taking out the material, washing the material with deionized water, drying the material with an air gun, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
fifthly, connecting SiO grown at high temperature on the surface of the hard silicon substrate in the step (IV)25214 negative light is coated on the surface of the N-type ion implantation doped porous silicon nano film 3 above the gate dielectric layer 4Etching, setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30s, and uniformly throwing the 5214 negative photoresist;
sixthly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a heating plate2Injecting N-type ions above the gate dielectric layer 4 into the doped porous silicon nano film 3, and baking and heating for 90s at 115 ℃;
seventhly, connecting SiO grown at high temperature to the surface of the hard silicon substrate in step (IV) by using a photoetching machine and a mask plate manufactured according to photoetching patterns2N-type ions are injected into the undoped regions 7-2 at the two sides of the doped porous silicon nano film 3 above the gate dielectric layer 4 and above the adjacent N-type heavily doped region 8, photoetching is carried out to cover the N-type heavily doped region 8 and the undoped regions 7-2 at the two sides with the length and the width of 30 mu m and 300 mu m respectively to form a source electrode 1 pattern and a drain electrode 2 pattern, and the lengths of the source electrode 1 pattern and the drain electrode 2 pattern covering the N-type heavily doped region 8 are 15 mu m;
eighthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern on the upper surface of the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
ninthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown by high temperature2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern engraved on the surface above the gate dielectric layer 4 is exposed and exploded on a photoetching machine for 70 s;
connection of surface of hard silicon substrate in R and step (IV) by using high-temperature grown SiO2After an N-type ion implantation doped porous silicon nano film 3 with a source electrode 1 pattern and a drain electrode 2 pattern etched on the surface above a gate dielectric layer 4 is developed, the source electrode 1 and the drain electrode 2 are respectively positioned above an undoped region 7-2 and an N-type heavily doped region 8 at two sides, the height of a metal titanium electrode is evaporated by adopting vacuum electron beam coating equipment to be 10nm, then the metal titanium electrode is placed into a 250ml polypropylene plastic beaker, 200ml of acetone solution is poured into the polypropylene plastic beaker for soaking for 15min, 5214 negative photoresist and redundant metal titanium are washed off, and the metal titanium electrodes of the source electrode 1 and the drain electrode 2 with the length of 30 mu m, the width of 300 mu m and the height of 10nm are formed;
(V) SiO grown by high temperature2The grid dielectric layer 4 is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode 5
Adding 50ml acetone solution into 250ml polypropylene plastic beaker, connecting SiO grown at high temperature to surface of hard silicon substrate in step (IV)2Injecting N-type ions of the gate dielectric layer 4 and the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface into the doped porous silicon nano-film 3 material, putting the material into the polypropylene plastic beaker for cleaning for 8min, and putting the surface of the hard silicon substrate and the SiO grown at high temperature into the beaker2Cleaning the gate dielectric layer 4 by using SU8 glue, taking out, drying by using an air gun, and injecting N-type ions of the hard silicon substrate and the metal titanium electrodes with the source electrode 1 and the drain electrode 2 on the upper surface into the lower surface of the doped porous silicon nano film 3 by using SiO grown at high temperature2The gate dielectric layer 4 is integrally separated;
secondly, by means of electrostatic force adsorption, N-type ions of the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface are injected into the SiO grown on the lower surface of the doped porous silicon nano film 3 by high temperature2The gate dielectric layer 4 is connected above the ITO bottom gate electrode 5 to finish the high-temperature growth of SiO2And preparing the silicon nano flexible thin film transistor of the gate dielectric layer.
3. The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The performance of the silicon nano flexible thin film transistor of the gate dielectric layer is shown in Table 2
TABLE 2 growth of SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
Figure BDA0002644029490000211
Example 3
1. Sources of materials and equipment
(1) Source of material
PET flexible plastic substrate 6: the same as example 1;
ITO bottom gate electrode 5: the same as example 1;
SOI material: SOI refers to silicon on insulator, commercially available;
oxygen: the same as example 1;
metal titanium: the same as example 1;
a hard silicon substrate: the same as example 1;
hydrofluoric acid: the same as example 1;
acetone solution: the same as example 1;
isopropanol solution: the same as example 1;
deionized water: the same as example 1;
SU8 glue: the same as example 1;
1813 positive photoresist: the same as example 1;
5214 negative photoresist: the same as example 1;
heat release tape: the same as example 1;
250ml polypropylene plastic beaker: the same as example 1;
(2) source of equipment
An ultrasonic cleaner: the same as example 1;
an air gun: the same as example 1;
heating plate: the same as example 1;
a spin coater: the same as example 1;
a photoetching machine: the same as example 1;
mask plate: the same as example 1;
high-temperature heating furnace: the same as example 1;
the reactive ion etching equipment comprises: the same as example 1;
an ion implantation apparatus: the same as example 1;
and (3) thermal annealing equipment: the same as example 1;
vacuum magnetron sputtering coating equipment: the same as example 1;
vacuum electron beam coating equipment: the same as in example 1.
2. The invention relates to a method for growing SiO by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer
ITO bottom grid electrode 5 is plated on surface of flexible plastic substrate 6 of PET (polyethylene terephthalate)
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, a PET flexible plastic substrate 6 with the length of 2cm, the width of 2cm and the thickness of 175 mu m is placed into the polypropylene plastic beaker, and the polypropylene plastic beaker is placed into an ultrasonic cleaner for cleaning for 10 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the PET flexible plastic substrate 6 cleaned in the step (I) and putting the PET flexible plastic substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 10 min;
taking out the cleaned PET flexible plastic substrate 6 obtained in the step (I), washing with deionized water, drying with an air gun, and putting the PET flexible plastic substrate 6 into a clean 250ml polypropylene plastic beaker for later use;
plating an ITO bottom gate electrode 5 with the thickness of 200nm on the surface of the PET flexible plastic substrate 6 in the step (I) under the room temperature vacuum condition by adopting vacuum magnetron sputtering coating equipment;
(II) preparing a double-layer silicon laminating body consisting of the porous silicon nano-film 3 and the SOI silicon substrate by adopting the SOI material
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the silicon nano film 3 with the length of 1cm and the width of 1cm and the thickness of 210nm and the insulator layer SiO are poured into the beaker2Putting the SOI material with the thickness of 470nm and the thickness of 690 mu m of the silicon substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 10 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the SOI material cleaned in the step (II) and putting the SOI material into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 10 min;
taking out the cleaned SOI material obtained in the step (II), washing with deionized water, drying with an air gun, and putting the SOI material into a clean 250ml polypropylene plastic beaker for later use;
fourthly, coating 1813 positive photoresist on the surface of the silicon nano film 3 of the SOI material obtained in the step (II), and throwing and uniformly stirring the 1813 positive photoresist by sequentially setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
fifthly, baking and heating the SOI material silicon nano film 3 prepared in the step (II) for 90s at 115 ℃ by using a heating plate;
sixthly, using a photoetching machine and a mask plate manufactured according to photoetching patterns, carrying out alignment photoetching on the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the transverse spacing and the longitudinal spacing of 40 mu m which are uniformly distributed and arranged on the surface of the SOI material silicon nano film 3 manufactured in the step (II), and forming the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the longitudinal 5 mu m which are uniformly distributed and arranged with the transverse spacing and the longitudinal spacing of 40 mu m on the surface of the SOI material silicon nano film 3 after developing;
seventhly, etching for 10min in a vacuum environment by adopting an etching mode of reactive ions, and removing silicon in a square hole pattern of 5 multiplied by 5 mu m on the surface of the SOI material silicon nano film 3 manufactured in the step (II) to form a porous silicon nano film 3;
eighthly, pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, putting the porous silicon nano-film 3SOI material prepared in the step (B) into the acetone solution, cleaning for 10min, and removing the residual 1813 positive photoresist on the surface of the porous silicon nano-film 3; then pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the porous silicon nano-film 3SOI material cleaned by the acetone solution, and putting the material into the isopropanol solution for cleaning for 10 min; finally, taking out the porous silicon nano-film 3SOI material cleaned by the isopropanol solution, washing the material by deionized water, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
ninthly, 50ml of hydrofluoric acid water solution with the volume ratio of deionized water to hydrofluoric acid being 3:1 is poured into a 250ml polypropylene plastic beaker, the porous silicon nano-film 3SOI material manufactured in the step (II) is put into the polypropylene plastic beaker, and after 2 hours, an insulator layer SiO in the porous silicon nano-film 3SOI material2Is removed by etching to remove SiO in the insulator layer2The porous silicon nano film 3 and the SOI silicon substrate form a double-layer silicon laminating body by virtue of van der Waals attraction; taking out the double-layer silicon laminating body, washing the double-layer silicon laminating body by deionized water, and putting the double-layer silicon laminating body into a clean 250ml polypropylene plastic beaker for later use;
(III) production of SiO by high-temperature growth2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate after being turned over
Putting the double-layer silicon attaching body manufactured in the step (II) into a 1100 ℃ high-temperature heating furnace, introducing oxygen with the flow of 1000sccm, and oxidizing for 45min at high temperature to form SiO with the thickness of 40nm and grown at high temperature on the surface of the porous silicon nano film 32A gate dielectric layer 4;
secondly, coating SU8 glue on the surface of a hard silicon substrate with the thickness of 310 mu m, and uniformly throwing the SU8 glue by setting the rotating speed of a glue homogenizing machine to be 500rpm, the rotating time to be 10s, the rotating speed to be 4000rpm and the rotating time to be 30 s;
thirdly, growing SiO on the surface of the double-layer silicon laminating body porous silicon nano film 3 manufactured in the step (III) by utilizing high temperature2The gate dielectric layer 4 is turned over to make the SiO grown at high temperature2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate which is prepared in the step (III) and coated with SU8 glue on the surface, and the SU8 glue and the SiO grown at high temperature are used for connecting2The adhesive force between the gate dielectric layers 4 is larger than the Van der Waals force between the SOI silicon substrate and the porous silicon nano film 3 in the double-layer silicon laminating body, so that the SOI silicon substrate and the porous silicon nano film 3 in the double-layer silicon laminating body are separated, and SiO grown at high temperature is used2The gate dielectric layer 4 and the upper porous silicon nano-film 3 are transferred to the surface of the hard silicon substrate to realize the porous silicon nano-film 3 and the SiO grown by high temperature2Turning the upper position and the lower position of the gate dielectric layer 4;
(IV) manufacturing metal titanium electrodes of a source electrode 1 and a drain electrode 2 on the surface of the N-type ion implantation doped porous silicon nano film 3
Connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step (III)2Coating 1813 positive photoresist on the surface of the porous silicon nano film 3 above the gate dielectric layer 4, and uniformly throwing the spin rate of a spin coater at 500rpm for 10s, the spin rate at 4000rpm for 30sThe 1813 positive photoresist;
secondly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The porous silicon nano film 3 above the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
thirdly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Photoetching the surface of the porous silicon nano film 3 above the gate dielectric layer 4 to form an N-type heavily doped region 8 pattern, carrying out N-type ion implantation by using ion implantation equipment after developing, wherein the implantation energy is 40Kev, and the dosage is 4 multiplied by 1015cm-2Generating an N-type heavily doped region 8, and performing rapid thermal annealing at the temperature of 750 ℃ for 10s, wherein the undoped region 7 comprises an undoped region 7-1 at the middle position and undoped regions 7-2 at the two sides, the length and the width of the undoped region 7-1 at the middle position are respectively 50 micrometers and 500 micrometers, the length and the width of the undoped region 7-2 at the two sides are respectively 50 micrometers and 500 micrometers, and the N-type heavily doped region 8 is positioned between the undoped region 7-1 at the middle position and the undoped regions 7-2 at the two sides, and the length and the width of the N-type heavily doped region are respectively 50 micrometers and 500 micrometers;
fourthly, 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the surface of the hard silicon substrate obtained in the step IV is connected with SiO growing at high temperature2Placing the gate dielectric layer 4 and the upper N-type ion implantation doped porous silicon nano-film 3 material into the polypropylene plastic beaker for 2min, and removing 1813 positive photoresist on the surface of the N-type ion implantation doped porous silicon nano-film 3; the surface of the hard silicon substrate cleaned by the acetone solution is connected with SiO grown at high temperature2Injecting the grid dielectric layer 4 and the upper N-type ion into the doped porous silicon nano film 3 material, taking out the material, washing the material with deionized water, drying the material with an air gun, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
fifthly, connecting SiO grown at high temperature on the surface of the hard silicon substrate in the step (IV)2Coating 5214 negative photoresist on the surface of the N-type ion implantation doped porous silicon nano film 3 above the gate dielectric layer 4, and uniformly throwing the 5214 negative photoresist at the rotating speed of 500rpm, the rotating time of 10s, the rotating speed of 4000rpm and the rotating time of 30s of a spin coater;
sixthly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a heating plate2Injecting N-type ions above the gate dielectric layer 4 into the doped porous silicon nano film 3, and baking and heating for 90s at 115 ℃;
seventhly, connecting SiO grown at high temperature to the surface of the hard silicon substrate in step (IV) by using a photoetching machine and a mask plate manufactured according to photoetching patterns2N-type ions are injected into the undoped regions 7-2 at the two sides of the doped porous silicon nano film 3 above the gate dielectric layer 4 and above the adjacent N-type heavily doped region 8, photoetching is carried out to cover the N-type heavily doped region 8 and the undoped regions 7-2 at the two sides, wherein the lengths and the widths of the undoped regions are respectively 50 mu m and 500 mu m, so as to form a source electrode 1 pattern and a drain electrode 2 pattern, and the lengths of the source electrode 1 pattern and the drain electrode 2 pattern covering the N-type heavily doped region 8 are both 25 mu m;
eighthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern on the upper surface of the gate dielectric layer 4 is baked and heated for 90s at 115 ℃;
ninthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown by high temperature2The N-type ion implantation doped porous silicon nano film 3 with the source electrode 1 pattern and the drain electrode 2 pattern engraved on the surface above the gate dielectric layer 4 is exposed and exploded on a photoetching machine for 70 s;
connection of surface of hard silicon substrate in R and step (IV) by using high-temperature grown SiO2After an N-type ion implantation doped porous silicon nano film 3 with a source electrode 1 pattern and a drain electrode 2 pattern etched on the surface above a gate dielectric layer 4 is developed, a source electrode 1 and a drain electrode 2 are respectively positioned above an undoped region 7-2 and an N-type heavily doped region 8 at two sides, the height of a metal titanium electrode is evaporated by adopting vacuum electron beam coating equipment to be 20nm, then the metal titanium electrode is placed into a 250ml polypropylene plastic beaker, 200ml of acetone solution is poured into the beaker to be soaked for 15min, 5214 negative photoresist and redundant metal titanium are washed off, and the metal titanium electrodes of the source electrode 1 and the drain electrode 2 with the length of 50 mu m, the width of 500 mu m and the height of 20nm are formed;
(V) SiO grown by high temperature2The grid dielectric layer 4 is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode 5
Adding 50ml acetone solution into 250ml polypropylene plastic beaker, connecting SiO grown at high temperature to surface of hard silicon substrate in step (IV)2Injecting N-type ions of the gate dielectric layer 4 and the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface into the doped porous silicon nano-film 3 material, putting the material into the polypropylene plastic beaker for cleaning for 10min, and putting the surface of the hard silicon substrate and the SiO grown at high temperature into the beaker2Cleaning the gate dielectric layer 4 by using SU8 glue, taking out, drying by using an air gun, and injecting N-type ions of the hard silicon substrate and the metal titanium electrodes with the source electrode 1 and the drain electrode 2 on the upper surface into the lower surface of the doped porous silicon nano film 3 by using SiO grown at high temperature2The gate dielectric layer 4 is integrally separated;
secondly, by means of electrostatic force adsorption, N-type ions of the metal titanium electrode with the source electrode 1 and the drain electrode 2 on the upper surface are injected into the SiO grown on the lower surface of the doped porous silicon nano film 3 by high temperature2The gate dielectric layer 4 is connected above the ITO bottom gate electrode 5 to finish the high-temperature growth of SiO2And preparing the silicon nano flexible thin film transistor of the gate dielectric layer.
3. The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
The invention relates to a method for growing SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The performance of the silicon nano flexible thin film transistor of the gate dielectric layer is shown in Table 3
TABLE 3 growth of SiO by high temperature2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor performance of gate dielectric layer
Figure BDA0002644029490000281
Example illustrates the use of a high temperature to grow SiO in accordance with the present invention2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer for preparing SiO2When the silicon nano flexible thin film transistor of the gate dielectric layer is used, the SiO grown at high temperature is utilized2The gate dielectric layer 4 is not directly grown on the surface of the PET flexible plastic substrate 6 coated with the ITO bottom gate electrode 5, but is grown on the surface of the double-layer silicon laminating body porous silicon nano film 3 at high temperature, and then the SiO grown at high temperature is utilized2The gate dielectric layer 4 is connected with the surface of the hard silicon substrate through overturning, after the source electrode 1 and the drain electrode 2 metal titanium electrode are evaporated on the upper surface of the N-type ion injection doped porous silicon nano film 3, the lower surface of the N-type ion injection doped porous silicon nano film 3 utilizes the SiO grown at high temperature2The gate dielectric layer 4 is separated from the hard silicon substrate, and finally, the SiO grown at high temperature is utilized2The gate dielectric layer 4 is connected with an ITO bottom gate electrode 5 to finish the method of the invention by growing SiO at high temperature2The preparation of the silicon nanometer flexible thin film transistor of the gate dielectric layer is realized by utilizing high-temperature growth SiO2The gate dielectric layer 4 is SiO grown at a lower temperature2The gate dielectric layer has the advantages of high density, high performance stability, high breakdown voltage and the like, so that the invention utilizes high-temperature growth of SiO2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Compared with the prior art, the electrical property and stability of the silicon nano flexible thin film transistor of the gate dielectric layer are obviously improved, and the invention utilizes high-temperature growth of SiO2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2Silicon nanometer flexible thin film transistor gate dielectric layer unit area capacitance of 20-60 nF/cm22.6-3.0V of turn-on voltage and 10 of grid leakage current-9～10- 7A. Electron mobility 100cm at room temperature2VS, service life 6000-10000 min, the invention utilizes high temperature to grow SiO2SiO prepared by preparation method of silicon nano flexible thin film transistor of gate dielectric layer2The silicon nano flexible thin film transistor of the gate dielectric layer has the characteristics of good electrical property and high stability.

Claims (1)

1. SiO growth by high temperature2The preparation method of the silicon nanometer flexible thin film transistor of the gate dielectric layer sequentially comprises the following steps:
ITO bottom grid electrode (5) is plated on the surface of PET flexible plastic substrate (6)
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, a PET flexible plastic substrate (6) with the length of 2cm, the width of 2cm and the thickness of 175 mu m is placed into the polypropylene plastic beaker, and the polypropylene plastic beaker is placed into an ultrasonic cleaner for cleaning for 5-10 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the PET flexible plastic substrate (6) cleaned in the step (I) and putting the PET flexible plastic substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
taking out the cleaned PET flexible plastic substrate (6) in the step (I), washing with deionized water, drying by using an air gun, and putting the PET flexible plastic substrate (6) into a clean 250ml polypropylene plastic beaker for later use;
fourthly, plating an ITO bottom gate electrode (5) with the thickness of 200nm on the surface of the PET flexible plastic substrate (6) in the step (I) under the room temperature vacuum condition by adopting vacuum magnetron sputtering coating equipment;
(II) adopting SOI material to manufacture a double-layer silicon laminating body consisting of the porous silicon nano-film (3) and the SOI silicon substrate
50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the silicon nano film (3) with the length of 1cm and the width of 1cm, the thickness of 190-210 nm and the insulator layer of SiO is poured into the beaker2Putting the SOI material with the thickness of 430-470 nm and the thickness of 660-690 mu m of the silicon substrate into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the SOI material cleaned in the step (II) and putting the SOI material into the polypropylene plastic beaker, and putting the polypropylene plastic beaker into an ultrasonic cleaner for cleaning for 5-10 min;
taking out the cleaned SOI material obtained in the step (II), washing with deionized water, drying with an air gun, and putting the SOI material into a clean 250ml polypropylene plastic beaker for later use;
fourthly, coating 1813 positive photoresist on the surface of the SOI material silicon nano film (3) obtained in the step (II), and throwing and uniformly the 1813 positive photoresist by sequentially setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
fifthly, baking and heating the SOI material silicon nano film (3) prepared in the step (II) for 90s at 115 ℃ by using a heating plate;
sixthly, using a photoetching machine and a mask plate manufactured according to photoetching patterns, carrying out alignment photoetching on the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the length of 5 multiplied by 5 mu m which are uniformly distributed and arranged on the surface of the SOI material silicon nano film (3) manufactured in the step (II) fifth, wherein the transverse spacing and the longitudinal spacing are 40 mu m, and forming the transverse 222 square hole patterns and the longitudinal 222 square hole patterns with the length of 5 multiplied by 5 mu m which are uniformly distributed and arranged on the surface of the SOI material silicon nano film (3) after developing;
seventhly, etching for 5-10 min in a vacuum environment by adopting a reactive ion etching mode, and removing silicon in a square hole pattern of 5 multiplied by 5 mu m on the surface of the SOI material silicon nano film (3) manufactured in the step (II) to form a porous silicon nano film (3);
pouring 50ml of acetone solution into a 250ml polypropylene plastic beaker, putting the porous silicon nano-film (3) SOI material prepared in the step (B) into the acetone solution, cleaning for 5-10 min, and removing the residual 1813 positive photoresist on the surface of the porous silicon nano-film (3); then pouring 50ml of isopropanol solution into a 250ml polypropylene plastic beaker, taking out the porous silicon nano film (3) SOI material cleaned by the acetone solution, and putting the porous silicon nano film (3) SOI material into the isopropanol solution for cleaning for 5-10 min; finally, taking out the porous silicon nano film (3) SOI material cleaned by the isopropanol solution, washing the material by deionized water, and putting the material into a clean 250ml polypropylene plastic beaker for later use;
ninthly, 50ml of hydrofluoric acid water solution with the volume ratio of deionized water to hydrofluoric acid being 3:1 is poured into a 250ml polypropylene plastic beaker, the porous silicon nano-film (3) SOI material manufactured in the step (II) is put into the polypropylene plastic beaker, and after 2 hours, an insulator layer SiO in the porous silicon nano-film (3) SOI material2Is removed by etching to remove SiO in the insulator layer2The porous silicon nano film (3) and the SOI silicon substrate form a double layer by virtue of van der Waals attractionA silicon bonded body; taking out the double-layer silicon laminating body, washing the double-layer silicon laminating body by deionized water, and putting the double-layer silicon laminating body into a clean 250ml polypropylene plastic beaker for later use;
(III) production of SiO by high-temperature growth2The gate dielectric layer (4) is connected with the surface of the hard silicon substrate after being turned over
Putting the double-layer silicon attaching body manufactured in the step (II) into a 1100 ℃ high-temperature heating furnace, introducing oxygen with the flow of 1000sccm, and oxidizing for 45min at high temperature to form SiO with the thickness of 30-40 nm and grown at high temperature on the surface of the porous silicon nano film (3)2A gate dielectric layer (4);
secondly, coating SU8 glue on the surface of a hard silicon substrate with the thickness of 290-310 mu m, and uniformly throwing the SU8 glue at the rotating speed of 500rpm, the rotating time of 10s, the rotating speed of 4000rpm and the rotating time of 30s of a spin coater;
thirdly, growing SiO on the surface of the double-layer silicon laminating body porous silicon nano film (3) manufactured in the step (III) by utilizing high temperature2The gate dielectric layer (4) is turned over to ensure that the SiO grown at high temperature is utilized2The gate dielectric layer (4) is connected with the surface of the hard silicon substrate which is prepared in the step (III) and coated with SU8 glue on the surface, and the SU8 glue and the SiO grown at high temperature are used for connection2The adhesive force between the gate dielectric layers (4) is larger than the Van der Waals force between the SOI silicon substrate and the porous silicon nano film (3) in the double-layer silicon laminating body, so that the SOI silicon substrate and the porous silicon nano film (3) in the double-layer silicon laminating body are separated, and SiO grown at high temperature is used2The gate dielectric layer (4) and the upper porous silicon nano film (3) are transferred to the surface of the hard silicon substrate to realize the porous silicon nano film (3) and the SiO grown by high temperature2The upper and lower positions of the gate dielectric layer (4) are turned over;
(IV) manufacturing metal titanium electrodes of a source electrode (1) and a drain electrode (2) on the surface of the N-type ion implantation doped porous silicon nano film (3)
Connecting SiO grown at high temperature to the surface of the hard silicon substrate in the step (III)2Coating 1813 positive photoresist on the surface of the porous silicon nano film (3) above the gate dielectric layer (4), and uniformly throwing the 1813 positive photoresist by setting the rotation speed of a spin coater to be 500rpm, the rotation time to be 10s, the rotation speed to be 4000rpm and the rotation time to be 30 s;
② step (IV) using a heating plate) Firstly, the surface of the hard silicon substrate is connected with SiO grown at high temperature2The porous silicon nano film (3) above the gate dielectric layer (4) is baked and heated for 90s at 115 ℃;
thirdly, connecting the surface of the hard silicon substrate obtained in the step (IV) with SiO grown at high temperature by using a photoetching machine and a mask plate manufactured according to photoetching patterns2Photoetching the surface of the porous silicon nano film (3) above the gate dielectric layer (4) to form an N-type heavily doped region (8) pattern, carrying out N-type ion implantation by adopting ion implantation equipment after developing, wherein the implantation energy is 40Kev, and the dosage is 4 multiplied by 1015cm-2Generating an N-type heavily doped region (8), and performing rapid thermal annealing at the temperature of 750 ℃ for 10s, wherein the undoped region (7) comprises an undoped region (7-1) at the middle position and undoped regions (7-2) at the two sides, the length and the width of the undoped region (7-1) at the middle position are respectively 10-50 mu m and 50-500 mu m, the length and the width of the undoped region (7-2) at the two sides are respectively 10-50 mu m and 50-500 mu m, the N-type heavily doped region (8) is positioned between the undoped region (7-1) at the middle position and the undoped regions (7-2) at the two sides, and the length and the width of the N-type heavily doped region are respectively 10-50 mu m and 50-500 mu m;
fourthly, 50ml of acetone solution is poured into a 250ml polypropylene plastic beaker, and the surface of the hard silicon substrate obtained in the step IV is connected with SiO growing at high temperature2Placing the gate dielectric layer (4) and the upper N-type ion implantation doped porous silicon nano-film (3) material into the polypropylene plastic beaker for 2min, and removing 1813 positive photoresist on the surface of the N-type ion implantation doped porous silicon nano-film (3); the surface of the hard silicon substrate cleaned by the acetone solution is connected with SiO grown at high temperature2Taking the grid dielectric layer (4) and the upper N-type ion implantation doped porous silicon nano film (3) material out of deionized water, washing, drying by using an air gun, and putting into a clean 250ml polypropylene plastic beaker for later use;
fifthly, connecting SiO grown at high temperature on the surface of the hard silicon substrate in the step (IV)2Coating 5214 negative photoresist on the surface of the N-type ion implantation doped porous silicon nano film (3) above the gate dielectric layer (4), and uniformly throwing the 5214 negative photoresist by setting the rotating speed of a spin coater to be 500rpm, the rotating time to be 10s, the rotating speed to be 4000rpm and the rotating time to be 30 s;
sixthly, use and addHot plate step (IV) connecting the surface of the hard silicon substrate with SiO grown at high temperature2N-type ions are injected above the gate dielectric layer (4) and doped with the porous silicon nano-film (3) and are baked and heated for 90s at the temperature of 115 ℃;
seventhly, connecting SiO grown at high temperature to the surface of the hard silicon substrate in step (IV) by using a photoetching machine and a mask plate manufactured according to photoetching patterns2N-type ions are injected into undoped regions (7-2) at two sides of the doped porous silicon nano film (3) above the gate dielectric layer (4) and above N-type heavily doped regions (8) adjacent to the undoped regions, photoetching is carried out to cover the N-type heavily doped regions (8) and the undoped regions (7-2) at two sides, wherein the lengths and the widths of the undoped regions (7-2) are respectively 10-50 mu m and 50-500 mu m, so as to form a source electrode (1) pattern and a drain electrode (2) pattern, and the lengths of the source electrode (1) pattern and the drain electrode (2) pattern covering the N-type heavily doped regions (8) are both 5-25 mu m;
eighthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown at high temperature by using a heating plate2Injecting N-type ions with source electrode (1) patterns and drain electrode (2) patterns on the upper surface of the gate dielectric layer (4) into the doped porous silicon nano film (3), and baking and heating the film for 90s at 115 ℃;
ninthly, connecting the surface of the hard silicon substrate in the step (IV) with SiO grown by high temperature2Injecting N-type ions with source electrode (1) patterns and drain electrode (2) patterns on the upper surface of the gate dielectric layer (4) into the doped porous silicon nano film (3) and carrying out naked explosion on the photoetching machine for 70 s;
connection of surface of hard silicon substrate in R and step (IV) by using high-temperature grown SiO2After an N-type ion injection doped porous silicon nano film (3) with a source electrode (1) pattern and a drain electrode (2) pattern engraved on the surface above a gate dielectric layer (4) is developed, evaporating and plating a metal titanium electrode with the height of 0.5-20 nm respectively above an undoped region (7-2) and an N-type heavily doped region (8) of the source electrode (1) and the drain electrode (2) which are respectively positioned at two sides by adopting vacuum electron beam coating equipment, then putting the metal titanium electrode into a 250ml polypropylene plastic beaker, pouring 200ml of acetone solution for soaking for 15min, washing 5214 negative photoresist and redundant metal titanium, and forming the metal titanium electrode of the source electrode (1) and the drain electrode (2) with the length of 10-50 mu m, the width of 50-500 mu m and the height of 0.5-20 nm;
(V) SiO grown by high temperature2Grid mediumThe layer (4) is separated from the surface of the hard silicon substrate and is connected with an ITO bottom grid electrode (5)
Adding 50ml acetone solution into 250ml polypropylene plastic beaker, connecting SiO grown at high temperature to surface of hard silicon substrate in step (IV)2Injecting N-type ions of a gate dielectric layer (4) and a metal titanium electrode with a source electrode (1) and a drain electrode (2) on the upper surface into a doped porous silicon nano-film (3) material, putting the material into the polypropylene plastic beaker, cleaning for 5-10 min, and putting the surface of a hard silicon substrate and SiO grown at high temperature into the beaker2Cleaning SU8 glue used for connecting the gate dielectric layer (4), taking out, drying by using an air gun, and injecting N-type ions of the hard silicon substrate and the metal titanium electrodes of the source electrode (1) and the drain electrode (2) on the upper surface into the lower surface of the doped porous silicon nano film (3) by using SiO grown at high temperature2The gate dielectric layer (4) is integrally separated;
secondly, by means of electrostatic force adsorption, the lower surface of the porous silicon nano-film (3) is doped with SiO grown at high temperature by N-type ion injection of the metal titanium electrode with the source electrode (1) and the drain electrode (2) on the upper surface through evaporation2The gate dielectric layer (4) is connected above the ITO bottom gate electrode (5) to finish the high-temperature growth of SiO2And preparing the silicon nano flexible thin film transistor of the gate dielectric layer.
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