CN108346691A - Germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor and preparation method thereof - Google Patents
Germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor and preparation method thereof Download PDFInfo
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- CN108346691A CN108346691A CN201810113893.9A CN201810113893A CN108346691A CN 108346691 A CN108346691 A CN 108346691A CN 201810113893 A CN201810113893 A CN 201810113893A CN 108346691 A CN108346691 A CN 108346691A
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- 239000010408 film Substances 0.000 title claims abstract description 71
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 54
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 54
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 238000002360 preparation method Methods 0.000 title claims description 14
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000011787 zinc oxide Substances 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 239000004033 plastic Substances 0.000 claims abstract description 9
- 229920003023 plastic Polymers 0.000 claims abstract description 9
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims abstract description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 29
- 238000001259 photo etching Methods 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 14
- 238000000992 sputter etching Methods 0.000 claims description 8
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004026 adhesive bonding Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000011701 zinc Substances 0.000 claims 1
- 229910052725 zinc Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 4
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 28
- 239000011112 polyethylene naphthalate Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 241000209094 Oryza Species 0.000 description 3
- 235000007164 Oryza sativa Nutrition 0.000 description 3
- 235000009566 rice Nutrition 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000012585 homogenous medium Substances 0.000 description 2
- HHAVHBDPWSUKHZ-UHFFFAOYSA-N propan-2-ol;propan-2-one Chemical compound CC(C)O.CC(C)=O HHAVHBDPWSUKHZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 210000000170 cell membrane Anatomy 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002609 medium Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- -1 polyethylene naphthalate Polymers 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to high control force thin-film transistor technologies, flexible devices, to propose thin film transistor (TFT) and its manufacturing technology scheme, the transistor has preferable performance and higher working frequency and stronger grid control force, is with a wide range of applications in the making of flexible integration circuit, intelligence wearing and field of photoelectric devices.Thus, the technical solution adopted by the present invention is, germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor, structure is followed successively by PEN plastic supporting bases, tin indium oxide ITO bottom gate thin films layer, zinc oxide gate dielectric layer, the germanium nanometer film of n-type doping, ITO source-drain electrodes layer, top zinc oxide gate dielectric layer and top grid oxide layer from the bottom to top, the germanium nanometer film of the n-type doping is that symmetrical N doped regions at two are formed in germanium nanometer film, it is source electrode above N doped regions at one, is drain electrode above another place N doped regions.Present invention is mainly applied to thin film transistor (TFT) design and manufacture.
Description
Technical field
The present invention relates to high control force thin-film transistor technologies, flexible devices, specifically, are related to germanium nanometer film flexible and transparent
Type top bottom double gate thin-film transistor manufacturing method.
Background technology
Flexible electronic be by organic and inorganic material electronics element manufacturing on flexible, Drawability plastics or thin metal matrix plate
New electronic science and technology, the fields such as information, the energy, medical treatment, national defence all have extensive use.Such as print RFID (radio frequency identifications
Label), electronics surface mount, Organic Light Emitting Diode OLED, flexible electronic displays etc..With traditional IC (integrated circuit) skill
Art is the same, and the main drive of flexible electronic technology development is manufacturing process and equipment.With lower on the substrate of more large format
Cost produce the smaller flexible electronic device of characteristic size and become the key of manufacture.The present invention is received using one kind based on germanium
The novel process of rice film preparation, using magnetron sputtering conductive film and dual dielectric layer grid, ion etching and HF after photoetching
The technology of (hydrofluoric acid) wet etching, by GOI (germanium on insulator) germanium nanometer film stripping and be transferred to flexible
On PEN (polyethylene naphthalate) substrate, a double-deck grid is then formed by way of photoetching layer by layer and etching
Single-groove road structure transistor is controlled, is expected in the future in wearable electronic, extensive flexible integration circuit etc. acquirement is answered extensively
With.
Invention content
In order to overcome the deficiencies of the prior art, the present invention is directed to propose thin film transistor (TFT) and its manufacturing technology scheme, the crystalline substance
Body pipe has preferable performance and higher working frequency and stronger grid control force, making, intelligence in flexible integration circuit
It can dress and field of photoelectric devices is with a wide range of applications.For this purpose, the technical solution adopted by the present invention is, germanium nanometer film
Flexible and transparent type top bottom double gate thin-film transistor, structure are followed successively by PEN plastic supporting bases, tin indium oxide ITO bottom gate electricity from the bottom to top
Pole layer, the germanium nanometer film of zinc oxide gate dielectric layer, n-type doping, ITO source-drain electrodes layer, top zinc oxide gate dielectric layer and
Top grid oxide layer, the germanium nanometer film of the n-type doping are that symmetrical N doped regions at two are formed in germanium nanometer film, and N mixes at one
It is source electrode above miscellaneous area, is drain electrode above another place N doped regions.
Bias is added between top grid oxide layer, ITO bottom gate thin film layers, doped region is close to gate oxide below source and drain grade
Place can form electron inversion layer, and as the conducting channel of device, break-over of device then adds bias between source-drain electrode,
Device will start to work.
Germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor preparation method, is sequentially prepared the bottoms ITO on PEN substrates
Gate electrode layer, zinc oxide gate dielectric layer, the germanium nanometer film of n-type doping, ITO source-drain electrodes layer, top zinc oxide gate dielectric
Layer and top grid oxide layer, using ito film as the gate electrode of top and bottom, grid oxygen of the zinc oxide film as top and bottom
Layer is carried out at the same time driving in top and bottom grid to realize to transistor；The germanium nanometer film of the n-type doping is received in germanium
Rice film is interior to form symmetrical N doped regions at two, and N doped regions top is source electrode at one, is drain electrode above another place N doped regions.
Further specific preparation process is as follows：
A. it selects PEN flexible materials as substrate, first puts PEN into the beaker for filling acetone soln, then super
It is cleaned 5 minutes in sound wave washer, it then will in ultrasonic cleaner by the PEN cleaned with acetone using aqueous isopropanol
Acetone cleans up, and obtains more clean substrate；
B. ito film and zinc oxide bottom dielectric grid layer film are plated on PEN substrates using magnetron sputtering；
C. GOI materials are selected, are cleaned using acetone in ultrasonic cleaner, acetone is then cleaned using isopropanol
Residue dries up GOI；
D. photoresist is coated on the surfaces GOI, and is got rid of photoresist uniformly using sol evenning machine, then use litho machine and system
The mask plate performed carries out being lithographically formed specific doped region pattern, and N-type injection is then carried out by the way of ion implanting, production
Source of students leakage doped region after rapid thermal annealing, removes photoresist under 750 DEG C of temperature condition in acetone soln；
E. according to ready-made label on mask plate, by the square hole of spacing 5um arrangements in source and drain doping area and mask plate
Layer carries out alignment photoetching, the small aperture layer of square of spacing 5um arrangements is formed after development on GOI, then using ion etching
Mode removes the silicon on square aperture；
F. 3:In 1 HF solution, ready-made GOI before being put into, the oxygen buried layer after two hours on GOI will be corroded dry
Only, subsequent germanium nanometer film layer will fall off, and germanium nanometer film layer is adhered to the flexible PEN substrates for having plated film, drying；
G. gluing in the germanium nanometer film on being transferred to PEN, according in square aperture layer after being got rid of uniformly with sol evenning machine
Label carry out alignment photoetching, form the grid of transistor, then by the way of ion etching, respectively by germanium nanometer film and
The gate oxide film layer etching plated, Ohmic contact is formed with conductive ITO layer；
H. after going photoresist then to carry out spin coating to the device on PEN, alignment photoetching, shape are carried out according to the label of grid
At the pattern of top gate dielectric layer；
I. last, magnetron sputtering is carried out on the pattern of formation, the gate dielectric layer at the top of top grid plated zinc oxide；
J. it is directed at photoetching after going photoresist then to carry out gluing to the flexible device for forming top gate dielectric layer, forms top-gated
With the photoengraving pattern of source-drain electrode, ITO top grids and source-drain electrode layer are formed by the way of magnetron sputtering, removes photoresist it
Afterwards, the preparation of device is completed.
The features of the present invention and advantageous effect are：
The present invention prepares transistor in PEN plastic supporting bases, realizes the flexural property of device, is compared to traditional silicon in addition
Substrate can greatly improve the ghost effect of device, improves working frequency and response speed, may be implemented under flexuosity
The normal work of transistor increases substantially the control ability of grid, is realized on intelligently wearing flexible electronic product extensive
Using.
Description of the drawings：
Fig. 1 is the 3 dimensional drawing of flexible double grid thin film transistor (TFT)；
Fig. 2 is the sectional view of transistor；
Fig. 3 is the fundamental diagram of invention.
Specific implementation mode
The present invention is described and a kind of is prepared on PEN plastics based on the germanium film transfer techniques in flexible substrate
The structure and preparation method of the high control force thin film transistor (TFT) of bottom double grid driving are pushed up, the primary structure of transistor is moulded comprising PEN
Expect substrate, ITO gate electrode layers, novel ZnO gate dielectric layers, the germanium nanometer film of n-type doping, ITO source-drain electrode layers.It uses herein
A kind of novel preparation process coats layer of ZnO Jie on the PEN substrates for be coated with ITO conductive layer using the method for magnetron sputtering
Matter layer applies layer of ZnO as bottom grid oxide layer, in the specific undoped area of germanium film after the transfer and is used as top grid oxygen
Layer.Shifted on GOI followed by the mask plate photoetching layer by layer for preparing of design prepared in the germanium nanometer film got off grid with
Source-drain electrode, realize a upper frequency under work and the higher control ability of grid top bottom double-gate structure transistor system
It is standby.Transistor has preferable performance and higher working frequency and stronger grid control force, in the system of flexible integration circuit
Make, intelligence wearing and field of photoelectric devices are with a wide range of applications.
It is brilliant it is an object of the invention to design and prepare a kind of germanium nanometer film of the double-deck grid structure based on flexible PEN substrates
Body pipe, using the low temperature process of magnetron sputtering, being designed in relatively simple technique and preparing the double-deck grid structure has higher grid
The flexible thin-film transistor of pole drive control ability, using top bottom double-gate structure extreme enrichment transistor as circuit components
Use.In addition, being driven using bottom and top transparent conductive film, production cost is reduced, light transmission is more excellent
It is good so that the flexible device provides possibility in the application of large scale integrated circuit and photoelectric device.
Technical program of the present invention lies in ITO and zinc oxide grid Jie are plated on PEN substrates using magnetron sputtering technique
Plasma membrane then forms doped region by the way of being lithographically formed pattern and ion implanting, using photoetching and ion etching
Mode forms square hole layer, and germanium nanometer film layer is formed by the way of wet method HF etchings, is received by shifting the formation germanium on PEN substrates
Rice film is respectively formed top zinc oxide gate dielectric layer finally by the mode of photoetching and magnetron sputtering and source and drain grid is transparent
Electrode layer.Complete the preparation of transistor.
A kind of germanium nanometer film flexibility homogenous medium layer top bottom double-gate structure transistor, prepares germanium nanometer film on PEN substrates,
Using ito film as the gate electrode of top and bottom, grid oxide layers of the ZnO as top and bottom, to realize at top and bottom
Portion's grid is carried out at the same time driving to transistor, generates higher control driving capability, and single-groove road double-gate structure, which has, widely answers
With.
Transistor is prepared in PEN plastic supporting bases, the flexural property of device is realized, is compared to traditional silicon substrate in addition,
The ghost effect of device is can greatly improve, working frequency and response speed is improved, the crystal under flexuosity may be implemented
The normal work of pipe increases substantially the control ability of grid, realizes and is widely applied on intelligently wearing flexible electronic product.
The main operational principle of the flexibility bottom gate homogenous medium layer film transistor is by upper and lower two gate electrodes
Upper addition bias can form electron inversion floor, as the conducting channel of device, device in source and drain doping area in place of gate oxide
Part is connected, and bias is then added between source-drain electrode, and device will start to work, i.e., by adjusting grid voltage come controller
Whether the conducting of part, the electric current between source and drain is controlled by controlling the voltage between source and drain.Further, since upper and lower two grid electricity
The package action of pole makes grid have a stronger control ability for channel current, and control ability is to reducing under same grid voltage
It is one times strong, and flexible substrate can reduce the ghost effect of traditional silicon substrate substrate MOS FTT transistors, and can be different curved
It works under Qu Chengdu, is provided for the large-scale integrated of high-performance flexible circuit and the extensive use of wearable electronic
It may.
Attached drawing 2 is every to be marked in figure, to 1 explanation of attached drawing：1 is PEN flexible substrates, and 2 be the transparent grid in the bottoms ITO
Pole, 3 be zinc oxide bottom gate dielectric layer, and 4 be germanium nanometer film, and 5 be the aperture layer on germanium film, and 6 leak doped region for N-shaped, and 7 be zinc oxide
Top gate dielectric layer, 8 be N-shaped source dopant region, and 9 be transparent source electrode, and 10 be ITO top transparent gate electrodes, and 11 is saturating for ITO
Bright drain electrode.
Attached drawing 3 be invention fundamental diagram, apply in two gate electrodes at the top and bottom of ITO certain bias it
Afterwards, by the ITO conductive films of top and bottom, the ITO layer in top and bottom generates certain voltage, when the voltage of application
When smaller or no-bias, germanium nanometer thin film layer due to not no inversion layer generation, even if adding voltage between source and drain, source and drain
Between will not generate electric current, device shutdown.When voltage is sufficiently large, germanium nanometer thin film layer will be on the surface contacted with grid oxide layer
Place generates electron inversion layer, and hollow more germanium nano thin-films two surfaces up and down of living in caves of script crystal will generate electron number and be more than
The surface inversion regime of hole number, this region are referred to as the channel region of device, then, are biased in the source-drain electrode of n-type doping, meeting
Generate the electric current between source and drain, break-over of device.Device in the present invention has higher integrated level, there is more broad range of answer
With.In addition, the present invention is integrated in the transistor device in plastic supporting base, when plastic supporting base is bent, it can still meet device
The normal work of part, can be in intelligent wearing, and artificial skin, biologic medical, photoelectric device etc. are obtained and more widely answered
With.
Specific manufacture craft is as follows
K. it selects PEN flexible materials as substrate, first puts PEN into the beaker for filling acetone soln, then super
It is cleaned 5 minutes in sound wave washer, it then will in ultrasonic cleaner by the PEN cleaned with acetone using aqueous isopropanol
Acetone cleans up, and obtains more clean substrate.
L. 200nm thickness ito film and 100nm thickness ZnO bottom dielectric grid layer films are plated on PEN substrates using magnetron sputtering.
M. GOI materials are selected, are cleaned using acetone in ultrasonic cleaner, acetone is then cleaned using isopropanol
Residue dries up GOI.
N. 1813 positive photo glues are coated on the surfaces GOI, and uses sol evenning machine, setting rotating speed is 4000rpm, rotation time
For 30s, photoresist is got rid of uniformly, then carries out being lithographically formed specific doped region using litho machine and the mask plate made
Pattern then carries out N-type injection by the way of ion implanting, and parameter is that Implantation Energy is 40Kev, dosage 4*1015cm2,
It generates source and drain doped region and after rapid thermal annealing 10s, photoresist is removed in acetone soln under 750 DEG C of temperature condition.
O. according to ready-made label on mask plate, by the square hole of spacing 5um arrangements in source and drain doping area and mask plate
Layer carries out alignment photoetching, the small aperture layer of square of spacing 5um arrangements is formed after development on GOI, then using ion etching
Mode removes the silicon on square aperture.
P. 3:In 1 HF solution, ready-made GOI before being put into, the oxygen buried layer after two hours on GOI will be corroded dry
Only, subsequent germanium nanometer film layer will fall off, and germanium nanometer film layer is adhered to the flexible PEN substrates for having plated film, drying.
Q. gluing in the germanium nanometer film on being transferred to PEN, according in square aperture layer after being got rid of uniformly with sol evenning machine
Label carry out alignment photoetching, form the grid of transistor, then by the way of ion etching, respectively by germanium nanometer film and
The gate oxide film layer etching plated, Ohmic contact is formed with conductive ITO layer.
R. after going photoresist then to carry out spin coating to the device on PEN, alignment photoetching, shape are carried out according to the label of grid
At the pattern of top gate dielectric layer.
S. last, magnetron sputtering is carried out on the pattern of formation, the gate medium at the top of the ZnO that top grid plates 100nm thickness
Layer.
T. it is directed at photoetching after going photoresist then to carry out gluing to the flexible device for forming top gate dielectric layer, forms top-gated
With the photoengraving pattern of source-drain electrode, the ITO top grids and source-drain electrode of 200nm thickness are formed by the way of magnetron sputtering
Layer, after removing photoresist, the preparation of device is completed.
Claims (4)
1. a kind of germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor, characterized in that structure is followed successively by PEN from the bottom to top
Plastic supporting base, tin indium oxide ITO bottom gate thin films layer, zinc oxide gate dielectric layer, the germanium nanometer film of n-type doping, ITO source-drain electrodes
Layer, top zinc oxide gate dielectric layer and top grid oxide layer, the germanium nanometer film of the n-type doping are formed in germanium nanometer film
Symmetrical N doped regions at two, are source electrode above N doped regions at one, are drain electrode above another place N doped regions.
2. germanium nanometer film flexible and transparent type top as described in claim 1 bottom double gate thin-film transistor, characterized in that in top gate
Bias is added between oxygen layer, ITO bottom gate thin film layers, doped region can form electron back in place of gate oxide below source and drain grade
Type layer, as the conducting channel of device, break-over of device then adds bias between source-drain electrode, and device will start to work.
3. a kind of germanium nanometer film flexible and transparent type top bottom double gate thin-film transistor preparation method, characterized in that on PEN substrates according to
It is secondary to prepare ITO bottom gate thin films layer, zinc oxide gate dielectric layer, the germanium nanometer film of n-type doping, ITO source-drain electrodes layer, top oxidation
Zinc gate dielectric layer and top grid oxide layer, using ito film as the gate electrode of top and bottom, zinc oxide film is used as top and bottom
The grid oxide layer in portion is carried out at the same time driving in top and bottom grid to realize to transistor；The germanium nanometer film of the n-type doping
It is that symmetrical N doped regions at two are formed in germanium nanometer film, N doped regions top is source electrode at one, is above another place N doped regions
Drain electrode.
4. germanium nanometer film flexible and transparent type top as claimed in claim 3 bottom double gate thin-film transistor preparation method, characterized in that
Further the specific preparation process in refinement ground is as follows：
A. it selects PEN flexible materials as substrate, first puts PEN into the beaker for filling acetone soln, then in ultrasonic wave
Cleaned 5 minutes in washer, then using aqueous isopropanol by the PEN cleaned with acetone in ultrasonic cleaner by acetone
It cleans up, obtains more clean substrate；
B. ito film and zinc oxide bottom dielectric grid layer film are plated on PEN substrates using magnetron sputtering；
C. GOI materials are selected, are cleaned using acetone in ultrasonic cleaner, acetone residue is then cleaned using isopropanol
Object dries up GOI；
D. photoresist is coated on the surfaces GOI, and is got rid of photoresist uniformly using sol evenning machine, then use litho machine and made
Mask plate carry out being lithographically formed specific doped region pattern, N-type injection, generating source are then carried out by the way of ion implanting
Leakage doped region after rapid thermal annealing, removes photoresist under 750 DEG C of temperature condition in acetone soln；
E. according to ready-made label on mask plate, by the square aperture layer of spacing 5um arrangements in source and drain doping area and mask plate into
Row alignment photoetching forms the small aperture layer of square of spacing 5um arrangements, then by the way of ion etching on GOI after development
By the silicon removal on square aperture；
F. 3:In 1 HF solution, be put into before ready-made GOI, the oxygen buried layer after two hours on GOI will be corroded totally, with
Germanium nanometer film layer will fall off afterwards, and germanium nanometer film layer is adhered to the flexible PEN substrates for having plated film, drying；
G. gluing in the germanium nanometer film on being transferred to PEN, according to the mark in square aperture layer after being got rid of uniformly with sol evenning machine
It remembers row alignment photoetching into, forms the grid of transistor, then by the way of ion etching, by germanium nanometer film and plate respectively
Gate oxide film layer etching, form Ohmic contact with conductive ITO layer；
H. after going photoresist then to carry out spin coating to the device on PEN, alignment photoetching is carried out according to the label of grid, forms top
The pattern of portion's gate dielectric layer；
I. last, magnetron sputtering is carried out on the pattern of formation, the gate dielectric layer at the top of top grid plated zinc oxide；
J. it is directed at photoetching after going photoresist then to carry out gluing to the flexible device for forming top gate dielectric layer, forms top-gated and source
The photoengraving pattern of drain electrode forms ITO top grids and source-drain electrode layer, after removing photoresist, device by the way of magnetron sputtering
The preparation of part is completed.
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| CN109166913A (en) * | 2018-08-31 | 2019-01-08 | 天津大学 | Germanium nanometer film flexible metal type top bottom double gate thin-film transistor and preparation method thereof |
| CN109326678A (en) * | 2018-10-11 | 2019-02-12 | 西安电子科技大学 | Flexible molybdenum disulfide phototransistor and preparation method thereof |
| CN111029402A (en) * | 2019-11-14 | 2020-04-17 | 天津大学 | Flexible bottom gate thin film transistor of zirconium-titanium oxide gate dielectric layer and manufacturing method thereof |
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