CN114078765A - 半导体装置的形成方法 - Google Patents
半导体装置的形成方法 Download PDFInfo
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- CN114078765A CN114078765A CN202110782913.3A CN202110782913A CN114078765A CN 114078765 A CN114078765 A CN 114078765A CN 202110782913 A CN202110782913 A CN 202110782913A CN 114078765 A CN114078765 A CN 114078765A
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本发明说明一种半导体装置的方法。方法包括形成鳍状结构于基板的第一侧上,形成源极/漏极区以与鳍状结构相邻,形成第一源极/漏极接点结构于基板的第一侧上以接触源极/漏极区,并形成盖结构于第一源极/漏极接点结构上。方法还包括经由盖结构移除第一源极/漏极接点结构的一部分以形成气隙,并形成第二源极/漏极接点结构于基板的第二侧上以接触源极/漏极区。第二侧与第一侧相对。
Description
技术领域
本发明实施例涉及背侧电源轨半导体装置,更特别涉及采用气隙降低背侧电源轨半导体装置的电容。
背景技术
随着半导体技术的进展,对更高储存能力、更快处理系统、更高效能、与更低成本的需求也增加。为符合这些需求,半导体产业持续缩小半导体装置如金属氧化物半导体场效晶体管(含平面金属氧化物半导体场效晶体管与鳍状场效晶体管)的尺寸。尺寸缩小亦增加半导体制造制程的复杂度。
发明内容
在一些实施例中,半导体装置的形成方法包括:形成鳍状结构于基板的第一侧上;形成源极/漏极区以与鳍状结构相邻;形成第一源极/漏极接点结构于基板的第一侧上并接触源极/漏极区;以及形成盖结构于第一源极/漏极接点结构上。方法还包括经由盖结构移除第一源极/漏极接点结构的一部分,以形成气隙;以及形成第二源极/漏极接点结构于基板的第二侧上并接触源极/漏极区。第二侧与第一侧相对。
在一些实施例中,半导体装置的形成方法包括:形成鳍状结构于基板的第一侧上;形成第一源极/漏极区与第二源极/漏极区以与鳍状结构的两端相邻;在基板的第一侧上形成第一源极/漏极接点结构以接触第一源极/漏极区,并形成第二源极/漏极接点结构以接触第二源极/漏极区;形成第一盖结构于第一源极/漏极接点结构上,并形成第二盖结构于第二源极/漏极接点结构上。方法还包括经由第二盖结构移除第二源极/漏极接点结构的一部分,以形成气隙;以及形成第三接点结构于基板的第二侧上并接触第二源极/漏极区。第二侧与第一侧相对。
在一些实施例中,半导体装置包括:鳍状结构,位于基板的第一侧上;第一源极/漏极区与第二源极/漏极区,与鳍状结构的两端相邻;第一源极/漏极接点结构,接触第一源极/漏极区;第一盖结构,位于第一源极/漏极接点结构上;第二盖结构,位于第二源极/漏极区上;气隙,位于第二盖结构与第二源极/漏极区之间;以及第二源极/漏极接点结构,接触基板的第二侧上的第二源极/漏极区。第二侧与第一侧相对。
附图说明
图1A至图1C是一些实施例中,背侧电源轨半导体装置的等角图与多种剖视图。
图2A至图2D是一些实施例中,采用气隙减少电容的多种背侧电源轨半导体装置的剖视图。
图3是一些实施例中,采用气隙减少电容的背侧电源轨半导体装置的制作方法的流程图。
图4至图13是一些实施例中,采用气隙减少电容的背侧电源轨半导体装置在制作制程的多种阶段的剖视图。
其中,附图标记说明如下:
B,C,D:区域
B-B:剖线
100,200-1,200-2:背侧电源轨半导体装置
102:场效晶体管
103:背侧电源轨
104:背侧内连线结构
105:前侧电源轨
108:鳍状结构
110A,110A*:第一源极/漏极区
110A-0,110B-0:第二虚置外延层
110A-1,110B-1:第一外延子区
110A-2,110B-2:第二外延子区
110B,110B*,110B**:第二源极/漏极区
112:栅极结构
114:前侧内连线结构
116:栅极间隔物
122:半导体层
124:第一蚀刻停止层
126,226-1,226-2:气隙
126h,226-1h,226-2h:垂直尺寸
126w,226-1w,226-2w:水平尺寸
127:内侧间隔物结构
128A,128B:硅化物层
130A,130B:金属接点
132A:第一源极/漏极接点结构
132B:第二源极/漏极接点结构
134:栅极盖结构
136A,136A*:第一盖结构
136B,136B*:第二盖结构
138:第二蚀刻停止层
140:前侧层间介电层
142:密封介电结构
144:衬垫层
146:背侧层间介电层
148:第三接点结构
150:阻障层
242:密封介电层
300:方法
310,320,330,340,350,360:步骤
406:基板
406S1:第一侧
406S2:第二侧
452A,452B,842:开口
554:第一虚置外延层
554t:厚度
554w:宽度
具体实施方式
搭配图式的详细说明有利于理解本发明实施例。实施例将搭配图式说明。在图式中,类似标号通常指的是相同、功能类似、及/或结构类似的单元。
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例是用以简化本发明内容而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外构件而非直接接触的实施例。此外,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
应注意说明书中“一个实施例”、“实施例”、“示例实施例”表示所述实施例可包括特定结构或特性,但每一实施例不一定都包括特定的结构或特性。此外,这些用语不一定表示相同实施例。此外,当实施例描述特定的结构或特性时,本技术领域中具有通常知识者能结合其他实施例以实现这些结构或特性,无论是否明确说明。
应理解的是,此处的措词或用语的目的为说明而非限制,因此本技术领域中具有通常知识者可依此处说明解释下述说明的措词或用语。
在一些实施例中,用语“大约”和“基本上”指的是在5%之内变化的给定数值(比如数值±1%、±2%、±3%、±4%、或±5%)。这些数值仅用于举例而非局限本发明实施例。用语“大约”和“基本上”指的数值%可由本技术领域中具有通常知识者依此处教示的内容变化。
随着对更低能耗、更高效能、与够小面积的半导体装置的需求增加,可实施背侧电源轨于半导体装置中,以减少装置面积与金属内连线长度,因此可减少寄生电容、减少寄生电阻、并改善装置效能。举例来说,背侧电源轨可改善进阶技术节点所用的电源输送网络效能。背侧电源轨半导体装置可具有前侧源极/漏极接点结构与内连线结构于前侧,以及背侧缘及/漏极接点结构与内连线结构于背侧,以减少装置面积、寄生电容、与电阻,并改善装置效能。举例来说,前侧源极/漏极接点结构与内连线结构可连接背侧电源轨半导体装置的漏极区至前侧电源轨。背侧源极/漏极接点结构与内连线结构可连接背侧电源轨半导体装置的源极区至背侧电源轨。虽然背侧电源轨半导体装置的源极区连接至虚置前侧源极/漏极接点结构,但其可连接至背侧源极/漏极接点结构。虚置前侧源极/漏极接点结构未连接至前侧内连线结构或前侧电源轨,但会诱发寄生电容于背侧电源轨半导体装置的虚置前侧源极/漏极接点结构与栅极结构之间。寄生电容可劣化背侧电源轨半导体装置的装置效能。
本发明多种实施例提供背侧电源轨半导体装置的形成方法,其采用气隙降低电容。在一些实施例中,背侧电源轨半导体装置可具有第一源极/漏极区与第二源极/漏极区以与基板的前侧上的鳍状结构的两端相邻。第一源极/漏极接点结构与第二源极/漏极接点结构各自具有金属接点与硅化物层,以分别接触第一源极/漏极区与第二源极/漏极区。通过穿过第一源极/漏极接点结构上的第一盖结构的第一内连线结构,第一源极/漏极接点结构可连接至前侧电源轨。可经由第二源极/漏极区上的第二盖结构中的开口,移除第二源极/漏极接点结构。在移除第二源极/漏极接点结构之后,可形成气隙于第二盖结构与第二源极/漏极区之间。在一些实施例中,可经由开口移除第二源极/漏极接点结构的金属接点。在一些实施例中,可经由开口移除第二源极/漏极接点结构的金属接点与硅化物层。在一些实施例中,可形成密封介电结构于开口中,以密封第二盖结构与第二源极/漏极区之间的气隙。在一些实施例中,在形成密封介电结构于开口中十,可形成密封介电层于气隙中。在一些实施例中,气隙可降低背侧电源轨半导体装置的栅极结构与第二源极/漏极区之间的寄生电容。在一些实施例中,由于采用气隙降低电容,背侧电源轨半导体装置的装置效能可改善约3%至约5.5%。
图1A显示一些实施例中,背侧电源轨半导体装置100的等角图,其采用气隙126降低电容。背侧电源轨半导体装置100可包含场效晶体管102。第一内连线结构(亦可视作前侧内连线结构114)可连接场效晶体管102的第一源极/漏极区至前侧电源轨105。第二内连线结构(亦可视作背侧内连线结构104)可连接场效晶体管102的第二源极/漏极区至背侧电源轨103。图1B显示一些实施例中,背侧电源轨半导体装置100沿着图1A的剖线B-B的剖视图。图1C显示一些实施例中,图1B的区域C的放大图。在一些实施例中,图1A至图1C显示集成电路布局的一部分,其中鳍状结构与栅极结构可与图1A至图1C所示的结构类似或不同。
如图1A至图1C所示,背侧电源轨半导体装置100可包含场效晶体管102,以及前侧内连线结构114与背侧内连线结构104分别连接至前侧电源轨105与背侧电源轨103。场效晶体管102可进一步包含鳍状结构108、第一源极/漏极区110A、第二源极/漏极区110B、栅极结构112、栅极间隔物116、与内侧间隔物结构127。
在一些实施例中,场效晶体管102可为p型鳍状场效晶体管或n型鳍状场效晶体管。用语“p型”关于掺杂p型掺质如硼的结构、层状物、及/或区域。用语“n型”关于掺杂n型掺质如磷的结构、层状物、及/或区域。虽然图1A至图1C显示一个鳍状场效晶体管,背侧电源轨半导体装置100可具有任何数目的鳍状场效晶体管。此外,背侧电源轨半导体装置100可经由其他结构构件(如导电通孔、导电线路、介电层、与钝化层,未图示以简化图式)整合至集成电路中。
场效晶体管102可形成于基板406的第一侧(如前侧)上,如图4至图10所示。在一些实施例中,基板406可包含半导体材料如硅。在一些实施例中,基板406可包含绝缘层上硅基板(如绝缘层上硅晶圆)。在一些实施例中,基板406可包含(i)半导体元素如锗;(ii)半导体化合物如碳化硅、砷化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、及/或III-V族半导体材料;(iii)半导体合金如硅锗、碳化硅锗、锗锡、硅锗硅、磷砷化镓、磷化镓铟、砷化镓铟、磷砷化镓铟、砷化铝铟、及/或砷化铝镓;(iv)绝缘层上硅锗结构;(v)绝缘层上锗结构;或(vi)上述的组合。此外,可掺杂基板406,端视设计需求(如p型基板或n型基板)而定。在一些实施例中,基板406可掺杂p型掺质(如硼、铟、铝、或镓)或n型掺质(如磷或砷)。
如图1B所示,背侧电源轨半导体装置100可包含鳍状结构108,其沿着X轴延伸穿过场效晶体管102。鳍状结构108可包含半导体层122的堆叠,而半导体层122可为纳米片或纳米线。每一半导体层122可形成场效晶体管102的栅极结构112之下的通道区。此处公开的鳍状结构的图案化方法可为任何合适方法。举例来说,鳍状结构的图案化方法可采用一或多道光微影制程,包括双重图案化制程或多重图案化制程。双重图案化制程或多重图案化制程结合光微影与自对准制程,其产生的图案间距小于采用单一的直接光微影制程所得的图案间距。举例来说,形成牺牲层于基板上,并采用光微影制程图案化牺牲层。采用自对准制程以沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层,并可采用保留的间隔物以图案化鳍状结构。
在一些实施例中,半导体层122包含的半导体材料可与基板406的材料类似或不同。在一些实施例中,每一半导体层122可包含硅而不具有任何实质上的锗,或包含硅锗而锗浓度为约5原子%至约50原子%(其余的原子%为硅)。半导体层122的半导体材料可未掺杂,或在外延成长制程时采用(i)p型掺质如硼、铟、或镓及/或(ii)n型掺质如磷或砷进行原位掺杂。虽然图1B所示的场效晶体管102所用的半导体层122为三层,但场效晶体管102可包含任何数目的半导体层122。
如图1A至图1C所示,第一源极/漏极区110A与第二源极/漏极区110B可与鳍状结构108的两端相邻。在一些实施例中,第一源极/漏极区110A与第二源极/漏极区110B可具有任何几何形状如多边形、椭圆形、或圆形。第一源极/漏极区110A与第二源极/漏极区110B可包含外延成长的半导体材料。在一些实施例中,外延成长的半导体材料与基板406的材料相同。在一些实施例中,外延成长的半导体材料不同于基板406的材料。在一些实施例中,第一源极/漏极区110A与第二源极/漏极区110B所用的外延成长的半导体材料可彼此相同或不同。外延成长的半导体材料可包含(i)半导体材料如硅或锗;(ii)半导体化和物材料如砷化镓或砷化铝镓;或(iii)半导体合金如硅锗或磷砷化镓。
在一些实施例中,第一源极/漏极区110A与第二源极/漏极区110B可为n型或p型。在一些实施例中,n型的第一源极/漏极区110A与第二源极/漏极区110B可包含硅,且可在外延成长制程时采用n型掺质如磷或砷进行原位掺杂。在一些实施例中,n型的第一源极/漏极区110A与第二源极/漏极区110B可具有多个n型外延的鳍状子区,其掺杂浓度及/或外延成长的制程条件可彼此不同。在一些实施例中,p型的第一源极/漏极区110A与第二源极/漏极区110B可包含硅锗,且可在外延成长制程时采用p型掺质如硼、铟、或镓进行原位掺杂。在一些实施例中,p型的第一源极/漏极区110A与第二源极/漏极区110B可具有多个含硅锗的子区,其掺杂浓度、外延成长的制程条件、及/或锗相对于硅的相对浓度可彼此不同。以图1B为例,第一源极/漏极区110A可包含第一外延子区110A-1与第二外延子区110A-2。在一些实施例中,第一外延子区110A-1沿着X轴的宽度可为约10nm至约30nm,而沿着Z轴的厚度可为约5nm至约10nm。在一些实施例中,第二外延子区110A-2沿着X轴的宽度可为约10nm至约30nm,而沿着Z轴的厚度可为约30nm至约50nm。
如图1A及图1B所示,鳍状结构108可为场效晶体管102所用的载流结构。场效晶体管102的通道区可形成于个别的鳍状结构108位于栅极结构112之下的部分中。第一源极/漏极区110A与第二源极/漏极区110B可作为场效晶体管102的源极/漏极区。
如图1A至图1C所示,栅极结构112可为多层结构,且可包覆鳍状结构108的半导体层122。在一些实施例中,栅极结构112的一或多层可分别包覆鳍状结构108的每一半导体层122,而栅极结构112可视作全绕式栅极结构,而场效晶体管102可视作“全绕式栅极场效晶体管”或“全绕式栅极鳍状场效晶体管”。
栅极结构112可包含栅极介电层与栅极以包覆半导体层122。栅极介电层可包覆每一半导体层122,因此可使半导体层122彼此电性隔离并与导电栅极电性隔离,以在操作场效晶体管102时避免栅极结构112与半导体层122之间的短接。在一些实施例中,栅极介电层可包含界面层与高介电常数层。在半导体装置结构与制造制程的领域中,高介电常数指的是大于氧化硅的介电常数(如大于约3.9)。在一些实施例中,界面层可包含氧化硅。在一些实施例中,高介电常数层可包含氧化铪、氧化锆、或任何合适的高介电常数的介电材料。在一些实施例中,栅极可包含栅极阻障层、栅极功函数层、与栅极金属填充层。一或多个栅极阻障层、栅极功函数层、与栅极金属填充层可包覆每一半导体层122。在一些实施例中,栅极可包含钛、钽、氮化钛、氮化钽、铝、铜、钨、钴、或其他合适的导电材料。
如图1B及图1C所示,栅极间隔物116可沿着栅极结构112的侧壁,而内侧间隔物结构127可位于栅极结构112的部分与第一源极/漏极区110A(及第二源极/漏极区110B)之间。每一栅极间隔物116与内侧间隔物结构127可包含介电材料,比如氧化硅、氮氧化硅、氮化硅、碳氧化硅、碳氮化硅、碳氮氧化硅、或上述的组合。在一些实施例中,每一栅极间隔物116与内侧间隔物结构127可包含单层或多层的绝缘材料。在一些实施例中,栅极间隔物116可隔离栅极结构112与相邻的源极/漏极接点结构。内侧间隔物结构127可隔离栅极结构112与第一源极/漏极区110A,并隔离栅极结构112与第二源极/漏极区110B。
如图1A至图1C所示,背侧电源轨半导体装置100可进一步包含前侧源极/漏极接点结构如第一源极/漏极接点结构132A、虚置的硅化物层128B、气隙126、第一蚀刻停止层124、栅极盖结构134、第一盖结构136A、第二盖结构136B、密封介电结构142、前侧内连线结构114、第二蚀刻停止层138、前侧层间介电层140、衬垫层144、背侧层间介电层146、背侧接点结构如第三接点结构148、阻障层150、与背侧内连线结构104。如图1A至图1C所示,前侧源极/漏极接点结构如第一源极/漏极接点结构132A与前侧内连线结构114可连接第一源极/漏极区110A至前侧电源轨105。背侧接点结构如第三接点结构148与背侧内连线结构104可连接第二源极/漏极区110B至背侧电源轨103。在一些实施例中,前侧电源轨105与背侧电源轨可包含背侧电源轨半导体装置100所用的电源线与地线。
前侧源极/漏极接点结构如第一源极/漏极接点结构132A可包含硅化物层128A与金属接点130A。硅化物层128A可包含金属硅化物,并降低场效晶体管102的第一源极/漏极区110A与金属接点130A之间的接点电阻。形成金属硅化物于n型源极/漏极区上所用的金属例子,可包含钛、铬、钽、钼、锆、铪、钪、钇、钬、铽、钆、镏、镝、铒、镱、或其他合适金属。形成金属硅化物于p型源极/漏极区上所用的金属例子,可包含镍、钴、锰、钨、铁、铑、钯、钌、铂、铱、锇、或其他合适金属。在一些实施例中,硅化物层128A沿着Z轴的厚度可为约1nm至约10nm。在一些实施例中,虚置的硅化物层128B可与硅化物层128A具有相同的金属硅化物,且厚度可为约1nm至约10nm。
金属接点130A可包含金属如钨、钌、钴、铜、钛、氮化钛、钽、氮化钽、钼、镍、金属合金、或其他合适金属。在一些实施例中,金属接点130A沿着Z轴的厚度可为约10nm至约50nm。
如图1B及图1C所示,气隙126可位于第二盖结构136B与第二源极/漏极区110B之间。气隙126的形成方法可为移除第二源极/漏极区110B上的虚置金属接点,并填入空气。在一些实施例中,置换金属接点的气隙126可减少栅极结构112与第二源极/漏极区110B之间的重叠面积,进而减少栅极结构112与第二源极/漏极区110B之间的寄生电容。采用气隙降低电阻,可使背侧电源轨半导体装置100的装置效能改善约3%至约5.5%。在一些实施例中,气隙126沿着X轴的水平尺寸126w(如宽度)可为约5nm至约30nm。气隙126沿着Z轴的垂直尺寸126h(如高度)可为约5nm至约50nm。在一些实施例中,垂直尺寸126h与水平尺寸126w之间的比例可为约0.1至约10。若垂直尺寸126h小于约5nm或比例小于约0.1,则无法改善背侧电源轨半导体装置100的装置效能。若垂直尺寸126h大于约50nm或比例大于约10,则无法适当地密封气隙126。此外,水平尺寸126w受限于相邻的栅极结构之间的距离,而垂直尺寸126h受限于周围结构。
栅极盖结构134可位于栅极结构112上,且设置以在背侧电源轨半导体装置100的制程时保护下方的结构及/或层状物。举例来说,栅极盖结构134在形成前侧源极/漏极接点结构于第一源极/漏极区110A与第二源极/漏极区110B之上时,可作为蚀刻停止层。栅极盖结构134可包含一或多种绝缘材料。在一些实施例中,绝缘材料可包含氧化硅、铪硅化物、碳氧化硅、氧化铝、锆硅化物、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、碳氮氧化硅、硅、氮化锆、碳氮化硅、或其他合适材料。在一些实施例中,栅极结构134沿着Z轴的厚度可为约0nm至约50nm。在一些实施例中,栅极盖结构134沿着X轴的宽度可为约5nm至约30nm。在一些实施例中,背侧电源轨半导体装置100可不具有栅极盖结构。
第一盖结构136A可位于前侧源极/漏极接点结构如第一源极/漏极接点结构132A上,而第二盖结构136B可位于气隙126上。第一盖结构136A与第二盖结构136B可设置以在形成前侧内连线结构114与密封介电结构142时,保护相邻的结构如栅极结构112。在一些实施例中,第一盖结构136A与第二盖结构136B可包含绝缘材料如氧化硅、碳氧化硅、氧化铝、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、碳氮氧化硅、氮化锆、碳氮化硅、或其他合适材料。在一些实施例中,第一盖结构136A与第二盖结构136B可包含相同的绝缘材料。在一些实施例中,栅极盖结构134包含的绝缘材料,可不同于第一盖结构136A与第二盖结构136B的材料,且可具有不同的蚀刻选择性以进一步保护相邻结构(如栅极结构112)。用语“蚀刻选择性”指的是两种不同材料在相同蚀刻条件下的蚀刻速率的比例。在一些实施例中,栅极盖结构134与第一盖结构136A(及第二盖结构136B)之间的蚀刻选择性可为约15至约20。举例来说,栅极盖结构134可包含氮化硅,而第一盖结构136A与第二盖结构136B可包含氧化硅。在一些实施例中,第一盖结构136A与第二盖结构136B沿着Z轴的厚度可为约0nm至约50nm,而沿着X轴的宽度可为约5nm至约30nm。在一些实施例中,背侧电源轨半导体装置100可不具有盖结构于前侧源极/漏极接点结构如第一源极/漏极接点结构132A上。
如图1A至图1C所示,前侧内连线结构114可连接至前侧源极/漏极接点结构如第一源极/漏极接点结构132A,并延伸穿过第一盖结构136A、第二蚀刻停止层138、与前侧层间介电层140。前侧内连线结构114可包含金属如钨、钌、钴、铜、钛、氮化钛、钽、氮化钽、钼、镍、金属合金、或其他合适金属。在一些实施例中,前侧内连线结构114沿着Z轴的厚度可为约1nm至约50nm。
密封介电结构142可延伸穿过第二盖结构136B、第二蚀刻停止层138、与前侧层间介电层140,并延伸至密封气隙126。密封介电结构142可包含绝缘材料如氧化硅、碳氧化硅、氧化铝、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、碳氮氧化硅、氮化锆、碳氮化硅、或其他合适材料。在一些实施例中,密封介电结构142沿着Z轴的厚度可为约10nm至约50nm,而沿着X轴的宽度可为约5nm至约30nm。在一些实施例中,密封介电结构142的宽度与第二盖结构136B的宽度的比例,可为约0.3至约0.6。若密封介电结构142的宽度小于约5nm或比例小于约0.3,则可能无法移除第二源极/漏极区110B上的金属接点,而无法形成气隙126与密封介电结构142。若密封介电结构142的宽度大于约15nm或比例大于约0.6,则密封介电结构142可能不密封气隙126而填入气隙126。在一些实施例中,密封介电结构142可具有与气隙126相邻的凹陷表面。由于密封介电结构142的沉积制程,凹陷表面可为圆形或三角形的表面。
可形成第一蚀刻停止层124于栅极间隔物116的侧壁之上,以及第一源极/漏极区110A与第二源极/漏极区110B之上。第一蚀刻停止层124可保护未接触前侧源极/漏极接点结构如第一源极/漏极接点结构132A的第一源极/漏极区110A与第二源极/漏极区110B的部分及/或栅极结构112。举例来说,可在形成前侧源极/漏极接点结构如第一源极/漏极接点结构132A时提供此保护。在一些实施例中,第一蚀刻停止层124可包含氮化硅、氧化硅、氮氧化硅、碳化硅、或上述的组合。第二蚀刻停止层138可形成于栅极盖结构134、第一盖结构136A、与第二盖结构136B上。在一些实施例中,第二蚀刻停止层138可包含介电材料如氧化铝,以在形成前侧内连线结构时保护下方结构。
前侧层间介电层140可位于第一蚀刻停止层124上。前侧层间介电层140可包含介电材料,以隔离前侧内连线结构114与其他内连线结构。介电材料的沉积方法可为适于沉积可流动的介电材料(比如可流动的氧化硅、可流动的氮化硅、可流动的氮氧化硅、可流动的碳化硅、或可流动的碳氧化硅)的方法。在一些实施例中,介电材料可为氧化硅。在一些实施例中,前侧层间介电层140沿着Z轴的厚度可为约10nm至约25nm。背侧层间介电层146可位于鳍状结构108另一侧(如背侧)上,以与前侧源极/漏极接点结构如第一源极/漏极接点结构132A相对。背侧层间介电层146包含的介电材料可与前侧层间介电层140类似,且可提供背侧内连线结构104与其他背侧内连线结构之间的隔离。
衬垫层144可位于背侧层间介电层146与第一源极/漏极区110A(及第二源极/漏极区110B)之间。在一些实施例中,衬垫层144在形成背侧层间介电层146时,可保护栅极结构112、第一源极/漏极区110A、与第二源极/漏极区110B。背侧接点结构如第三接点结构148可包含硅化物层,其可与硅化物层128A及128B类似或不同。在一些实施例中,背侧接点结构如第三接点结构148可减少背侧内连线结构104与第二源极/漏极区110B之间的接点电阻。阻障层150可位于背侧内连线结构104与衬垫层144之间。在一些实施例中,阻障层150可避免金属自背侧内连线结构104扩散至背侧层间介电层146。
在一些实施例中,背侧电源轨半导体装置100可进一步包含其他结构,比如金属线路、金属通孔、与介电结构,以提供连接至集成电路布局的其他部分或与其他部分隔离。这些结构的细节未图示以使图式清楚并易于说明。
图2A显示一些实施例中,背侧电源轨半导体装置200-1的剖视图,其采用气隙226-1降低电容。图2B显示一些实施例中,图2A中的区域B的放大图。图2C显示一些实施例中,背侧电源轨半导体装置200-2的剖视图,其采用气隙226-2降低电容。图2D显示一些实施例中,图2C中的区域D的放大图。图2A至图2D与图1A至图1C中相同标号的单元如上所述。
如图2A及图2B所示,背侧电源轨半导体装置200-1可不包含虚置硅化物层于第二源极/漏极区110B上。由于不存在虚置硅化物层,气隙226-1的尺寸增加,且可进一步降低栅极结构112与第二源极/漏极区110B之间的寄生电容。在一些实施例中,气隙226-1沿着X轴的水平尺寸226-1w(如宽度)可为约5nm至约30nm。气隙226-1沿着Z轴的垂直尺寸226-1h(如高度)可为约10nm至约50nm。在一些实施例中,垂直尺寸226-1h与水平尺寸226-1w之间的比例可为约0.1至约10。
如图2C及图2D所示,背侧电源轨半导体装置200-2可具有密封介电层242位于气隙226-2中的第二源极/漏极区110B上。在沉积密封介电结构142时,密封介电层242可形成于第二源极/漏极区110B与第一蚀刻停止层124的表面上。在一些实施例中,密封介电层242在气隙226-2中的底部角落具有较大厚度。由于形成密封介电层242,可减少气隙226-2的尺寸并增加栅极结构112与第二源极/漏极区110B之间的寄生电容。在一些实施例中,气隙226-2沿着X轴的水平尺寸可为约5nm至约20nm。气隙226-2沿着Z轴的垂直尺寸226-2h(如高度)可为约5nm至约40nm。在一些实施例中,垂直尺寸226-2h与水平尺寸226-2w之间的比例可为约0.2至约8。在一些实施例中,背侧电源轨半导体装置200-1不含虚置硅化物层,且可在制作制程时具有密封介电层于气隙226-1中(未图示)。气隙226-1中的密封介电层亦可减少气隙226-1的尺寸,并增加栅极结构112与第二源极/漏极区110B之间的寄生电容。
图3是一些实施例中,制作背侧电源轨半导体装置100的方法300的流程图,其采用气隙126以降低电容。方法300不限于全绕式栅极场效晶体管,且可用于得利于采用气隙以降低电容的装置,比如平面场效晶体管、鳍状场效晶体管、或类似物。在方法300的多种步骤之间可进行额外制作步骤,且可省略这些步骤的内容以使说明清楚并易于说明。可在方法300之前、之中、及/或之后提供额外制程,且在此仅简述一或多个这些额外制程。此外,不需进行此处提供的所有步骤。另一方面,可同时进行一些步骤,或由图3所示的顺序以外的其他顺序进行一些步骤。在一些实施例中,可额外进行一或多个其他步骤,或将此处所述的步骤置换成一或多个其他步骤。为了说明目的,图3所示的步骤将搭配图4至图13所示的背侧电源轨半导体装置100的制作制程说明。图4至图13是背侧电源轨半导体装置100的剖视图。虽然图4至图13显示背侧电源轨半导体装置100的制作制程,其采用场效晶体管102中的气隙126以减少电容,但方法300可用于背侧电源轨半导体装置100、200-1、及200-2、以及其他背侧电源轨半导体装置中的其他场效晶体管。图4至图13与图1A至图1C中具有相同标号的单元如上所述。
在图3中,方法300一开始的步骤310形成鳍状结构于基板的第一侧上。以图4为例,可形成鳍状结构108于基板406的第一侧406S1上。在一些实施例中,基板406可为硅。鳍状结构108可包含半导体层122。在一些实施例中,半导体层122可包含硅。栅极结构112可包覆每一半导体层122。栅极间隔物116可形成于鳍状结构108上的栅极结构112的侧壁上。内侧间隔物结构127可与栅极结构112相邻,并位于半导体层122之间。栅极盖结构134可形成于栅极结构112上以保护栅极结构112。
鳍状结构108的形成方法可包含以交错设置的方式外延成长不同蚀刻选择性的半导体层。可移除交错的半导体层,并可形成内侧间隔物结构127与栅极结构112于半导体层122之间。形成鳍状结构108之后,可垂直蚀刻以形成开口452A及452B而与鳍状结构108的两端相邻。
在图3的步骤320中,可形成第一源极/漏极区与第二源极/漏极区以与鳍状结构的两端相邻。以图5及图6为例,可分别形成第一源极/漏极区110A*与第二源极/漏极区110B*于开口452A及452B中,以与基钣406的第一侧406S1上的鳍状结构108的两端相连。在一些实施例中,可形成虚置外延层于开口452A及452B中,以用于背侧连接至第二源极/漏极区110B*。
在形成第一源极/漏极区110A*与第二源极/漏极区110B*之前,可蚀刻开口452B并以遮罩层阻挡开口452A,并可外延成长第一虚置外延层554于延伸至基板406中的开口452B中。在一些实施例中,第一虚置外延层554沿着X轴的宽度554w可为约10nm至约30nm,而沿着Z轴的厚度554t可为约20nm至约50nm。在一些实施例中,第一虚置外延层554可包含硅锗,其锗浓度为约5原子%至约15原子%,而其他原子%为硅。在一些实施例中,在后续制程可将第一虚置外延层置换成背侧内连线结构。
形成第一虚置外延层554之后,可分别外延成长第二虚置外延层110A-0及110B-0于开口452A及452B中。在一些实施例中,第二虚置外延层110A-0及110B-0可包含硅锗,其锗浓度可为约20原子%至约35原子%,而其余原子%为硅。在一些实施例中,第二虚置外延层110A-0及110B-0沿着X轴的宽度可为约10nm至约30nm,且沿着Z轴的厚度可为约5nm至约10nm。在一些实施例中,第二虚置外延层110A-0及110B-0在移除基板406的后续制程时,可保护第一源极/漏极区110A与第二源极/漏极区110B。
第一外延子区110A-1及110B-1与第二外延子区110A-2及110B-2,可分别外延成长于第二虚置外延层110A-0与110B-0。在一些实施例中,第一外延子区110A-1及110B-1沿着X轴的宽度可为约10nm至约30nm,而沿着Z轴的厚度可为约5nm至约10nm。在一些实施例中,第二外延子区110A-2及110B-2沿着X轴的宽度可为约10nm至约30nm,而沿着Z轴的厚度可为约30nm至约50nm。在一些实施例中,第一外延子区110A-1及110B-1与第二外延子区110A-2及110B-2可包含硅锗,且可采用p型掺质进行原位掺杂以用于p型的第一源极/漏极区110A与第二源极/漏极区110B。在一些实施例中,第一外延子区110A-1及110B-1与第二外延子区110A-2及110B-2可包含硅,且可采用n型掺质进行原位掺杂以用于n型的第一源极/漏极区110A与第二源极/漏极区110B。
在形成虚置外延层与外延子区之后,第一源极/漏极区110A可包含第二虚置外延层110A-0、第一外延子区110A-1、与第二外延子区110A-2。第二源极/漏极区110B可包含第一虚置外延层554、第二虚置外延层110B-0、第一外延子区110B-1、与第二外延子区110B-2。
在图3的步骤330中,可形成第一源极/漏极接点结构以接触第一源极/漏极区,且可形成第二源极/漏极接点结构以接触第二源极/漏极区。以图7为例,第一源极/漏极接点结构132A(亦可视作前侧源极/漏极接点结构)可形成于图6所示的开口452A中,并接触第一源极/漏极区110A*。第二源极/漏极接点结构132B(亦可视作虚置源极/漏极接点结构)可形成于图6所示的开口452B中,并接触第二源极/漏极区110B*。在形成第一源极/漏极接点结构132A与第二源极/漏极接点结构132B之前可形成第一蚀刻停止层124,以保护不接触第一源极/漏极接点结构132A与第二源极/漏极接点结构132B的第一源极/漏极区110A与第二源极/漏极区110B的部分及/或栅极结构112。
形成第一源极/漏极接点结构132A与第二源极/漏极接点结构132B的方法,可包含移除第一源极/漏极区110A与第二源极/漏极区110B上的第一蚀刻停止层124的一部分,形成硅化物层128A及128B、沉积金属于开口452A及452B中、接着以化学机械研磨制程使栅极盖结构134、第一源极/漏极接点结构132A、与第二源极/漏极接点结构132B的上表面共平面。第一源极/漏极接点结构132A可包含硅化物层128A与金属接点130A,且可在后续制程中连接至内连线结构。第二源极/漏极接点结构132B可包含硅化物层128B与金属接点130B,且可不连接至任何内连线结构。如此一来,第二源极/漏极接点结构132B可视作虚置源极/漏极接点结构,而硅化物层128B可视作虚置的硅化物层,而金属接点130B可视作虚置的金属接点。在一些实施例中,硅化物层128A与虚置的硅化物层128B可包含相同的金属硅化物,而金属接点130A与虚置的金属接点130B可包含相同金属。
在图3的步骤340中,可形成第一盖结构于第一源极/漏极接点结构上,并可形成第二盖结构于第二源极/漏极接点结构上。以图7为例,可形成第一盖结构136A*于第一源极/漏极接点结构132A上,并可形成第二盖结构136B*于第二源极/漏极接点结构132B上。可回蚀刻第一源极/漏极接点结构132A与第二源极/漏极接点结构132B。可沉积盖介电材料于第一源极/漏极接点结构132A与第二源极/漏极接点结构132B上,接着以化学机械研磨制程使栅极盖结构134、第一盖结构136A*、与第二盖结构136B*的上表面共平面。在一些实施例中,第一盖结构136A*与第二盖结构136B*沿着Z轴的厚度可为约0nm至约50nm,而沿着X轴的宽度可为约5nm至约30nm。在一些实施例中,背侧电源轨半导体装置100可不具有盖结构于前侧源极/漏极接点结构如第一源极/漏极接点结构132A上。
在图3的步骤350中,可经由第二盖结构移除第二源极/漏极接点结构的一部分,以形成气隙。以图8及9为例,可经由第二盖结构136B*移除第二源极/漏极接点结构132B的一部分,以形成气隙126。移除第二源极/漏极接点结构132B的部分的方法,可包含形成开口842于第二盖结构136B*中、蚀刻第二源极/漏极接点结构132B的部分、并形成密封介电结构142于开口842中。在形成开口842之前,可毯覆性沉积第二蚀刻停止层138与前侧层间介电层140于栅极盖结构134、第一盖结构136A*、与第二盖结构136B*的上表面上,如图8所示。
毯覆性沉积第二蚀刻停止层138与前侧层间介电层140之后,可由图案化制程形成开口842。可沉积遮罩层于前侧层间介电层140上,并露出第二源极/漏极区110B上的区域以进行蚀刻制程。可蚀刻前侧层间介电层140、第二蚀刻停止层138、与第二盖结构136B*以形成开口842。在一些实施例中,蚀刻制程可包含多个步骤,且每一步骤可移除前侧层间介电层140、第二蚀刻停止层138、与第二盖结构136B*之一者。在一些实施例中,蚀刻制程可止于虚置的金属接点130B上。在一些实施例中,开口842沿着X方向的宽度可为约5nm至约15nm。
形成开口842之后,可蚀刻第二源极/漏极接点结构132B的部分以形成气隙126。如图8所示,可经由开口842蚀刻与移除第二源极/漏极接点结构132B的虚置的金属接点130B。在一些实施例中,虚置的金属接点130B的移除方法可为湿蚀刻制程。在一些实施例中,湿蚀刻制程包含的蚀刻剂可为多种浓度的硫酸、氯化氢、或过氧化氢。在一些实施例中,湿蚀刻制程的温度可为约25℃至约125℃。在一些实施例中,湿蚀刻制程可移除虚置的金属接点130B,但保留虚置的硅化物层128B,如图1A至图1C及图8所示。在一些实施例中,湿蚀刻制程可移除虚置的金属接点130B与虚置的硅化物层128B,如图2A及图2B所示。
蚀刻第二源极/漏极接点结构132B以形成气隙126之后,可形成密封介电结构142于开口842中。如图9所示,可形成密封介电结构142于图8所示的开口842中,以密封气隙126。在一些实施例中,密封介电结构142的形成方法可为沉积密封介电材料于开口842中,且沉积方法可为原子层沉积或其他合适的沉积方法。密封介电材料可包含绝缘材料,比如氧化硅、碳氧化硅、氧化铝、氮氧化铝、氧化锆、氧化铪、氧化钛、氧化锆铝、氧化锌、氧化钽、氧化镧、氧化钇、碳氮化钽、氮化硅、碳氮氧化硅、氮化锆、碳氮化硅、或其他合适材料。在一些实施例中,密封介电材料的沉积温度可为约100℃至约400℃。在一些实施例中,密封介电材料的沉积方法所采用的前驱物可包含硅烷与其他合适前驱物。密封介电材料的沉积速率可为约 至约且可沉积约5次沉积循环至30次沉积循环。在一些实施例中,沉积制程可形成密封介电结构142于开口842中,如图1A至图1C及图9所示。在一些实施例中,密封介电材料可沉积于开口842中的侧壁上,且可在开口842的中间处合并,进而形成凹陷表面以与气隙126相邻。在一些实施例中,沉积制程可在密封开口842之前,沉积密封介电材料层于气隙126中,因此形成密封介电结构142于开口842中并形成密封介电层242于气隙126中,如图2C及图2D所示。沉积密封介电结构142之后可进行化学机械研磨制程,使前侧层间介电层140与密封介电结构142的上表面共平面。
形成密封介电结构142之后,可形成前侧内连线结构114与前侧电源轨105。如图10所示,前侧内连线结构114可形成于第一盖结构136A中,以连接至前侧源极/漏极接点结构如第一源极/漏极接点结构132A。形成前侧内连线结构114的方法可包含图案化制程,以形成开口于前侧层间介电层140、第二蚀刻停止层138、与第一盖结构136A中,其与图案化形成开口842的制程类似。可沉积金属至开口中,以形成前侧内连线结构114。
在图3的步骤360中,可形成第三接点结构于基板的第二侧上,以接触第二源极/漏极区。第二侧与第一侧相对。以图11至图13为例,第三接点结构148(亦可视作背侧接点结构)可形成于基板406的第二侧406S2(如背侧)上。第二侧406S2可与第一侧406S1相对。在形成背侧接点结构如第三接点结构148之前,可接合背侧电源轨半导体装置100至基板406的第一侧406S1(如前侧)上的载板(未图示),以在基板406的第二侧406S2上进行后续制作制程。
将背侧电源轨半导体装置100接合至载板之后,可由蚀刻制程移除基板406,如图11所示。在一些实施例中,蚀刻制程可包含采用蚀刻剂如氯气、三氯化硼、与氧气的干蚀刻制程。蚀刻剂的流速可为约5sccm至约200sccm。干蚀刻制程的压力可为约1mTorr至约100mTorr,而电浆功率可为约50W至约250W。移除基板406之后可移除第二虚置外延层110A-0,如图11所示。一些实施例在移除基板406与第二虚置外延层110A-0时,由于蚀刻速率不同而不移除第一虚置外延层554与第二虚置外延层110B-0。举例来说,在移除含硅的基板406时,第一虚置外延层554与第二虚置外延层110A-0可包含硅锗而具有较低蚀刻速率,因此不会被移除。在移除第二虚置外延层110A-0时,第一虚置外延层554可包含不同锗浓度的硅锗与不同蚀刻速率,进而保护第二虚置外延层110B-0。
移除基板406与第二虚置外延层110A-0之后,可沉积衬垫层144与背侧层间介电层146,如图12所示。在一些实施例中,衬垫层144可在形成背侧层间介电层146时,保护栅极结构112、第一源极/漏极区110A、与第二源极/漏极区110B**。在一些实施例中,背侧层间介电层146的沉积方法,可为适于沉积可流动的介电材料的方法。在一些实施例中,背侧层间介电层146可包含可流动的氧化硅、可流动的氮化硅、可流动的氮氧化硅、可流动的碳化硅、或可流动的碳氧化硅。在一些实施例中,背侧层间介电层146可隔离场效晶体管102的背侧内连线结构104与其他相邻的装置及结构。
沉积衬垫层144与背侧层间介电层146之后,可移除第一虚置外延层554与第二虚置外延层110B-0。对p型的第一外延子区110B-1与第二外延子区110B-2而言,由于第二虚置外延层110B-0与p型的第一外延子区110B-1之间的蚀刻选择性类似,移除第一虚置外延层554与第二虚置外延层110B-0的步骤可能过蚀刻第一外延子区110B-1并移除第一外延子区110B-1。对n型的第一外延子区110B-1与第二外延子区110B-2而言,由于第二虚置外延层110B-0与n型的第一外延子区110B-1之间的蚀刻选择性较高,移除第一虚置外延层554与第二虚置外延层110B-0的步骤可止于第一外延子区110B-1。
移除第一虚置外延层554与第二虚置外延层110B-0之后,可形成第三接点结构148(亦视作背侧接点结构)于第二侧406S2上,如图13所示。在一些实施例中,背侧接点结构148可包含具有金属硅化物的硅化物层,其可与硅化物层128A即128B相同或不同。在一些实施例中,背侧接点结构如第三接点结构148可减少第二源极/漏极区110B与背侧内连线结构104之间的接点电阻。形成背侧接点结构如第三接点结构148之后,可形成阻障层150、背侧内连线结构104、与背侧电源轨103。
本发明的多种实施例可提供背侧电源轨半导体装置100、200-1、及200-2的形成方法,其分别采用气隙126、226-1、及226-2以降低电容。在一些实施例中,背侧电源轨半导体装置100可具有第一源极/漏极区110A与第二源极/漏极区110B,以与基板406的背侧如第二侧406S2上的鳍状结构108的两端相邻。可形成具有个别金属接点130A及130B与硅化物层128A及128B的第一源极/漏极接点结构132A与第二源极/漏极接点结构132B,以分别接触第一源极/漏极区110A与第二源极/漏极区110B。通过穿过第一盖结构136A的前侧内连线结构114,第一源极/漏极接点结构132A可连接至前侧电源轨105。可经由第二盖结构136B中的开口842移除第二源极/漏极接点结构132B。在移除第二源极/漏极接点结构之后,可形成气隙于第二盖结构与第二源极/漏极区之间。在一些实施例中,可经由开口842移除第二源极/漏极接点结构132B的金属接点130B。在一些实施例中,可经由开口842移除第二源极/漏极接点结构132B的金属接点130B与硅化物层128B。在一些实施例中,可形成密封介电结构142于开口842中,以密封第二盖结构136B与第二源极/漏极区110B之间的气隙126。在一些实施例中,在形成密封介电结构142时可形成密封介电层242于气隙226-2中。在一些实施例中,气隙126可减少背侧电源轨半导体装置100的栅极结构112与第二源极/漏极区110B之间的寄生电容。在一些实施例中,由于气隙126减少电容,背侧电源轨半导体装置100的装置效能可改善约3%至约5.5%。
在一些实施例中,半导体装置的形成方法包括:形成鳍状结构于基板的第一侧上;形成源极/漏极区以与鳍状结构相邻;形成第一源极/漏极接点结构于基板的第一侧上并接触源极/漏极区;以及形成盖结构于第一源极/漏极接点结构上。方法还包括经由盖结构移除第一源极/漏极接点结构的一部分,以形成气隙;以及形成第二源极/漏极接点结构于基板的第二侧上并接触源极/漏极区。第二侧与第一侧相对。
在一些实施例中,第一源极/漏极接点结构包括金属接点,且移除该第一源极/漏极接点结构的部分的步骤包括:形成开口于盖结构中;经由开口移除金属接点以形成气隙;以及形成密封结构于开口中以密封气隙。
在一些实施例中,形成密封结构的步骤包括沉积介电材料于开口与气隙中。
在一些实施例中,第一源极/漏极接点结构包括金属接点与硅化物层,且移除源极/漏极接点结构的部分的步骤包括:形成开口于盖结构中;经由开口移除金属接点与硅化物层以形成气隙;以及形成密封结构于开口中以密封气隙。
在一些实施例中,形成源极/漏极区的步骤包括:形成源极/漏极区的第一部分于基板中;以及形成源极/漏极的第二部分以接触鳍状结构,其中第一源极/漏极接点结构接触第二部分。
在一些实施例中,形成第二源极/漏极接点结构的步骤包括:将基板置换成介电层;移除基板的第二侧上的源极/漏极区的一部分;以及形成硅化物层以接触基板的第二侧上的源极/漏极区。
在一些实施例中,方法还包括形成内连线结构以接触第二源极/漏极接点结构。
在一些实施例中,半导体装置的形成方法包括:形成鳍状结构于基板的第一侧上;形成第一源极/漏极区与第二源极/漏极区以与鳍状结构的两端相邻;在基板的第一侧上形成第一源极/漏极接点结构以接触第一源极/漏极区,并形成第二源极/漏极接点结构以接触第二源极/漏极区;形成第一盖结构于第一源极/漏极接点结构上,并形成第二盖结构于第二源极/漏极接点结构上。方法还包括经由第二盖结构移除第二源极/漏极接点结构的一部分,以形成气隙;以及形成第三接点结构于基板的第二侧上并接触第二源极/漏极区。第二侧与第一侧相对。
在一些实施例中,第二源极/漏极接点结构包括金属接点,且移除第二源极/漏极接点结构的部分的步骤包括:形成开口于第二盖结构中;经由开口移除金属接点以形成气隙;以及形成密封结构于开口中以密封气隙。
在一些实施例中,形成密封结构的步骤包括沉积介电材料于开口与气隙中。
在一些实施例中,第二源极/漏极接点结构包括金属接点与硅化物层,且移除第二源极/漏极接点结构的部分的步骤包括:形成开口于第二盖结构中;经由开口移除金属接点与硅化物层以形成气隙;以及形成密封结构于开口中以密封气隙。
在一些实施例中,形成第二源极/漏极区的步骤包括:形成第二源极/漏极区的第一部分于基板中;以及形成第二源极/漏极区的第二部分以接触鳍状结构,其中第二源极/漏极接点结构接触第二部分。
在一些实施例中,形成第三接点结构的步骤包括:将基板置换成介电层;移除基板的第二侧上的第二源极/漏极区的一部分;以及形成硅化物层以接触基板的第二侧上的第二源极/漏极区。
在一些实施例中,方法还包括:形成第一内连线结构于第一侧上以接触第一源极/漏极接点结构;以及形成第二内连线结构于第二侧上以接触第三接点结构。
在一些实施例中,半导体装置包括:鳍状结构,位于基板的第一侧上;第一源极/漏极区与第二源极/漏极区,与鳍状结构的两端相邻;第一源极/漏极接点结构,接触第一源极/漏极区;第一盖结构,位于第一源极/漏极接点结构上;第二盖结构,位于第二源极/漏极区上;气隙,位于第二盖结构与第二源极/漏极区之间;以及第二源极/漏极接点结构,接触基板的第二侧上的第二源极/漏极区。第二侧与第一侧相对。
在一些实施例中,半导体装置还包括硅化物层位于气隙中的第二源极/漏极区上。
在一些实施例中,半导体装置还包括密封结构位于第二盖结构中以密封气隙,其中密封结构包括介电材料。
在一些实施例中,半导体装置还包括介电材料层于气隙中。
在一些实施例中,半导体装置还包括:第一内连线结构位于基板的第一侧上并接触第一源极/漏极接点结构;以及第二内连线结构位于基板的第二侧上并接触第二源极/漏极接点结构。
在一些实施例中,第一源极/漏极接点结构包括金属接点与第一硅化物层,而第二源极/漏极接点结构包括第二硅化物层。
应理解的是,实施方式(非摘要)用于说明请求项。摘要可提及一或多个但非所有可能的本发明实施例,因此并非用以局限所附的请求项。
上述实施例的特征有利于本技术领域中具有通常知识者理解本发明。本技术领域中具有通常知识者应理解可采用本发明作基础,设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中具有通常知识者亦应理解,这些等效置换并未脱离本发明精神与范畴,并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。
Claims (1)
1.一种半导体装置的形成方法,包括:
形成一鳍状结构于一基板的一第一侧上;
形成一源极/漏极区以与该鳍状结构相邻;
形成一第一源极/漏极接点结构于该基板的该第一侧上并接触该源极/漏极区;
形成一盖结构于该第一源极/漏极接点结构上;
经由该盖结构移除该第一源极/漏极接点结构的一部分,以形成一气隙;以及
形成一第二源极/漏极接点结构于该基板的一第二侧上并接触该源极/漏极区,其中该第二侧与该第一侧相对。
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US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
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