CN114039557A - Precise large-bandwidth digital phase-locked amplifier with hybrid sampling structure - Google Patents
Precise large-bandwidth digital phase-locked amplifier with hybrid sampling structure Download PDFInfo
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- CN114039557A CN114039557A CN202111316282.2A CN202111316282A CN114039557A CN 114039557 A CN114039557 A CN 114039557A CN 202111316282 A CN202111316282 A CN 202111316282A CN 114039557 A CN114039557 A CN 114039557A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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Abstract
The invention provides a precise large-bandwidth digital phase-locked amplifier with a mixed sampling structure, which comprises a signal link to be tested, a reference signal link, digital logic and a computing system, wherein the signal link to be tested is connected with the reference signal link; the signal link to be tested inputs an input signal to be tested and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to a digital logic and computing system; the reference signal link inputs a reference input signal and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and calculation system; the digital logic and computing system outputs a plurality of control signals to a signal link to be tested and a reference signal link; the digital phase-locked amplifier with the mixed sampling structure has a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode, and can improve the signal-to-noise ratio of a signal link to be measured in the measurement of low-frequency signals and high-frequency signals.
Description
Technical Field
The invention relates to the field of weak signal detection instruments, in particular to a precise large-bandwidth digital phase-locked amplifier with a mixed sampling structure.
Background
There are a number of weak signals in nature and human social life, and how to detect these weak signals is becoming an important issue in the fields of biomedicine, basic discipline, electronic information, material engineering, and the like.
A lock-in amplifier is an instrument for detecting weak signals, and can extract signals of specific frequencies from a strong noise background. The phase-locked amplifier can be divided into an analog phase-locked amplifier and a digital phase-locked amplifier according to a system architecture, a phase sensitive detector serving as a core of the analog phase-locked amplifier is realized by an analog multiplier, but the dynamic reserve range is difficult to further improve due to the nonlinearity of an analog device and the easiness of external interference, so that the digital phase-locked amplifier replaces analog operation by digital operation and overcomes the defect.
As shown in fig. 1, a conventional digital lock-in amplifier generally includes a reference signal link, a signal link under test, and a digital logic and computing system. The signal link to be measured generally includes amplification, filtering and single analog-to-digital conversion, the reference signal link generally includes filtering and single analog-to-digital conversion, the digital signals output by the above-mentioned two circuits are multiplied and low-pass filtered by phase-sensitive detection module in digital logic and computing system, then the mathematical operation is made so as to can calculate the amplitude value of the signal to be measured and the phase difference with reference signal.
The conventional digital lock-in amplifier has the disadvantage that for a higher frequency signal to be measured, the sampling rate of an analog-to-digital converter in a signal link to be measured needs to be higher. A few MSPS sampling rate adcs can achieve 24 bits, but ultra high speed adcs above about 250MSPS typically have less than 14 bits, which means that a choice must be made between high speed and high accuracy, but the measurement accuracy of the instrument is a prerequisite for detecting weak signals. For low-frequency signals, due to the use of a super-high-speed analog-to-digital converter with a lower bit number, the noise performance is far inferior to that of a low-frequency digital lock-in amplifier; for high frequency signals, the digital lock-in amplifier with the traditional structure inevitably introduces lower signal-to-noise ratio, and the seeking of a high-bit ultra-high-speed analog-to-digital converter is not only technically difficult but also extremely high in cost.
Disclosure of Invention
The invention provides a precise large-bandwidth digital phase-locked amplifier with a mixed sampling structure, which can improve the signal-to-noise ratio of a signal link to be measured in the measurement of low-frequency signals and high-frequency signals.
In order to achieve the technical effects, the technical scheme of the invention is as follows:
a precise large-bandwidth digital phase-locked amplifier with a mixed sampling structure comprises a signal link to be tested, a reference signal link, digital logic and a computing system; the signal link to be tested inputs an input signal to be tested and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to a digital logic and computing system; the reference signal link inputs a reference input signal and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and calculation system; the digital logic and computing system outputs a plurality of control signals to the signal link to be tested and the reference signal link.
Furthermore, the signal link to be tested comprises a low-noise pre-stage amplifying circuit, a first low-pass filter, a first analog-to-digital converter, a frequency mixer, a numerically controlled oscillator, a gating circuit, a second low-pass filter and a second analog-to-digital converter;
the input signal to be detected is amplified through a low-noise pre-stage amplifying circuit and filtered through a first low-pass filter to obtain a first low-pass filtering signal;
the numerically controlled oscillator is controlled to generate a sinusoidal signal with adjustable frequency and input the sinusoidal signal into the mixer, so that the down-conversion component output by the mixer is fixed in a low-frequency range, and if the frequency of the reference input signal is omega, the frequency of the numerically controlled oscillator is set to be omega-omega0The frequency component of the mixer output has 2 omega-omega0And ω0Second low-pass filter for filtering out 2 omega-omega0Component, leaving only ω0The component is transmitted to a second analog-to-digital converter;
the first low-pass filtering signal is divided into three paths which are respectively connected with a gating circuit, a frequency mixer and a first analog-to-digital converter, so that three sampling modes of a signal link to be detected are determined, namely a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode;
the first low-pass filtering signal is subjected to a mixer to obtain a down-conversion mixer signal which is connected with a gating circuit, and the first low-pass filtering signal is subjected to a first analog-to-digital converter to obtain a first analog-to-digital conversion signal;
the gating circuit selects a first low-pass filter signal or a mixer signal to obtain a gating circuit signal which is connected with a second low-pass filter;
and the gating circuit signal sequentially passes through a second low-pass filter and a second analog-to-digital converter to obtain a second analog-to-digital conversion signal.
Further, the reference signal link comprises a low noise amplifier, a third low pass filter, a third analog-to-digital converter and a hysteresis comparator; amplifying the reference input signal through a low-noise amplifier, and filtering the amplified reference input signal through a third low-pass filter to obtain a third low-pass filtered signal; the third low-pass filtering signal is divided into two paths and respectively passes through a third analog-to-digital converter and a hysteresis comparator to obtain a third analog-to-digital conversion signal and a hysteresis comparison signal.
Furthermore, the digital logic and computing system comprises a data gate, a digital phase-locked loop, a frequency measurement module, a digital sine generator, a phase-sensitive detection module and a microprocessor, and is realized on an Soc chip containing an FPGA and the microprocessor;
the data gate selects the first analog-to-digital converter or the second analog-to-digital converter to be connected to the phase-sensitive detection module;
the third analog-to-digital conversion signal passes through a digital phase-locked loop and then is connected with a digital sine generator control phase;
one path of the hysteresis comparison signal is connected to the control frequency of the digital sine generator after passing through the frequency measurement module, and the other path of the hysteresis comparison signal is connected with the microprocessor to transmit signal frequency information;
the phase-sensitive detection module multiplies and filters signals from the data strobe and the digital sine generator and then is connected to the microprocessor;
and the microprocessor calculates the amplitude of the input signal to be detected and the phase difference between the input signal to be detected and the reference input signal according to the signal output by the phase-sensitive detection module.
Further, in a low-frequency sampling mode, after the gating circuit selects and connects the first low-pass filtering signal, the second low-pass filtering signal and the second analog-to-digital converter are sequentially passed through to obtain a second analog-to-digital conversion signal, the second analog-to-digital conversion signal is connected to the digital logic and computing system, and the second analog-to-digital conversion signal is connected to the phase-sensitive detection module through the data gating device;
under the down-conversion sampling mode, after the gating circuit selects and connects the signals of the frequency mixer, the signals sequentially pass through a second low-pass filter and a second analog-to-digital converter to obtain second analog-to-digital conversion signals, and the second analog-to-digital conversion signals are connected to a digital logic and computing system and are connected to a phase-sensitive detection module through a data gating device;
and under a high-frequency sampling mode, the first low-pass filtering signal passes through the first analog-to-digital converter to obtain a first analog-to-digital conversion signal, is connected to the digital logic and computing system, and is connected to the phase-sensitive detection module through the data gate.
Furthermore, the microprocessor controls the low-noise pre-stage amplifying circuit, the numerical control oscillator and the gating circuit through a level conversion circuit interface, and controls the data gating device and the phase-sensitive detection module through a digital bus interface.
Preferably, the gating circuit is a high-speed analog switch; the digital logic and computing system is a Soc chip, a combination of CPLD and DSP chips or an ASIC chip containing an FPGA and a microprocessor.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the invention adds a frequency mixer, a numerical control oscillator, another group of low-pass filters and a low-speed high-precision analog-to-digital converter on a signal link to be measured, and selects a signal to the low-speed high-precision analog-to-digital converter through a gating circuit. According to the selection between the gating circuit and the two analog-to-digital converters, the signal link to be detected can have three sampling modes, namely a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode; the low-frequency sampling mode can realize the optimal signal-to-noise ratio in the measurement of the low-frequency signal, and the low-frequency signal is finally fed to the low-speed high-precision analog-to-digital converter through the gating circuit; the signal-to-noise ratio can be improved in the measurement of high-frequency signals in the down-conversion sampling mode, because the bit number of the ultrahigh-frequency analog-to-digital converter is low, but the high-frequency signals cannot be directly sent to the low-speed high-precision analog-to-digital converter, the down-conversion is carried out through a mixer to obtain a low-frequency signal, and then the low-frequency signal is sent to the low-speed high-precision analog-to-digital converter; the high-frequency sampling mode keeps the most basic data path of the digital phase-locked amplifier with the traditional structure, and the branch can not be replaced by other branches when the harmonic measurement of the phase-locked amplifier is carried out; the digital phase-locked amplifier with the mixed sampling structure has a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode, and can improve the signal-to-noise ratio of a signal link to be measured in the measurement of low-frequency signals and high-frequency signals.
Drawings
Fig. 1 is a structural diagram of a conventional digital lock-in amplifier in the prior art;
fig. 2 is a system block diagram of a digital lock-in amplifier according to embodiment 1;
fig. 3 is a system block diagram of a low frequency sampling mode of the digital lock-in amplifier according to embodiment 1;
fig. 4 is a system block diagram of a down-conversion sampling mode of the digital lock-in amplifier according to embodiment 1;
fig. 5 is a system block diagram of a high frequency sampling mode of the digital lock-in amplifier according to embodiment 1;
FIG. 6 is a control block diagram of the microprocessor described in embodiment 1;
FIG. 7 is a graph comparing the signal-to-noise ratio curves of the digital lock-in amplifier of the present invention and the conventional structure as described in example 1;
in the figure, 1 — signal link under test; 2-reference signal link; 3-digital logic and computing system 3; 11-low noise pre-amplifier circuit; 12-a first low-pass filter; 13-a first analog-to-digital converter; 14-a mixer; 15-a numerically controlled oscillator; 16-a gating circuit; 17-a second low pass filter; 18-a second analog-to-digital converter; 21-a low noise amplifier; 22-a third low-pass filter; 23-a third analog-to-digital converter; 24-a hysteresis comparator; 31-a data strobe; 32-a digital phase locked loop; 33-a frequency measurement module; 34-a digital sine generator; 35-a phase sensitive detection module; 36-a microprocessor; 41-level shift circuit interface; 42-digital bus interface.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
As shown in fig. 2, the present invention provides a precise large-bandwidth digital lock-in amplifier with a hybrid sampling structure, which includes a signal link 1 to be tested, a reference signal link 2, and a digital logic and computation system 3, where the signal link 1 to be tested inputs an input signal to be tested and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital logic and computation system 3; the reference signal link 2 inputs a reference input signal and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and calculation system 3; the digital logic and computing system 3 outputs a plurality of control signals to the signal link 1 to be tested and the reference signal link 2.
The signal link 1 to be tested comprises a low-noise pre-amplification circuit 11, a first low-pass filter 12, a first analog-to-digital converter 13, a frequency mixer 14, a numerically controlled oscillator 15, a gating circuit 16, a second low-pass filter 17 and a second analog-to-digital converter 18;
an input signal to be measured is amplified through a low-noise pre-stage amplifying circuit 11 and filtered through a first low-pass filter 12 to obtain a first low-pass filtering signal;
the numerically controlled oscillator is controlled to generate a sinusoidal signal with adjustable frequency, and the sinusoidal signal is input into the mixer, so that the down-conversion component of the mixer output is fixed at oneIn the low frequency range, if the frequency of the reference input signal is omega, the frequency of the numerical control oscillator is set to be omega-omega0The frequency component of the mixer output has 2 omega-omega0And ω0Second low-pass filter for filtering out 2 omega-omega0Component, leaving only ω0The component is transmitted to a second analog-to-digital converter;
the first low-pass filtering signal is divided into three paths, and the three paths are respectively connected with the gating circuit 16, the frequency mixer 14 and the first analog-to-digital converter 13, so that three sampling modes of a signal link to be detected are determined, namely a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode;
the first low-pass filtered signal passes through a mixer 14 to obtain a down-converted mixer signal, and is connected with a gating circuit 16, and the first low-pass filtered signal passes through a first analog-to-digital converter 13 to obtain a first analog-to-digital converted signal;
the gating circuit 16 selects the first low-pass filter signal or the mixer signal to obtain a gating circuit signal which is connected with the second low-pass filter 17;
the gating circuit signal sequentially passes through the second low pass filter 17 and the second analog-to-digital converter 18 to obtain a second analog-to-digital conversion signal.
The reference signal link 2 comprises a low noise amplifier 21, a third low pass filter 22, a third analog-to-digital converter 23 and a hysteresis comparator 24;
the reference input signal is amplified by a low noise amplifier 21 and filtered by a third low pass filter 22 to obtain a third low pass filtered signal;
the third low-pass filtered signal is divided into two paths, which pass through a third analog-to-digital converter 23 and a hysteresis comparator 24, respectively, to obtain a third analog-to-digital converted signal and a hysteresis comparison signal.
The digital logic and computing system 3 comprises a data gate 31, a digital phase-locked loop 32, a frequency measurement module 33, a digital sine generator 34, a phase sensitive detection module 35 and a microprocessor 36, and is realized on an Soc chip containing an FPGA and the microprocessor;
the data gate 31 selects the first analog-to-digital converter 13 or the second analog-to-digital converter 18 to be connected to the phase-sensitive detection module 35;
the third analog-to-digital conversion signal passes through the digital phase-locked loop 32 and then is connected with a digital sine generator 34 to control the phase;
after passing through the frequency measurement module 33, one path of the hysteresis comparison signal is connected to the digital sine generator 34 for controlling the frequency, and the other path of the hysteresis comparison signal is connected to the microprocessor 36 for transmitting the signal frequency information.
The phase-sensitive detection module 35 multiplies and filters the signals from the data strobe 31 and the digital sine generator 34, and then is connected to the microprocessor 36;
the microprocessor 36 calculates the amplitude of the input signal to be detected and the phase difference between the input signal and the reference input signal according to the signal output by the phase-sensitive detection module 35.
As shown in fig. 3, in the low-frequency sampling mode, the gating circuit 16 selectively connects the first low-pass filtered signal, and then sequentially passes through the second low-pass filter 17 and the second analog-to-digital converter 18 to obtain a second analog-to-digital converted signal, and is connected to the digital logic and computing system 3, and is connected to the phase-sensitive detection module 35 through the data gate 31.
As shown in fig. 4, in the down-conversion sampling mode, the gating circuit 16 selects and connects the mixer signal, and then sequentially passes through the second low-pass filter 17 and the second analog-to-digital converter 18 to obtain a second analog-to-digital conversion signal, and is connected to the digital logic and computing system 3, and is connected to the phase-sensitive detection module 35 through the data gate 31.
As shown in fig. 5, in the high frequency sampling mode, the first low pass filtered signal passes through the first analog-to-digital converter 13 to obtain a first analog-to-digital converted signal, and is connected to the digital logic and computation system 3, and is connected to the phase sensitive detection module 35 through the data strobe 31.
As shown in fig. 6, the microprocessor 36 controls the low noise pre-amplifier circuit 11, the digitally controlled oscillator 15 and the gating circuit 16 through the level shift circuit interface 41, and controls the data strobe 31 and the phase sensitive detection module 35 through the digital bus interface 42.
As shown in fig. 7, comparing the signal-to-noise ratio curves of the precise large-bandwidth digital lock-in amplifier with the hybrid sampling structure of the present invention and the digital lock-in amplifier with the conventional structure, since only a single ultra-high frequency analog-to-digital converter is used in the conventional structure,
the signal-to-noise ratio is lower under low-frequency signals, and the signal-to-noise ratio is gradually reduced along with the increase of the frequency of the signal to be detected. In the mixed structure of the invention, for low-frequency signals, the digital phase-locked amplifier works in a low-frequency sampling mode, and the second analog-to-digital converter 18 with low speed and high precision is used for sampling, so that the signal-to-noise ratio is higher; for high-frequency signals, the digital phase-locked amplifier works in a down-conversion frequency sampling mode or a high-frequency sampling mode, the signal-to-noise ratio of the high-frequency sampling mode is the same as that of a traditional structure, the requirement of harmonic measurement is met, and the signal-to-noise ratio can be improved compared with that of the traditional structure in the down-conversion sampling mode.
Compared with the digital phase-locked amplifier with the traditional structure, the digital phase-locked amplifier has the innovative technical key point of the structural design of the signal link to be tested. In the prior structure, an input signal to be measured sequentially passes through an amplifying circuit and a filtering circuit and then is connected to an analog-to-digital converter, but for a high-frequency signal, the number of bits of the ultrahigh-speed analog-to-digital converter is low, so that the signal-to-noise ratio of a signal link to be measured is low.
The invention adds a frequency mixer, a numerical control oscillator, another group of low-pass filters and a low-speed high-precision analog-to-digital converter on a signal link to be measured, and selects a signal to the low-speed high-precision analog-to-digital converter through a gating circuit. According to the selection between the gating circuit and the two analog-to-digital converters, the signal link to be detected can have three sampling modes, namely a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode.
The low-frequency sampling mode can realize the optimal signal-to-noise ratio in the measurement of the low-frequency signal, and the low-frequency signal is finally supplied to the low-speed high-precision analog-to-digital converter through the gating circuit.
The down-conversion sampling mode can improve the signal-to-noise ratio in the measurement of high-frequency signals, because the bit number of the ultrahigh-frequency analog-to-digital converter is low, but the high-frequency signals cannot be directly sent to the low-speed high-precision analog-to-digital converter, the down-conversion is carried out through a mixer to obtain a low-frequency signal, and then the low-frequency signal is sent to the low-speed high-precision analog-to-digital converter.
The high frequency sampling mode maintains the most basic data path of the digital lock-in amplifier of the conventional structure, and this branch can not be replaced by other branches when the harmonic measurement of the lock-in amplifier is carried out.
In summary, the digital lock-in amplifier with the traditional structure only has a high-frequency sampling mode, while the digital lock-in amplifier with the mixed sampling structure of the invention has a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode, and can improve the signal-to-noise ratio of a signal link to be measured in the measurement of low-frequency signals and high-frequency signals.
The same or similar reference numerals correspond to the same or similar parts;
the positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A precise large-bandwidth digital phase-locked amplifier with a mixed sampling structure is characterized by comprising a signal link (1) to be tested, a reference signal link (2) and a digital logic and computing system (3); the signal link (1) to be tested inputs an input signal to be tested and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital logic and calculation system (3); the reference signal link (2) inputs a reference input signal and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and calculation system (3); the digital logic and computing system (3) outputs a plurality of control signals to the signal link (1) to be tested and the reference signal link (2).
2. The fine large-bandwidth digital phase-locked amplifier with a hybrid sampling structure according to claim 1, wherein the signal link (1) under test comprises a low-noise pre-amplifier circuit (11), a first low-pass filter (12), a first analog-to-digital converter (13), a mixer (14), a numerically controlled oscillator (15), a gating circuit (16), a second low-pass filter (17) and a second analog-to-digital converter (18);
the input signal to be measured is amplified through a low-noise pre-stage amplifying circuit (11) and filtered through a first low-pass filter (12) to obtain a first low-pass filtering signal;
the numerically controlled oscillator (15) is controlled to generate a frequency-adjustable sinusoidal signal for input to the mixer (14) such that the down-converted component of the mixer (14) output is fixed within a low-frequency range, and the numerically controlled oscillator is set to have a frequency of ω - ω if the frequency of the reference input signal is ω0The frequency component of the mixer output has 2 omega-omega0And ω0The second low-pass filter (17) filters out 2 omega-omega0Component, leaving only ω0The components are passed to a second analogue to digital converter (18);
the first low-pass filtering signal is divided into three paths which are respectively connected with a gating circuit (16), a mixer (14) and a first analog-to-digital converter (13), so that three sampling modes of a signal link to be detected are determined, wherein the three sampling modes are a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode;
the first low-pass filtering signal is processed by a mixer (14) to obtain a down-converted mixer signal which is connected with a gating circuit (16), and the first low-pass filtering signal is processed by a first analog-to-digital converter (13) to obtain a first analog-to-digital conversion signal;
the gating circuit (16) selects the first low-pass filter signal or the mixer signal to obtain a gating circuit signal which is connected with the second low-pass filter (17);
and the gating circuit signal sequentially passes through a second low-pass filter (17) and a second analog-to-digital converter (18) to obtain a second analog-to-digital conversion signal.
3. The fine large bandwidth digital lock-in amplifier of hybrid sampling structure according to claim 2, characterized in that the reference signal chain (2) comprises a low noise amplifier (21), a third low pass filter (22), a third analog-to-digital converter (23), a hysteresis comparator (24); the reference input signal is amplified through a low-noise amplifier (21) and filtered through a third low-pass filter (22) to obtain a third low-pass filtered signal; the third low-pass filtering signal is divided into two paths and respectively passes through a third analog-to-digital converter (23) and a hysteresis comparator (24) to obtain a third analog-to-digital conversion signal and a hysteresis comparison signal.
4. The precision large-bandwidth digital phase-locked amplifier with a hybrid sampling structure according to claim 3, wherein the digital logic and computation system (3) comprises a data gate (31), a digital phase-locked loop (32), a frequency measurement module (33), a digital sine generator (34), a phase-sensitive detection module (35) and a microprocessor (36), and is implemented on a Soc chip comprising an FPGA and the microprocessor;
the data gate (31) selects the first analog-to-digital converter (13) or the second analog-to-digital converter (18) to be connected to the phase-sensitive detection module (35);
the third analog-to-digital conversion signal passes through a digital phase-locked loop (32) and then is connected with a digital sine generator (34) to control the phase;
one path of the hysteresis comparison signal is connected to the control frequency of the digital sine generator (34) after passing through the frequency measurement module (33), and the other path of the hysteresis comparison signal is connected with the microprocessor (36) to transmit signal frequency information;
the phase-sensitive detection module (35) multiplies and filters signals from the data strobe (31) and the digital sine generator (34), and then is connected to the microprocessor (36);
and the microprocessor (36) calculates the amplitude of the input signal to be detected and the phase difference between the amplitude and the reference input signal according to the signal output by the phase-sensitive detection module (35).
5. The precise large-bandwidth digital phase-locked amplifier with the hybrid sampling structure according to claim 4, wherein in the low-frequency sampling mode, the gating circuit (16) is selectively connected with the first low-pass filtered signal, and then sequentially passes through the second low-pass filter (17) and the second analog-to-digital converter (18) to obtain a second analog-to-digital converted signal, and is connected to the digital logic and computation system (3) and connected to the phase-sensitive detection module (35) through the data gate (31).
6. The fine large bandwidth digital lock-in amplifier with hybrid sampling architecture as claimed in claim 5, wherein in the down-conversion sampling mode, the gating circuit (16) selects the connection of the mixer signal, then the signal passes through the second low pass filter (17) and the second analog-to-digital converter (18) in turn to obtain the second analog-to-digital converted signal, and is connected to the digital logic and computation system (3) and the phase sensitive detection module (35) through the data gate (31).
7. The fine large bandwidth digital lock-in amplifier of hybrid sampling structure as claimed in claim 6, wherein in the high frequency sampling mode, the first low pass filtered signal is passed through the first analog-to-digital converter (13) to obtain the first analog-to-digital converted signal, and is connected to the digital logic and computation system (3) and the phase sensitive detection module (35) through the data strobe (31).
8. The fine large bandwidth digital lock-in amplifier of hybrid sampling architecture according to claim 7, characterized by the microprocessor (36) controlling the low noise pre-amplifier circuit (11), the digitally controlled oscillator (15) and the gating circuit (16) through the level shifter circuit interface (41) and the data gate (31) and the phase sensitive detection module (35) through the digital bus interface (42).
9. The sophisticated large bandwidth digital lock-in amplifier of hybrid sampling architecture as claimed in claim 8, characterized in that the gating circuit (16) is a high speed analog switch.
10. The sophisticated large bandwidth digital lock-in amplifier of hybrid sampling structure according to claim 9, characterized in that the digital logic and computation system (3) is a Soc chip, a combination of CPLD and DSP chips containing FPGA and microprocessor or an ASIC chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115001419A (en) * | 2022-05-26 | 2022-09-02 | 中山大学 | Photoelectric isolated high-frequency digital phase-locked amplifier |
| CN117254805A (en) * | 2023-11-20 | 2023-12-19 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
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2021
- 2021-11-08 CN CN202111316282.2A patent/CN114039557A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115001419A (en) * | 2022-05-26 | 2022-09-02 | 中山大学 | Photoelectric isolated high-frequency digital phase-locked amplifier |
| CN115001419B (en) * | 2022-05-26 | 2024-04-02 | 中山大学 | Photoelectric isolation high-frequency digital phase-locked amplifier |
| CN117254805A (en) * | 2023-11-20 | 2023-12-19 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
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