CN114005761A - Packaging method of photovoltaic bypass module - Google Patents
Packaging method of photovoltaic bypass module Download PDFInfo
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- CN114005761A CN114005761A CN202111275699.9A CN202111275699A CN114005761A CN 114005761 A CN114005761 A CN 114005761A CN 202111275699 A CN202111275699 A CN 202111275699A CN 114005761 A CN114005761 A CN 114005761A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H01L2224/84205—Ultrasonic bonding
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- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a packaging method of a photovoltaic bypass module, which comprises the following steps: providing a lead frame, an MOS chip, an IC chip and a capacitor; the upper core fixes the MOS chip, the IC chip and the capacitor on the base island of the anode pin; bonding, namely bonding the MOS chip, the IC chip and the capacitor by adopting a copper wire or a gold wire, and bonding the MOS chip and the cathode pin by adopting an aluminum tape; cleaning; plastic packaging; tin coating; cutting ribs, testing characters and packaging for shipment. The invention can effectively improve the production efficiency and reduce the production cost through the multi-row frame unit; in the packaging process, copper wires or gold wires are used for bonding among chips and between the chips and capacitors, so that the on-resistance can be reduced by 20-30%, and the reliability of welding spots is improved; the MOS chip and the cathode pin are bonded by adopting an aluminum tape, so that the on-resistance can be reduced by 10-20%, the on-loss is reduced, and the current impact resistance is improved; and bonding is carried out by using a wider aluminum tape, so that the thermal resistance can be effectively reduced by 20-30%, and the heat conduction capability is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a packaging method of a photovoltaic bypass module.
Background
Photovoltaic power generation converts inexhaustible light energy into electric energy, pure and pollution-free light energy is more in line with the development of the era, but the difficult problems that how to convert more light energy into electric energy and how to avoid the converted electric energy from being lost are avoided. The conversion efficiency mainly depends on the efficiency of the solar panel material for converting light energy into electric energy, the electric energy loss is influenced by the hot spot effect, and the whole solar battery pack can be damaged even by the serious hot spot effect. Although the hot spot effect is unavoidable, the influence of the hot spot effect can be minimized by adding a photovoltaic bypass circuit.
The photovoltaic bypass circuit can block reverse current in time when the solar battery pack generates a hot spot effect, and avoids the shielded solar battery pack from generating heat, causing loss of electric energy and damage to the battery. The photovoltaic bypass circuit of the first generation PN junction diode and the second generation Schottky diode is large in power consumption and easy to fail, and the MOS photovoltaic bypass switch circuit of the third generation utilizes the characteristics of low on-resistance and low electric leakage of a power MOSFET to solve the problems of large forward voltage drop, low high-temperature voltage resistance and large electric leakage of the photovoltaic bypass diode. However, in the prior art, the MOS photovoltaic bypass module has low heat dissipation efficiency and high power consumption during packaging, and is often prone to failure, which affects the performance of a power device.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for packaging a photovoltaic bypass module, which is used to solve the problems of low heat dissipation efficiency, high power consumption, easy failure and influence on the performance of a power device in the prior art when a photovoltaic bypass module device is packaged.
In order to achieve the above and other related objects, the present invention provides a method for packaging a photovoltaic bypass module, where a lead frame 100 of the photovoltaic bypass module includes a frame body 1 and a plurality of frame units 2 arranged in an array, each frame unit 2 includes a base island 23, an anode pin 22 and a cathode pin 21, the base island 23 is disposed on the anode pin 22, the anode pin 22 and the cathode pin 21 are both provided with a T-shaped pin portion 24, and the pin portion 24 is provided with a groove 241, the method includes the following steps:
providing a lead frame, an MOS chip, an IC chip and a capacitor;
the MOS chip, the IC chip and the capacitor are fixed on the base island of the anode pin;
bonding, namely bonding the MOS chip, the IC chip and the capacitor by adopting a copper wire (or a gold wire), and bonding the MOS chip and the cathode pin by adopting an aluminum tape;
cleaning, namely cleaning the lead frame welded with the MOS chip, the IC chip and the capacitor;
plastic packaging, namely packaging the cleaned lead frame by using a plastic packaging material to form a plastic packaging body, and externally leaking the anode pin and the cathode pin;
tinning, namely electroplating tinning the lead frame subjected to plastic packaging;
cutting ribs, testing, printing characters, packaging and delivering.
Optionally, the base island on the anode pin is divided into a silver plating region and a roughening region, the silver plating region is subjected to silver plating, the roughening region is subjected to bare copper roughening, and the back side of the anode pin corresponding to the base island is provided with pits.
Optionally, the frame units are arranged in three rows.
Optionally, the step of fixing the MOS chip, the IC chip, and the capacitor on the base island of the anode pin includes:
welding the MOS chip on the base island of the anode pin by adopting a soft solder process;
and welding the IC chip and the capacitor on the base island of the anode pin by adopting a dispensing process, and baking and curing by using nitrogen.
Optionally, the thickness of the solder layer of the soft solder is 25-55 um; the dispensing thickness is 20-30 um, the baking temperature is 150-170 ℃, and the baking time is 60-90 min.
Optionally, the bonding step comprises:
welding copper wires (or gold wires) between an MOS chip and an IC chip, between the MOS chip and a capacitor and between the IC chip and the capacitor by adopting an ultrasonic welding process, wherein the surface of the capacitor contains a gold-plated layer;
and bonding one end of the aluminum strip with the source electrode of the MOS chip and bonding the other end of the aluminum strip with the cathode pin by adopting an ultrasonic welding process.
Optionally, in the cleaning step, a plasma cleaning machine is used to clean the bonded lead frame.
Optionally, in the plastic packaging step, curing treatment after plastic packaging is further included, wherein the curing temperature is 175 ℃, and the curing time is 8 hours.
Optionally, after the plastic packaging step and before the tin coating step, a screening step is further included, and the screening step adopts a reflow soldering process to perform quality screening.
Optionally, the screening step further includes performing a cold-hot impact test through a cold-hot impact test.
As described above, the present invention has the following advantageous effects:
(1) the multi-row frame units can effectively improve the production efficiency and the utilization rate of raw materials and reduce the production cost;
(2) in the packaging process, copper wires (or gold wires) are used for bonding among the MOS chips and between the MOS chips and the capacitor, so that the on-resistance can be reduced by 20-30%, and the reliability of welding spots is improved;
(3) the MOS chip and the cathode pin are bonded by adopting an aluminum tape, so that the on-resistance can be reduced by 10-20%, the on-loss is reduced, and the current impact resistance is improved; and bonding is carried out by using a wider aluminum tape, so that the thermal resistance can be effectively reduced by 20-30%, and the heat conduction capability is improved.
Drawings
FIG. 1 is a schematic diagram of a lead frame structure according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a frame unit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a backside structure of a frame unit according to an embodiment of the present invention;
FIG. 4 is a schematic structural view of an embodiment of the present invention after core installation;
FIG. 5 is a schematic structural diagram of the embodiment of the present invention after bonding;
fig. 6 is a schematic structural diagram after plastic packaging according to an embodiment of the present invention.
Description of reference numerals
1-a frame body 1;
2-a frame unit; 21-cathode lead; 22-anode pin; 23-base island; 231-a silver plating zone; 232-a roughened region; 24-a pin section; 241-a groove; 25-a tin-on region; 26-glue locking holes; 27-pitting;
100-a lead frame; 200-MOS chip; 300-IC chip; 301-a first IC chip; 302-a second IC chip; 400-capacitance; 500-copper (or gold) wire; 600-aluminum strip; 700-plastic package body; 801-first weld site; 802-second weld location; 803-third weld site.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
Referring to fig. 1 to 6, in this embodiment, a method for packaging a photovoltaic bypass module is provided, where a lead frame 100 adopted by the photovoltaic bypass module includes a frame body 1 and a plurality of frame units 2 arranged in an array, each of the frame units 2 includes a base island 23, an anode pin 22, and a cathode pin 21, the base island 23 is disposed on the anode pin 22, the anode pin 22 and the cathode pin 21 are both provided with a T-shaped pin portion 24, and the pin portion 24 is provided with a groove 241, and the method includes the following steps:
providing a lead frame 100, a MOS chip 200, an IC chip 300 and a capacitor 400;
an upper core, which fixes the MOS chip 200, the IC chip 300 and the capacitor 400 on the base island 23 of the anode pin 22;
bonding, namely bonding the MOS chip 200, the IC chip 300 and the capacitor 400 by using a copper wire (or a gold wire) 500, and bonding the MOS chip 200 and the cathode lead 21 by using an aluminum tape 600;
cleaning, namely cleaning the lead frame 100 welded with the MOS chip 200, the IC chip 300 and the capacitor 400;
plastic packaging, namely packaging the cleaned lead frame 100 by using a plastic packaging material to form a plastic packaging body 700, and leaking the anode pin 22 and the cathode pin 21;
tinning, namely electroplating and tinning the lead frame 100 after plastic packaging;
cutting ribs, testing, printing characters, packaging and delivering.
Specifically, in this embodiment, the lead frame 100 is arranged in three rows, each row is provided with 5 frame units 2, and one lead frame 100 can encapsulate 15 photovoltaic bypass modules, so that the production efficiency and the utilization rate of raw materials can be effectively improved, and the production cost can be reduced. Each frame unit 2 comprises an anode pin 22 and a cathode pin 21, the anode pin 22 and the cathode pin 21 are marked with a plus sign and a minus sign respectively, so that the polarity of a device can be conveniently distinguished after plastic package; the base island 23 is located on the anode pin 22, the anode pin 22 and the cathode pin 21 are both provided with a pin part 24, the pin part 24 is in a T shape, and the pin part 24 is provided with a groove 241, so that the fixing position and the pin shaping in use are facilitated. The lead frame 100 provides support for the entire photovoltaic bypass module and provides electrical connection to the outside.
Wherein, the anode pin 22 and the cathode pin 21 are both provided with a tin-coating area 25 for coating tin during use; the anode pin 22 and the cathode pin 21 are respectively provided with glue locking holes 26 with different shapes, such as a bar shape, a circular shape, a semicircular shape and the like, in this embodiment, the cathode pin 21 is provided with a bar glue locking hole and a group of symmetrical circular glue locking holes, the anode pin 22 is provided with a bar glue locking hole, a group of symmetrical semicircular glue locking holes and a group of symmetrical circular glue locking holes, and meanwhile, the back side of the anode pin 22 corresponding to the base island 23 is provided with the bur 27, so that the bonding strength of the lead frame 100 and the plastic package material during plastic package can be enhanced, and the plastic package material is prevented from overflowing and being layered.
In addition, the lead frame 100 is made of bare copper, the base island 23 on the anode pin 22 is divided into a silver plating area 231 and a roughening area 232, the silver plating area 231 is subjected to silver plating, the roughening area 232 is subjected to bare copper roughening, and specifically, the silver plating area 231 on the base island 23 on the anode pin 22 is subjected to silver plating, so that press welding and routing are facilitated, and the reliability of welding spots is enhanced; the coarsening region 232 is coarsened by bare copper, so that the core loading is facilitated, and the bonding strength between the MOS chip 200 and the base island 23 is enhanced.
In detail, the method for packaging the photovoltaic bypass module is described below by taking the lead frame 100 shown in fig. 1 as an example.
Step S1: the lead frame 100, the MOS chip 200, the IC chip 300, and the capacitor 400 are provided to prepare a package. Specifically, a plurality of frame units 2 are arranged on the frame body 1 in three rows, and are connected together to form a lead frame 100; a plurality of frame units 2 in the lead frame 100 are packaged simultaneously, and during packaging, one frame unit 2 corresponds to one MOS chip 200, two IC chips 300 and one capacitor 400, so as to form one photovoltaic bypass module.
To obtain the MOS chip 200 and the IC chip 300, a dicing process is performed. Fixing the wafer from the back by adopting a blue film, and separating the MOS chips 200 along scribing lanes by using a diamond scribing knife to obtain a plurality of independent MOS chips 200;
step S2: and an upper core, wherein the MOS chip 200, the IC chip 300 and the capacitor 400 are fixed on the base island 23 of the anode pin 22. In this step: the MOS chip 200 is soldered on the base island 23 of the anode lead 22 using a soft solder process. The MOS chip 200 is soldered on the base island 23 with soft solder according to the required soldering temperature, soldering pressure and soldering time, and the electrical connection of the MOS chip 200 and the lead frame 100 is achieved. When going up the core the solder layer thickness of soft solder is 25 ~ 55um, for example 35um, and the welding voidage is whole to be controlled within 200 area 5% of MOS chip, and single cavity size needs to be controlled within 200 area 2% of MOS chip, still takes place the warpage when preventing to weld simultaneously, goes up core and accomplishes back MOS chip 200 thrust and need satisfy minimum requirement. The soft solder can be high lead solder (Pb95.5Sn2Ag2.5) or lead-free solder.
The IC chip 300 and the capacitor 400 are soldered to the base island 23 of the anode lead 22 by a dispensing process, and are baked and cured in nitrogen. Specifically, the IC chips 300 and the capacitor 400 are fixed by using a han-gao or amiable sesami product, and are welded on one side of the MOS chip 200, and the two IC chips 300 are located between the capacitor 400 and the MOS chip 200, the dispensing thickness is 20-30 um, in this embodiment 20um, and then the lead frame 100 after dispensing is placed in a nitrogen environment for baking, the baking temperature is 150-170 ℃, in this embodiment 170 ℃, the baking time is 60-90 min, in this embodiment 90 min.
Step S3: the MOS chip 200, the IC chip 300 and the capacitor 400 are bonded by using a copper wire (or gold wire) 500, and the MOS chip 200 and the cathode lead 21 are bonded by using an aluminum tape 600. As shown in fig. 5, specifically, the frame with the core is bonded, and a copper wire (or gold wire) 500 is welded between the MOS chip 200 and the IC chip 300, between the MOS chip 200 and the capacitor 400, and between the IC chip 300 and the capacitor 400 by using an ultrasonic welding process, where the surface of the capacitor 400 includes a gold plating layer. The bonding material is copper wire (or gold wire) meeting the wire diameter requirement, and bonding is performed on the surfaces of the MOS chip 200 and the capacitor 400. In this embodiment, two IC chips 300, namely a first IC chip 301 and a second IC chip 302, are provided, and when bonding, the first IC chip 301 and the second IC chip 302 are bonded through 1 copper wire (or gold wire), the second IC chip 302 is bonded with the capacitor 400 through 2 copper wires (or gold wires), and the MOS chip 200 is bonded with the second IC chip 302 through 2 copper wires (or gold wires). Thus, the electrical connection between the MOS chip 200 and the IC chip 300, between the MOS chip 200 and the capacitor 400, and between the IC chip 300 and the capacitor 400 can be realized. The MOS chip 200 and the IC chip 300, and the MOS chip 200 and the capacitor 400 are bonded by copper wires (or gold wires), so that the on-resistance can be reduced by 20-30%.
And bonding one end of the aluminum strip 600 with the source electrode of the MOS chip 200 and bonding the other end with the cathode lead 21 by adopting an ultrasonic welding process. Wherein, under the ultrasonic bonding process, the jumping is completed on the surface of the MOS chip 200, and then the MOS chip is connected with the cathode lead 21. In this embodiment, one end of the aluminum strip 600 is welded to the MOS chip 200 at the first welding position 801, and the other end is welded to the cathode pin 21 at the second welding position 802, specifically, the first welding position 801 having the same width as the aluminum strip 600 is pressed out on the MOS chip 200 by using a welding chopper, and one end of the aluminum strip 600 is welded to the MOS chip 200; and then a second welding position 802 with the width consistent with that of the aluminum strip 600 is pressed on the cathode pin 21 by a welding chopper, and the other end of the aluminum strip 600 is welded with the cathode pin 21. For a MOS chip 200 with a larger dimension, the width dimension of the aluminum strip 600 may be increased accordingly. It should be ensured that the size of the aluminum strip 600 contacting the MOS chip 200 does not exceed the outer profile of the MOS chip 200 to avoid short circuit.
The aluminum strip 600 is further soldered to the MOS chip 200 at a third soldering location 803, and the third soldering location 803 is disposed between the first soldering location 801 and the second soldering location 802. The welding chopper can also press a third welding position 803 on the MOS chip 200, so that one end of the aluminum strip 600 is welded with the MOS chip 200, the other end of the aluminum strip is welded with the cathode pin 21, and the aluminum strip 600 can also be welded with the MOS chip 200 at the third welding position 803, so as to ensure the reliability and the overall strength of the welding of the aluminum strip 600. The MOS chip 200 and the cathode pin 21 are bonded by the aluminum strip 600, so that the on-resistance can be reduced by 10-20%, the conduction loss can be reduced, the current impact resistance can be improved, the wider conductive aluminum strip 600 is used for bonding, the thermal resistance can be effectively reduced by 20-30%, and the heat conductivity can be improved. During the bonding process, attention should be paid to the magnitude of the bonding force to prevent the surface of the MOS chip 200 from being crated or the MOS chip 200 from being cracked due to the fact that the surface of the MOS chip 200 is pressed too much by the cleaver.
Step S4: and (5) cleaning. The lead frame 100 to which the MOS chip 200, the IC chip 300, and the capacitor 400 are bonded is cleaned. Specifically, the bonded lead frame 100 is cleaned by a plasma cleaning machine, and the purpose of removing stains on the surface of an object is achieved by the activation of active particles in plasma.
Step S5: and (3) plastic packaging, namely packaging the cleaned lead frame 100 by using a plastic packaging material to form a plastic packaging body 700, and leaking the anode pin 22 and the cathode pin 21. Specifically, according to the specification of the plastic package material meeting the requirements, the plastic package material is selected according to the used frame, stress and water absorption are more emphatically considered, the plastic package materials of the same specification series such as the Sumitomo 7XXX series and the amiable Sedi 9XXX series are selected, the series of plastic package materials are environment-friendly plastic package materials with high reliability, low stress, low warpage and low water absorption, and after plastic package forming, the surface of the plastic package body 700 has no burrs, sand holes and the like, so that the packaging requirements are met.
And in the plastic packaging step, the curing treatment after plastic packaging is further included, so that the inside of the plastic packaging material is completely reacted in a high-temperature environment, the curing temperature is 175 ℃, and the curing time is 8 hours. The high temperature can make the plastic package material and the lead frame 100 combined more tightly, and prevent the delamination. The plastic package body 700 obtained by plastic packaging completely covers all the MOS chips 200 and the capacitors 400, so as to facilitate sealing protection.
Step S6: and (4) screening. And the screening step adopts a reflow soldering process to carry out quality screening. The hidden failure problem in the plastic package body 700 is exposed in advance through a reflow soldering process, so that defective products are prevented from flowing into a client, and the yield is further improved; in the embodiment, the products are screened by adopting a reflow soldering curve at 260 ℃, and reflow soldering is simulated for 1-3 times.
And in the screening step, a cold-hot impact test is carried out through a cold-hot impact test. Specifically, a cold and hot impact test is carried out through the cold and hot impact test box, so that the quality of the product is confirmed, and the product is convenient to sort in a subsequent test.
Step S7: and (6) coating tin. And electroplating tin on the lead frame 100 after the plastic package. Specifically, the frame part exposed outside after packaging is electroplated with tin, so that oxidation is prevented in the processes of storage and transportation, and the yield of products at a client is improved.
Step S8: cutting ribs, testing and printing, packaging and delivering. Specifically, the method comprises the following steps:
s81: and (6) cutting ribs. And selecting a specific mould according to the frame to separate the connected devices into independent devices.
S82: and testing and printing. Specifically, according to the designed performance requirements of the devices, performance detection is carried out on each independent device, whether the performance parameter standard is met or not is tested, laser printing is carried out on qualified products, and printing information comprises product models and production dates.
S83: and (7) packaging and delivering. And packaging and delivering a plurality of mutually independent devices.
In summary, in the encapsulation method of the photovoltaic bypass module provided by the embodiment of the invention, the frame units arranged in multiple rows can effectively improve the production efficiency and the utilization rate of raw materials, and reduce the production cost; in the packaging process, copper wires or gold wires are used for bonding among chips and between the chips and the capacitor, so that the on-resistance can be reduced by 20-30%, and the reliability of welding spots is improved; the MOS chip and the cathode pin are bonded by adopting an aluminum tape, so that the on-resistance can be reduced by 10-20%, the on-loss is reduced, and the current impact resistance is improved; and bonding is carried out by using a wider aluminum tape, so that the thermal resistance can be effectively reduced by 20-30%, and the heat conduction capability is improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A packaging method of a photovoltaic bypass module is characterized in that a lead frame of the photovoltaic bypass module comprises a frame body and a plurality of frame units which are arranged in an array mode, each frame unit comprises a base island, an anode pin and a cathode pin, the base island is arranged on the anode pin, the anode pin and the cathode pin are both provided with T-shaped pin parts, grooves are formed in the pin parts, and the packaging method comprises the following steps:
providing a lead frame, an MOS chip, an IC chip and a capacitor;
the MOS chip, the IC chip and the capacitor are fixed on the base island of the anode pin;
bonding, namely bonding the MOS chip, the IC chip and the capacitor by adopting a copper wire or a gold wire, and bonding the MOS chip and the cathode pin by adopting an aluminum tape;
cleaning, namely cleaning the lead frame welded with the MOS chip, the IC chip and the capacitor;
plastic packaging, namely packaging the cleaned lead frame by using a plastic packaging material to form a plastic packaging body, and externally leaking the anode pin and the cathode pin;
tinning, namely electroplating tinning the lead frame subjected to plastic packaging;
cutting ribs, testing characters and packaging for shipment.
2. The method of packaging a photovoltaic bypass module as recited in claim 1, wherein: the base island on the anode pin is divided into a silver plating area and a coarsening area, the silver plating area is subjected to silver plating treatment, the coarsening area is subjected to bare copper coarsening treatment, and the back side of the anode pin corresponding to the base island is provided with pits.
3. The method of encapsulating a photovoltaic bypass module according to claim 1 or 2, characterized in that: the frame units are arranged in three rows.
4. The method of claim 1, wherein the step of attaching the MOS chip, the IC chip and the capacitor to the base island of the anode lead comprises:
welding the MOS chip on the base island of the anode pin by adopting a soft solder process;
and welding the IC chip and the capacitor on the base island of the anode pin by adopting a dispensing process, and baking and curing by using nitrogen.
5. The method of packaging a photovoltaic bypass module as recited in claim 4, wherein: the thickness of the solder layer of the soft solder is 25-55 um; the dispensing thickness is 20-30 um, the baking temperature is 150-170 ℃, and the baking time is 60-90 min.
6. The method of packaging a photovoltaic bypass module according to claim 1, wherein the bonding step comprises:
welding copper wires or gold wires between the MOS chip and the IC chip, between the MOS chip and the capacitor and between the IC chip and the capacitor by adopting an ultrasonic welding process, wherein the surface of the capacitor contains a gold-plated layer;
and bonding one end of the aluminum strip with the source electrode of the MOS chip and bonding the other end of the aluminum strip with the cathode pin by adopting an ultrasonic welding process.
7. The method of packaging a photovoltaic bypass module as recited in claim 1, wherein: and in the cleaning step, a plasma cleaning machine is adopted to clean the bonded lead frame.
8. The method of packaging a photovoltaic bypass module as recited in claim 1, wherein: and in the plastic packaging step, the curing treatment after the plastic packaging is also included, wherein the curing temperature is 175 ℃, and the curing time is 8 hours.
9. The method of packaging a photovoltaic bypass module as recited in claim 1, wherein: and after the plastic packaging step and before the tinning step, the method further comprises a screening step, wherein the screening step adopts a reflow soldering process to carry out quality screening.
10. The method of packaging a photovoltaic bypass module as recited in claim 9, wherein: and in the screening step, a cold-hot impact test is carried out through a cold-hot impact test.
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| CN202111275699.9A CN114005761A (en) | 2021-10-29 | 2021-10-29 | Packaging method of photovoltaic bypass module |
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