CN114005755A - Fin type field effect transistor and manufacturing method thereof - Google Patents
Fin type field effect transistor and manufacturing method thereof Download PDFInfo
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- CN114005755A CN114005755A CN202010738403.1A CN202010738403A CN114005755A CN 114005755 A CN114005755 A CN 114005755A CN 202010738403 A CN202010738403 A CN 202010738403A CN 114005755 A CN114005755 A CN 114005755A
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- isolation film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 83
- 239000001301 oxygen Substances 0.000 claims abstract description 83
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 83
- 238000002955 isolation Methods 0.000 claims abstract description 76
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 230000005669 field effect Effects 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a fin field effect transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin part positioned on one side of the semiconductor substrate and a mask layer positioned on the surface of one side, away from the semiconductor substrate, of the fin part; forming an oxygen isolation film along an exposed surface of the base structure having the fin side; forming a dielectric layer to cover the oxygen isolation film; carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed; etching and removing the mask layer and the parts of the dielectric layer and the oxygen isolation film corresponding to the removal area; and forming a gate structure crossing the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate. According to the invention, oxygen elements are isolated from entering the fin part through the oxygen isolation film, so that the condition that the side wall of the fin part is oxidized to reduce the flatness of the fin part is improved, the high flatness of the side wall of the prepared fin part is ensured, the preparation quality of the fin field effect transistor is improved, and the excellent performance of the fin field effect transistor is ensured.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a fin type field effect transistor and a manufacturing method thereof.
Background
In the development of semiconductor very large scale integrated circuits, the density and performance of transistors are continuously and systematically increased following moore's law under the direction of scaling of CMOS devices. However, when the feature size (CD) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor cannot meet the requirement for the device performance, and the multi-gate device is widely paid attention as a substitute for the conventional device. A fin field effect transistor (FinFET) is a common multi-gate device, but the existing fin field effect transistor is poor in shape during preparation, and the performance of the fin field effect transistor is influenced.
Disclosure of Invention
In view of this, the invention provides a fin field effect transistor and a manufacturing method thereof, which effectively solve the technical problems in the prior art, improve the manufacturing quality of the fin field effect transistor, and ensure the excellent performance of the fin field effect transistor.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a method for manufacturing a fin field effect transistor comprises the following steps:
providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin part positioned on one side of the semiconductor substrate and a mask layer positioned on the surface of one side, away from the semiconductor substrate, of the fin part;
forming an oxygen isolation film along an exposed surface of the base structure having the fin side;
forming a dielectric layer to cover the oxygen isolation film, wherein the dielectric layer is sequentially divided into a reserved area and a removed area in the direction from the semiconductor substrate to the fin part;
carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed;
etching and removing the mask layer, the dielectric layer and the oxygen isolation film corresponding to the removal area;
and forming a gate structure spanning the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate.
Optionally, forming an oxygen isolation film along an exposed surface of the base structure having the fin side includes:
and forming a silicon nitride film along the exposed surface of the base structure with the fin side, wherein the silicon nitride film is the oxygen isolation film.
Optionally, forming an oxygen isolation film along an exposed surface of the base structure having the fin side includes:
and sequentially forming a silicon nitride film and a polysilicon film along the exposed surface of the base structure on the fin side, wherein the laminated film of the silicon nitride film and the polysilicon film is the oxygen isolation film.
Optionally, forming a dielectric layer to cover the oxygen isolation film includes:
and forming a silicon oxide layer to cover the oxygen isolation film, wherein the silicon oxide layer is the dielectric layer.
Optionally, the silicon oxide layer is further doped with nitrogen.
Correspondingly, the invention also provides a fin field effect transistor, which comprises:
a semiconductor substrate;
at least one fin portion located on one side of the semiconductor substrate;
the oxygen isolation film covers the exposed surface of the semiconductor substrate and extends to cover the side face of the fin part;
the dielectric layer covers the oxygen isolation film, and the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, is flush with the surface of the end part, extending to the fin part, of the oxygen isolation film;
and the grid electrode structure is positioned on one side of the dielectric layer, which is far away from the semiconductor substrate, and spans the fin part.
Optionally, the oxygen isolation film comprises a silicon nitride film.
Optionally, the oxygen isolation film includes a stacked film of a silicon nitride film and a polysilicon film, wherein the silicon nitride film is located on a side of the oxygen isolation film close to the semiconductor substrate.
Optionally, the dielectric layer includes a silicon oxide layer.
Optionally, the silicon oxide layer is further doped with nitrogen.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a fin field effect transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin part positioned on one side of the semiconductor substrate and a mask layer positioned on the surface of one side, away from the semiconductor substrate, of the fin part; forming an oxygen isolation film along an exposed surface of the base structure having the fin side; forming a dielectric layer to cover the oxygen isolation film, wherein the dielectric layer is sequentially divided into a reserved area and a removed area in the direction from the semiconductor substrate to the fin part; carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed; etching and removing the mask layer, the dielectric layer and the oxygen isolation film corresponding to the removal area; and forming a gate structure spanning the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate.
According to the invention, the oxygen isolation film is preferentially prepared before the dielectric layer is prepared, and oxygen elements are isolated from entering the fin part through the oxygen isolation film, so that the condition that the side wall of the fin part is oxidized to reduce the flatness of the fin part is improved, the flatness of the side wall of the prepared fin part is ensured to be high, the preparation quality of the fin field effect transistor is improved, and the excellent performance of the fin field effect transistor is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for fabricating a fin field effect transistor according to an embodiment of the invention;
FIGS. 2 to 7 are schematic structural diagrams corresponding to the steps in FIG. 1;
FIG. 8 is a schematic structural diagram of an oxygen barrier film according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another oxygen barrier film according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, during the development of semiconductor very large scale integrated circuits, the density and performance of transistors are continuously and systematically increasing following moore's law under the direction of scaling of CMOS devices. However, when the feature size (CD) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor cannot meet the requirement for the device performance, and the multi-gate device is widely paid attention as a substitute for the conventional device. A fin field effect transistor (FinFET) is a common multi-gate device, but the existing fin field effect transistor is poor in shape during preparation, and the performance of the fin field effect transistor is influenced.
Based on the above, the embodiment of the invention provides a fin field effect transistor and a manufacturing method thereof, which effectively solve the technical problems in the prior art, improve the preparation quality of the fin field effect transistor and ensure the excellent performance of the fin field effect transistor.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 9.
Referring to fig. 1, a flow chart of a method for fabricating a fin field effect transistor according to an embodiment of the present invention is shown, wherein the method comprises:
s1, providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin portion located on one side of the semiconductor substrate, and a mask layer located on the surface of one side, away from the semiconductor substrate, of the fin portion.
And S2, forming an oxygen isolation film along the exposed surface of the base structure with the fin side.
And S3, forming a dielectric layer to cover the oxygen isolation film, wherein the dielectric layer is sequentially divided into a reserved area and a removed area in the direction from the semiconductor substrate to the fin portion.
And S4, carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed.
And S5, etching and removing the mask layer and the parts of the dielectric layer and the oxygen isolation film corresponding to the removal area.
And S6, forming a gate structure crossing the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate.
It should be noted that the source and the drain provided in the embodiments of the present invention may be formed after forming a fin portion on a semiconductor substrate, or after removing portions of a mask layer, a dielectric layer, and an oxygen isolation film corresponding to a removal region and before preparing a gate structure, and the like.
It can be understood that, in the embodiment of the invention, an oxygen isolation film is preferentially prepared before the dielectric layer is prepared, and oxygen element is isolated from entering the fin portion by the oxygen isolation film, so that the condition that the sidewall of the fin portion is oxidized to reduce the flatness of the fin portion is improved, the prepared sidewall of the fin portion is ensured to have high flatness, the preparation quality of the fin field effect transistor is improved, and the excellent performance of the fin field effect transistor is ensured.
The following describes the manufacturing method according to the embodiment of the present invention in more detail with reference to fig. 2 to 7, and fig. 2 to 7 are schematic structural diagrams corresponding to the steps in fig. 1.
As shown in fig. 2, corresponding to step S1, a base structure is provided, where the base structure includes a semiconductor substrate 100, at least one fin 200 located on one side of the semiconductor substrate 100, and a mask layer 300 located on a surface of the fin 200 facing away from the semiconductor substrate 100.
In an embodiment of the present invention, the semiconductor substrate and the fin portion provided by the present invention may be made of silicon, and the mask layer provided by the embodiment of the present invention may be made of silicon nitride; alternatively, the semiconductor substrate, the fin portion and the mask layer may be made of other materials in other embodiments of the present invention, and the present invention is not limited thereto.
The semiconductor substrate and the fin part provided by the embodiment of the invention can be formed by etching a semiconductor substrate, namely, the semiconductor substrate is provided firstly; then preparing a mask layer on the surface of one side of the semiconductor substrate, wherein the mask layer covers the corresponding area of the fin part; and etching the semiconductor substrate in the region outside the mask layer to form a plurality of isolation trenches, wherein the protruding parts between the isolation trenches are fin parts, and the rest parts below the protruding parts are the semiconductor substrate.
As shown in fig. 3, in step S2, an oxygen barrier film 400 is formed along the exposed surface of the base structure on the side having the fin 200.
It can be understood that the oxygen isolation film provided by the embodiment of the invention has the performance of isolating oxygen elements, and the oxygen elements are isolated from entering the fin portion through the oxygen isolation film, so that the condition that the side wall of the fin portion is oxidized to reduce the flatness of the fin portion is improved, the flatness of the side wall of the prepared fin portion is high, the preparation quality of the fin field effect transistor is improved, and the excellent performance of the fin field effect transistor is ensured.
In an embodiment of the present invention, the forming of the oxygen isolation film along the exposed surface of the base structure having the fin side includes: and forming a silicon nitride film along the exposed surface of the base structure with the fin side, wherein the silicon nitride film is the oxygen isolation film. Specifically, as shown in fig. 8, a schematic structural diagram of an oxygen isolation film according to an embodiment of the present invention is provided, wherein the oxygen isolation film 400 may include a silicon nitride film 410. Alternatively, embodiments of the present invention provide silicon nitride film 410 having a thickness in the range of 1.5 nm to 2 nm, inclusive.
Alternatively, the forming an oxygen isolation film along the exposed surface of the base structure having the fin side according to the embodiment of the present invention includes: and sequentially forming a silicon nitride film and a polysilicon film along the exposed surface of the base structure on the fin side, wherein the laminated film of the silicon nitride film and the polysilicon film is the oxygen isolation film. Specifically, as shown in fig. 9, a schematic structural diagram of another oxygen isolation film according to an embodiment of the present invention is provided, wherein the oxygen isolation film 400 may include a stacked film of a silicon nitride film 420 and a polysilicon film 430. Optionally, the thickness of the silicon nitride film 420 provided by the embodiment of the present invention may range from 1.5 nm to 2 nm, inclusive; and the polysilicon film 430 provided by embodiments of the present invention may have a thickness ranging from 0.8 nm to 1.2 nm, inclusive.
As shown in fig. 4, corresponding to step S3, a dielectric layer 500 is formed to cover the oxygen isolation film 400, and the dielectric layer 500 is sequentially divided into a reserved region S1 and a removed region S2 in the direction from the semiconductor substrate 100 to the fin 200, wherein the removed region S2 at least includes the mask layer 300.
In an embodiment of the present invention, after the preparation of the oxygen isolation film, the shape of the surface of the oxygen isolation film is the same as the shape of the surface of the base structure having the fin portion, so that the dielectric material is filled on the oxygen isolation film side to form a dielectric layer covering the oxygen isolation film. The dielectric layer provided by the invention can be made of silicon oxide. Namely, the forming of the dielectric layer to cover the oxygen isolation film provided by the embodiment of the invention comprises: and forming a silicon oxide layer to cover the oxygen isolation film, wherein the silicon oxide layer is the dielectric layer.
Furthermore, the silicon oxide layer provided by the embodiment of the invention is doped with nitrogen elements, so that oxygen atoms can be further prevented from entering the fin portion. Optionally, the concentration of nitrogen doped in the silicon oxide layer provided in the embodiment of the present invention is not more than 5%.
As shown in fig. 5, corresponding to step S4, a planarization process is performed on a surface of the dielectric layer 500 away from the semiconductor substrate 100 until the mask layer 300 is exposed.
In an embodiment of the invention, the dielectric layer can be planarized by chemical mechanical polishing or other processes.
As shown in fig. 6, corresponding to step S5, the mask layer 300, the dielectric layer 500, and the oxygen isolation film 400 are etched to remove the portions corresponding to the removal region S2.
As shown in fig. 7, corresponding to step S6, a gate structure 600 is formed across the fin 200 on a side of the dielectric layer 300 away from the semiconductor substrate 100.
Correspondingly, the embodiment of the invention also provides a fin field effect transistor, and the fin field effect transistor provided by the embodiment of the invention is manufactured by adopting the manufacturing method provided by any one of the embodiments. Referring to fig. 7, a finfet according to an embodiment of the present invention includes:
a semiconductor substrate 100.
At least one fin 200 located at one side of the semiconductor substrate 100.
An oxygen isolation film 400 covering the exposed surface of the semiconductor substrate 100 and extending to cover the side surface of the fin 200.
And the dielectric layer 500 covers the oxygen isolation film 400, and the surface of one side of the dielectric layer 500, which is far away from the semiconductor substrate 100, is flush with the surface of the end part of the fin part 200 where the oxygen isolation film 400 extends.
And a gate structure 600 located on a side of the dielectric layer 500 away from the semiconductor substrate 100 and crossing the fin 200.
In an embodiment of the present invention, the oxygen isolation film provided by the present invention includes a silicon nitride film. Optionally, the thickness of the silicon nitride film provided by the embodiment of the invention may range from 1.5 nm to 2 nm, inclusive. Alternatively, the oxygen isolation film provided by the embodiment of the present invention includes a stacked film of a silicon nitride film and a polysilicon film, wherein the silicon nitride film is located on a side of the oxygen isolation film close to the semiconductor substrate. Optionally, the thickness of the silicon nitride film provided by the embodiment of the present invention may range from 1.5 nm to 2 nm, inclusive; and the polysilicon film provided by the embodiments of the present invention may have a thickness ranging from 0.8 nm to 1.2 nm, inclusive.
In an embodiment of the invention, the dielectric layer provided by the invention includes a silicon oxide layer. Further, the silicon oxide layer provided by the embodiment of the invention is doped with nitrogen element. Optionally, the concentration of nitrogen doped in the silicon oxide layer provided in the embodiment of the present invention is not more than 5%.
The embodiment of the invention provides a fin field effect transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin part positioned on one side of the semiconductor substrate and a mask layer positioned on the surface of one side, away from the semiconductor substrate, of the fin part; forming an oxygen isolation film along an exposed surface of the base structure having the fin side; forming a dielectric layer to cover the oxygen isolation film, wherein the dielectric layer is sequentially divided into a reserved area and a removed area in the direction from the semiconductor substrate to the fin part; carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed; etching and removing the mask layer, the dielectric layer and the oxygen isolation film corresponding to the removal area; and forming a gate structure spanning the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate.
As can be seen from the above, in the embodiment of the invention, an oxygen isolation film is preferentially prepared before the dielectric layer is prepared, and oxygen is isolated from entering the fin portion by the oxygen isolation film, so that the condition that the sidewall of the fin portion is oxidized to reduce the flatness of the fin portion is improved, the flatness of the sidewall of the prepared fin portion is ensured to be high, the preparation quality of the fin field effect transistor is improved, and the excellent performance of the fin field effect transistor is ensured.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:
providing a base structure, wherein the base structure comprises a semiconductor substrate, at least one fin part positioned on one side of the semiconductor substrate and a mask layer positioned on the surface of one side, away from the semiconductor substrate, of the fin part;
forming an oxygen isolation film along an exposed surface of the base structure having the fin side;
forming a dielectric layer to cover the oxygen isolation film, wherein the dielectric layer is sequentially divided into a reserved area and a removed area in the direction from the semiconductor substrate to the fin part;
carrying out planarization treatment on the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, until the mask layer is exposed;
etching and removing the mask layer, the dielectric layer and the oxygen isolation film corresponding to the removal area;
and forming a gate structure spanning the fin part on one side of the dielectric layer, which is far away from the semiconductor substrate.
2. The method of claim 1, wherein forming an oxygen isolation film along an exposed surface of the base structure having the fin side comprises:
and forming a silicon nitride film along the exposed surface of the base structure with the fin side, wherein the silicon nitride film is the oxygen isolation film.
3. The method of claim 1, wherein forming an oxygen isolation film along an exposed surface of the base structure having the fin side comprises:
and sequentially forming a silicon nitride film and a polysilicon film along the exposed surface of the base structure on the fin side, wherein the laminated film of the silicon nitride film and the polysilicon film is the oxygen isolation film.
4. The method of claim 1, wherein forming a dielectric layer overlying the oxygen isolation film comprises:
and forming a silicon oxide layer to cover the oxygen isolation film, wherein the silicon oxide layer is the dielectric layer.
5. The method of claim 4, wherein the silicon oxide layer is further doped with nitrogen.
6. A fin field effect transistor, comprising:
a semiconductor substrate;
at least one fin portion located on one side of the semiconductor substrate;
the oxygen isolation film covers the exposed surface of the semiconductor substrate and extends to cover the side face of the fin part;
the dielectric layer covers the oxygen isolation film, and the surface of one side of the dielectric layer, which is far away from the semiconductor substrate, is flush with the surface of the end part, extending to the fin part, of the oxygen isolation film;
and the grid electrode structure is positioned on one side of the dielectric layer, which is far away from the semiconductor substrate, and spans the fin part.
7. The fin-type field effect transistor of claim 1, wherein the oxygen isolation film comprises a silicon nitride film.
8. The fin field effect transistor of claim 1, wherein the oxygen isolation film comprises a stacked film of a silicon nitride film and a polysilicon film, wherein the silicon nitride film is located on a side of the oxygen isolation film adjacent to the semiconductor substrate.
9. The fin-fet of claim 1, wherein the dielectric layer comprises a silicon oxide layer.
10. The fin-fet of claim 9, wherein the silicon oxide layer is further doped with an element of nitrogen.
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| CN109427684A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and method |
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