TW519761B - MOS device having dual-gate insulation layer and its manufacturing method - Google Patents

MOS device having dual-gate insulation layer and its manufacturing method Download PDF

Info

Publication number
TW519761B
TW519761B TW90128594A TW90128594A TW519761B TW 519761 B TW519761 B TW 519761B TW 90128594 A TW90128594 A TW 90128594A TW 90128594 A TW90128594 A TW 90128594A TW 519761 B TW519761 B TW 519761B
Authority
TW
Taiwan
Prior art keywords
gate
insulating layer
layer
semiconductor substrate
patent application
Prior art date
Application number
TW90128594A
Other languages
Chinese (zh)
Inventor
Wen-Ping Yen
Yun-Hsiu Chen
Hung-Cheng Weng
Original Assignee
Silicon Integrated Sys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Integrated Sys Corp filed Critical Silicon Integrated Sys Corp
Priority to TW90128594A priority Critical patent/TW519761B/en
Application granted granted Critical
Publication of TW519761B publication Critical patent/TW519761B/en
Priority to US10/382,842 priority patent/US20030146478A1/en

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of MOS device having dual-gate insulation layer includes the followings: a semiconductor substrate; the first gate insulation layer formed on a predetermined region surface of the semiconductor substrate; the second gate insulation layer formed on the region excluding the predetermined region of the semiconductor substrate to surround the first gate insulation layer, in which the second gate insulation layer thickness is larger than the first gate insulation layer thickness; and a gate layer, in which the bottom center portion of the gate layer covers the first gate insulation layer surface and the bottom edge portion of the gate layer extends to cover the second gate insulation layer surface.

Description

519761 五、發明說明(1) 本發明係有關於一種金屬氧化半導體(metal—oxide-semiconductor,M0S)元件之製作方法,特別有關於一種 具有雙閘極絕緣層(dual gate insulator)之M0S元件的結 構及其製作方法。 目前在高積集度之VLSI或ULSI製程中,會在主動區内 製作高壓元件與低壓元件,並在週邊電路區中製作高壓的 I/O元件。由於高壓元件之通道長度(channel length)較 長且所需之閘極絕緣層厚度較大,因此在閘極絕緣層的製 作上會遭遇到如何提供兩種厚度的問題。 請參考第1A至1E圖,其顯示習知高壓M0S元件區與低 壓M0S元件區之製作方法的剖面示意圖。如第u圖所示, 一半導體基底10包含有複數個場氧化隔離區12,用來區隔 相鄰之主動區域,如高壓M0S元件區I以及低壓元件區 I I。習知製作方法,如第1 B圖所示,首先於半導體基底丄〇 表面上形成一第一氧化層1 4,然後利用微影蝕刻製程將位 於低壓M0S元件區II之第一氧化層14去除,僅使第一氧化 層14殘畕於南壓M0S元件區II之表面上。然後,再於半導 體基底10表面上形成一第二氧化層16,以覆蓋住第一氧化 層14以及半導體基底10之曝露表面上。如此一來,高壓 M0S το件區I之閘極絕緣層係由第一氧化層丨4與第二氧化層 1 6所堆疊而成’而低壓m〇S元件區I I之閘極絕緣層係由第 二氧化層16所構成,故可使低壓M〇s元件區π具有較薄之 閘極絕緣層。後續,如第1C圖所示,於半導體基底1〇表面 上沉積一多晶矽層,再利用微影蝕刻製程將多晶矽層定義519761 V. Description of the invention (1) The present invention relates to a method for manufacturing a metal-oxide-semiconductor (MOS) device, and more particularly to a MOS device having a dual gate insulator. Structure and manufacturing method. At present, in high-integration VLSI or ULSI processes, high-voltage components and low-voltage components are produced in the active area, and high-voltage I / O components are produced in the peripheral circuit area. As the channel length of the high-voltage component is longer and the thickness of the required gate insulating layer is larger, the problem of how to provide two thicknesses in the gate insulating layer is encountered. Please refer to FIGS. 1A to 1E, which are schematic cross-sectional views showing a conventional method for manufacturing a high-voltage M0S element region and a low-voltage M0S element region. As shown in FIG. U, a semiconductor substrate 10 includes a plurality of field oxide isolation regions 12 to isolate adjacent active regions, such as a high-voltage MOS device region I and a low-voltage device region I I. In a conventional manufacturing method, as shown in FIG. 1B, a first oxide layer 14 is first formed on the surface of the semiconductor substrate 丄, and then the first oxide layer 14 located in the low-voltage MOS device region II is removed by a lithography etching process. Only the first oxide layer 14 is left on the surface of the south-voltage MOS device region II. Then, a second oxide layer 16 is formed on the surface of the semiconductor substrate 10 so as to cover the exposed surface of the first oxide layer 14 and the semiconductor substrate 10. In this way, the gate insulating layer of the high-voltage MOS device region I is formed by stacking the first oxide layer 4 and the second oxide layer 16 ′, and the gate insulating layer of the low-voltage MOS device region II is composed of The second oxide layer 16 is formed, so that the low-voltage Mos element region π can have a thin gate insulating layer. Subsequently, as shown in FIG. 1C, a polycrystalline silicon layer is deposited on the surface of the semiconductor substrate 10, and then the polycrystalline silicon layer is defined by a lithography etching process.

519761 五、發明說明(2) 形成間極層之圖案’以於高壓MGS元件區I形成-第一閘極 層18,而於低壓刪元件區Η形成―第二閘極層 此外’·有繁於通道長度之縮短設計會使熱載子效應 、及0極:fect)益加嚴重’因此設計出-種輕摻雜 /乂笛=:ped dr,ins,LDD)、结構來解決這個問題 置篡,、隹二一=换利用第一閘極層18與第二閘極層20作為 ,仃一輕払雜之離子佈植製程,以於第一閘極声J 8 與第二閘極層20周圍的丰墓辦A十,n + 1 =阳往層i 8 〇〇 3, ^ W的+導體基底10表面形成一輕摻雜區 ㈣t 所示’先利用沉積、微影、非等向性 姓刻H /刀別於第-閘極層18與第二閘極層2〇之側壁上 形成一側壁24。再利用第一閘極芦丨 壁24作為罩篡,、隹> μ 層弟甲’極層20與側 雜區22之曝露區域中形成一重摻雜區26,可以用來作f 源/汲極區,而輕摻雜區22係成為LDD結構。其中高壓肋S 疋件區I之通道長度士會比高壓M〇s元件區!之通道長声 長。 又II 構及ίϊϋ提出一種具有雙閘極絕緣層之M0S元件的結 構及/、1作方法,可以應用於低壓M〇s元件的製作上, 由雙閘極絕緣層之号辞敗抑丨纟士娃 曰 制Α θ 取代結構之功能,以省略側劈 氣作以及輕摻雜離子佈植製程等步驟。 圖式簡單說明 元件區與低壓MOS元件區 絕緣層之MOS元件的剖面 第1A至1E圖顯示習知高壓M〇S 之製作方法的剖面示意圖 第2圖顯示本發明具有雙閘極519761 V. Description of the invention (2) The pattern of forming the interpolar layer is formed in the high-voltage MGS element region I-the first gate layer 18, and formed in the low-voltage deletion element region-the second gate layer is also complicated. The shortened design of the channel length will make the hot carrier effect and the 0 pole: fect) worse. Therefore, a lightly doped / flute =: ped dr, ins (LDD), structure is designed to solve this problem. Tampering with the first gate layer 18 and the second gate layer 20 instead, a lightly doped ion implantation process, so that the first gate sound J 8 and the second gate layer 20 around the tomb office A10, n + 1 = positive layer i 8 〇03, ^ W + conductor substrate 10 surface formed a lightly doped region ㈣t 'shown first using deposition, lithography, anisotropy The characteristic name H / k is formed on a sidewall of the first gate layer 18 and the second gate layer 20 to form a sidewall 24. Then, the first gate electrode 24 is used as a mask, and a heavily doped region 26 is formed in the exposed region of the μ-layer sacral electrode layer 20 and the side impurity region 22, which can be used as f source / drain. The polar region, and the lightly doped region 22 become an LDD structure. Among them, the channel length of the high-voltage rib S and the component area I will be larger than the high-voltage M0s component area! The channel is long and long. In addition, the structure and the structure of the MOS element with a double-gate insulating layer are proposed, which can be applied to the manufacture of low-voltage Mos devices. Shiwa said that A θ replaces the function of the structure, in order to omit steps such as side splitting gas and lightly doped ion implantation process. Brief description of the drawing Element section and low-voltage MOS device section Sections of MOS devices with insulating layers Figures 1A to 1E show schematic cross-sectional views of a conventional method for manufacturing a high-voltage MOS. Figure 2 shows that the present invention has dual gates.

519761 五、發明說明(3) 示意圖。 第3A至3H圖顯示本發明之且右 一 ync - /a. t ^ ,、有雙閘極絶緣層之咼壓 MOS兀件與低壓_8元件的製作方 「斤& 卜乃去的剖面不意圖。 [符號說明] 場氧化隔離區〜1 2 ; 第二氧化層〜1 6 ; 弟一'閘極層〜2 0 ; 重摻雜區〜2 6 ; 較厚之閘極絕緣層〜3 2 閘極層〜3 6 ; 高壓MOS元件區〜I ; 週邊電路區〜I 11 ; 第一氧化層〜44 ; 開口〜4 7 ; 多晶秒層〜5 0 ; 第二閘極層〜5 0 2 ; 第二光阻層〜52。 半導體基底〜10 第一氧化層〜1 4 第一閘極層〜1 8 側壁〜24 ; ❿ 半導體基底〜30、40 ; 較薄之閘極絕緣層〜3 4 源/及極區〜3 8、5 2 ; 低壓MOS元件區〜I I ; 場氧化隔離區〜42 ; 第一光阻層〜4 6 ; 第二氧化層〜48 ; 第一閘極層〜5 〇 1 ; 第三閘極層〜5 〇 3 ; 實施例 明參閱第2圖,其顯示本發明具有雙閘極絕緣層之M〇s 元件的剖面示意圖。一半導體基底30包含有一較厚之閘極 絕緣層32,一較薄之閘極絕緣層34,一閘極層%係定義形 成於車父厚之閘極絕緣層3 2與較薄之閘極絕緣層3 4之表面上 ,以及一源/汲極區38係形成於閘極層36周圍之半導體基 底30中。較薄之閘極絕緣層34之長度為L,係覆蓋住半導519761 V. Description of the invention (3) Schematic diagram. Figures 3A to 3H show the production process of the present invention and the right one ync-/ a. T ^, a high-voltage MOS element and a low-voltage _8 element with a double-gate insulation layer. Not intended. [Explanation of symbols] Field oxide isolation region ~ 1 2; Second oxide layer ~ 16; Siyi 'gate layer ~ 2 0; Heavy doped region ~ 2 6; Thicker gate insulating layer ~ 3 2 Gate layer ~ 36; High-voltage MOS device area ~ I; Peripheral circuit area ~ I 11; First oxide layer ~ 44; Opening ~ 4 7; Polycrystalline second layer ~ 50; Second gate layer ~ 50 2; second photoresist layer ~ 52. Semiconductor substrate ~ 10 first oxide layer ~ 1 4 first gate layer ~ 18 side wall ~ 24; ❿ semiconductor substrate ~ 30, 40; thinner gate insulation layer ~ 3 4 source / and electrode regions ~ 3 8, 5 2; low-voltage MOS device region ~ II; field oxide isolation region ~ 42; first photoresistive layer ~ 4 6; second oxide layer ~ 48; first gate layer ~ 5 〇1; the third gate layer to 5 〇3; the embodiment is described with reference to FIG. 2, which shows a schematic cross-sectional view of a Mos element with a double-gate insulation layer according to the present invention. A semiconductor substrate 30 includes a thicker gate Very insulating layer 32, a thinner Gate insulation layer 34, a gate layer% is defined on the surface of the driver ’s thick gate insulation layer 32 and the thinner gate insulation layer 34, and a source / drain region 38 is formed on In the semiconductor substrate 30 around the gate layer 36. The length of the thinner gate insulating layer 34 is L, which covers the semiconductor

0702-6183T1F;90P17; Cherry.ptd 第6頁 519761 五、發明說明(4) 體基底3 0之一預定區域,而較厚t n + 薄之閑極絕緣層34以覆蓋;層32係圍繞較 的部份。問極層36之底部中預定區域以外 層以,其覆蓋長度& 邊^^覆盍住較薄之閘極絕緣 較厚之閑極絕緣層32,其覆蓋長度為d ; 可以製作成具有傾斜側壁二閘極層36之輪廓 方形輪廊(如虛線所示)靡有垂直側壁之 橫向距離A丨-Γ ^ 來,源/汲極區38之間的 巨離為L + 2d,可有效增加M〇s元件之通 =近没極接面處之橫向電場,而且 ;:改 與源/汲極區38之間的距離也會增加,可以改盖曰邊及緣處 接面處之垂直電場,推而你„ & a 〇 p 。罪近及極 ^ , f I Γ進而使閘極層36之底部邊緣處的寄生 電谷減小。因此在不製作LDD結構的前提下,仍能 =熱載子效應的㈣,這將使得整個製程步 =離子佈植製程、製作侧壁所需之沉積、微影、= I程,進而縮短製作時程與製作成本。此外,具 絕緣層之MOS元件可以應用在各種低壓M〇s f J件或是-般1/〇元件的製作上,以有效改;^M〇S 場分佈情形,進而防止通道長度縮短所產生的邊熱緣載 由於本發明之具有雙閘極絕緣層之M〇s元件之最佳應 用係在於低壓MOS元件之製作上,因此以下係詳細說明二 何將上述之具有雙閘極絕緣層之M〇s元件的製作方法與一 般高壓MOS元件之製程相結合。請參閱第^至扑圖\ ^顯 示本發明之具有雙閘極絕緣層之M0S元件的製作方法/的剖0702-6183T1F; 90P17; Cherry.ptd Page 6 519761 V. Description of the invention (4) One of the predetermined areas of the body substrate 30, with a thicker tn + thin idler insulating layer 34 to cover; layer 32 surrounds the more Part. The outer layer of the predetermined region in the bottom of the interrogation layer 36 has a coverage length & a side ^^ covers a thin gate insulation and a thick idler insulation layer 32 having a coverage length of d; it can be made to have a slope The contour of the second gate layer 36 on the side wall is a square contour (as shown by the dashed line). With the lateral distance A 丨 -Γ ^ of the vertical side wall, the distance between the source / drain region 38 is L + 2d, which can effectively increase The pass of the M0s element = the transverse electric field at the near-electrode junction, and: the distance from the source / drain region 38 will also increase, and the vertical electric field at the junctions at the edges and edges can be changed And push you "& a 〇p. Sin is close to the pole ^, f I Γ further reduces the parasitic valley at the bottom edge of the gate layer 36. Therefore, without making an LDD structure, it can still = The hot carrier effect is rampant, which will make the entire process step = ion implantation process, deposition, lithography, and I process required to make the sidewall, thereby shortening the production time and production cost. In addition, MOS with an insulating layer The components can be applied to the production of various low-voltage Mosf J components or -like 1/0 components to effectively modify; ^ M〇S field distribution Situation, thereby preventing the edge heat load caused by the shortening of the channel length. Since the best application of the Mos device with double-gate insulating layer of the present invention is in the manufacture of low-voltage MOS devices, the following is a detailed description of The above-mentioned manufacturing method of the MOS device with a double-gate insulating layer is combined with the manufacturing process of a general high-voltage MOS device. Please refer to Figures ^ to ^, which show the manufacturing of the MOS device with a double-gate insulating layer according to the present invention. Method / section

519761519761

面示意圖。如第3A 場氧化隔離區4 2, 元件區I、低壓MOS 製作方法,如第3 B 般的沉積製程,於 44。然後於第一氧 4 6,其包含有一開 較薄閘極絕緣層之 之第一氧化層44蝕 使低壓MOS元件區I 露出來。 圖所不:一半導體基底40包含有複數個 用來區隔相鄰之主動區域,如高壓MOS 兀件區II以及週邊電路區ΙΠ。本發明 圖所不,首先可採用熱氧化製程或是一 半導體基底4〇表面上形成—第—氧化層 化層44之表面上定義形成一第一光阻層 口 47,疋用來定義低壓MOS元件區II之 長度L。如第3C圖所示,將開口 47下方 刻去除,再將第一光阻層46去除掉,以 1之一預定區域的半導體基底40表面曝 如第3D圖所示,於半導體基底4〇表面上形成一 :匕層48,以覆蓋住第一氧化層44以及半導體基底4二 表面。如此一來,高壓M0S元件區!與週邊電路區ιπ之 極絕緣層係由第-氧化層44與第二氧化層48所堆疊而成。 低壓MOS元件區Π則具有兩種厚度之閘極絕緣層,1 緣層係由第一氧化層44與第二氧化層48所堆疊而成。 如第3E圖所示,於半導體基底4〇表面上沉積一多晶 層50與一具有問極圖案之第二光阻層52,再利用微影蝕 製程將多晶矽層5 0定義形成閘極層之圖案,跟著將第一二 阻層52去除掉。結果如第3F圖所示,於高壓M〇s元件區j = 成一第一閘極層501,於低壓MOS元件區π形成一第二閘二 層502,而於週邊電路區in形成一第三閘極層5〇3。其中亟面 Schematic. For example, the 3A field oxidizes the isolation region 42, the device region I, and the manufacturing method of the low-voltage MOS, as in the 3B deposition process. Then at the first oxygen 46, the first oxide layer 44 including a thinner gate insulating layer is etched to expose the low-voltage MOS device region I. What is not shown in the figure: A semiconductor substrate 40 includes a plurality of active regions for separating adjacent active regions, such as a high-voltage MOS element region II and a peripheral circuit region II. As shown in the figure of the present invention, first, a thermal oxidation process or a semiconductor substrate 40 may be formed on the surface—a first photoresist layer 44 is defined on the surface to form a first photoresist layer opening 47, which is used to define a low-voltage MOS. The length L of the element region II. As shown in FIG. 3C, the bottom of the opening 47 is etched away, and then the first photoresist layer 46 is removed, and the surface of the semiconductor substrate 40 in a predetermined area is exposed as shown in FIG. 3D on the surface of the semiconductor substrate 40. A first layer 48 is formed on the first oxide layer 44 and the second surface of the semiconductor substrate 4. In this way, the high-voltage M0S element area! The insulating layer with the peripheral circuit region is formed by stacking the first oxide layer 44 and the second oxide layer 48. The low-voltage MOS device region Π has a gate insulating layer of two thicknesses, and an edge layer is formed by stacking a first oxide layer 44 and a second oxide layer 48. As shown in FIG. 3E, a polycrystalline layer 50 and a second photoresist layer 52 having an interlayer pattern are deposited on the surface of the semiconductor substrate 40, and then the polycrystalline silicon layer 50 is defined by a lithography process to form a gate layer. Then, the first and second resist layers 52 are removed. As a result, as shown in FIG. 3F, a first gate layer 501 is formed in the high-voltage MOS device region j =, a second gate two-layer 502 is formed in the low-voltage MOS device region π, and a third is formed in the peripheral circuit region in. Gate layer 503. Which urgently

0702-6183TWF ; 90P17 ; Cherry.ptd 第8頁 五、發明說明(6) 弟 _-閑極 5 Π 9 rX- 層,底部邊緣處传部中央處係覆蓋住較薄之閘極絕緣 乂運緣處係延伸覆蓋住 兩壓MOS元件區!食调、套雷玫"τι 電性考量盥梦程+ 4、;:週邊電路區1 U之後續製程可依照 '及區之製作周整,以進行側壁、LDD結構與源/ 與3H圖所示:第」==件區Π之製作結果則如第3G 側壁之方形輪Ϊ:輪^ 側壁之梯形I : f::層5〇2之輪廓製作成具有傾斜 底部邊ίίί;伸覆 由於第二閘極㈣^ 壓_元件區π之通道長度,以;;=埶:J效增加低 靖。這將使得整個製程步驟省略掉輕換雜熱载子效應的問 二作侧壁所需之沉積、微影、敍刻等J,離:佈植製程 作時程與製作成本。 寻I耘,進而縮短製 雖然本發明已以一較佳實施例揭 以限定本發明,任何熟習此技蓺者,σ ,然其並非用 神和範圍内,當可作些許之更動盥潤 $離本發明之精 護範圍當視後附之申請專利範圍所界::本發明之保0702-6183TWF; 90P17; Cherry.ptd Page 8 V. Description of the invention (6) Brother _- idle pole 5 Π 9 rX- layer, the center of the bottom edge of the transmission part is covered with a thin gate insulation edge The system extends to cover the two-voltage MOS device area! Food taste, set of Lei Mei " τι electrical consideration of toilet dream course + 4,;: the subsequent process of the peripheral circuit area 1 U can be based on the production cycle of the 'and area, to carry out the side wall, LDD structure and source / and 3H map Shown: the production result of the "" == piece area Π is like the square wheel of the 3G side wall: wheel ^ the trapezoid of the side wall I: f :: The contour of the layer 5〇2 is made with a sloping bottom edge; stretched because The second gate electrode ㈣ ^ _ the channel length of the element region π; This will make the whole process step obviate the problem of light-changing heterothermal carrier effects. Second, the deposition, lithography, engraving, etc. required for the side wall. Seek work, and then shorten the system. Although the present invention has been described with a preferred embodiment to limit the present invention, anyone who is familiar with this technique, σ, but it is not within the scope of God, and it can be changed slightly. Departure from the scope of the present invention: The scope of the attached patent application:

Claims (1)

519761519761 六、申請專利範圍 1 · 一種具有雙閘極絕緣層之Μ 0 S元件,包括有: 一半導體基底; 一第一閘極絕緣層係形成於該半導體基底之一預定區 域表面上; 、一第二閘極絕緣層係形成於該半導體基底之預定區域 η:部份’u圍繞該第一閘極絕緣層,其中該第二閘極 、、、、、、二之厚度係大於該第一閘極絕緣層之厚度;以及 面,i π ’ ΐ底部中央處係覆蓋該第-閘極絕緣層表 2rί,ί延伸覆蓋該第二閘極絕緣層表面。 M〇S元件,其中該閘極;2閘極絕緣層之 廓。 糸裊作成具有垂直側壁之方形輪 3 ·如申請專利範圍 MOS元件,其中該閘極層制^ /、有雙閘極絕緣層之 廓。 ㈢μ製作成具有傾斜側壁之梯形輪 4 ·如申請專利範圍第 m〇s元件,另包含有—弟1員所述之具有雙閘極絕緣層之 之該半導體基底表面上、。/虽區,係形成於該閘極層周圍 5 ·如申請專利範圍第 MOS元件,其中該第一 、述之具有雙閘極絕緣層之 由氧化矽所構成。 °、、、緣層與該第二閘極絕緣層係 〇·如甲請 m〇s元件’其中該閘極m 1具有智 7. -種具有雙心:缘由广夕所構4 、尤緣層之MOS元件白 絕緣層之 方法,包6. Scope of patent application 1. An M 0 S element with a double-gate insulating layer includes: a semiconductor substrate; a first gate insulating layer is formed on a surface of a predetermined region of the semiconductor substrate; A two-gate insulating layer is formed in a predetermined region η of the semiconductor substrate: a portion 'u surrounds the first gate insulating layer, wherein the thickness of the second gate, ,,,,, and 2 is larger than that of the first gate. The thickness of the electrode insulating layer; and the surface, i π ′ at the center of the bottom is covered with the first gate insulating layer 2r, extending to cover the surface of the second gate insulating layer. MoS element, where the gate; 2 the outline of the gate insulation layer.方形 Make a square wheel with vertical side walls. 3 · If the scope of the patent application is for a MOS device, where the gate layer is made of a double-gate insulation layer. ㈢μ is made into a trapezoidal wheel with an inclined side wall. 4. As the m0s element in the scope of the patent application, it also includes the surface of the semiconductor substrate with a double-gate insulation layer described by 1 member. / Although the region is formed around the gate layer 5 · As for the MOS device in the scope of the patent application, the first and the second one described above has a double gate insulating layer composed of silicon oxide. ° ,,, and the marginal layer and the second gate insulation layer are 〇 · such as a request m0s element 'where the gate m 1 has wisdom 7.-a kind of dual-heart: Caused by Guangxi 4, especially margin Method for white insulating layer of MOS element, including 519761 六、申請專利範圍 括下列步驟: (a) 提供一半導體基底,其表面上定義有一預定區 域; (b) 於該半導體基底之預定區域以外的表面上形成一 第一絕緣層; (c) 於該第一絕緣層與該半導體基底之曝露表面上形 成一第二絕緣層,其中位於該預定區域之該第二絕緣層係 作為一較薄之閘極絕緣層,位於該預定區域以外之該第一 絕緣層與該第二絕緣層係作為一較厚之閘極絕緣層;以及 (d )於該第二絕緣層表面上定義形成一閘極層,其中 該閘極層之底部中央處係覆蓋該較薄之閘極絕緣層表面, 該閘極層之底部邊緣處係延伸覆蓋該較厚之閘極絕緣層表 面。 8.如申請專利範圍第7項所述之製作方法,其中該閘 極層係製作成具有垂直側壁之方形輪廓。 9 ·如申請專利範圍第7項所述之製作方法,其中該閘 極層係製作成具有傾斜側壁之梯形輪廓。 1 0.如申請專利範圍第7項所述之製作方法,其更包含 有一步驟(e):進行一離子佈植製程,以於該閘極層周圍 之該半導體基底表面上形成一源/汲極區。 1 1.如申請專利範圍第7項所述之製作方法,其中該步 驟(b )包含有下列步驟: (b 1 )於該半導體基底表面上形成該第一絕緣層; (b2)於該第一絕緣層表面上形成一第一光阻層,其包519761 6. The scope of patent application includes the following steps: (a) providing a semiconductor substrate with a predetermined area defined on the surface; (b) forming a first insulating layer on a surface other than the predetermined area of the semiconductor substrate; (c) A second insulating layer is formed on the exposed surfaces of the first insulating layer and the semiconductor substrate, wherein the second insulating layer located in the predetermined region is used as a thin gate insulating layer, and the second insulating layer is located outside the predetermined region. The first insulating layer and the second insulating layer serve as a thicker gate insulating layer; and (d) a gate layer is defined on the surface of the second insulating layer, wherein the bottom center of the gate layer is Cover the surface of the thinner gate insulating layer, and the bottom edge of the gate layer extends to cover the surface of the thicker gate insulating layer. 8. The manufacturing method according to item 7 of the scope of patent application, wherein the gate layer is made into a square profile with vertical side walls. 9. The manufacturing method as described in item 7 of the scope of patent application, wherein the gate layer is made into a trapezoidal profile with inclined sidewalls. 10. The manufacturing method described in item 7 of the scope of patent application, further comprising a step (e): performing an ion implantation process to form a source / drain on the surface of the semiconductor substrate around the gate layer. Polar region. 1 1. The manufacturing method described in item 7 of the scope of patent application, wherein step (b) includes the following steps: (b 1) forming the first insulating layer on the surface of the semiconductor substrate; (b2) forming the first insulating layer on the surface of the semiconductor substrate; A first photoresist layer is formed on the surface of an insulating layer. 0702-6183TWF ; 90P17 ; Cherry.ptd 第11頁 519761 六、申請專利範圍 含有一開口係使位於該預定區域之該第一絕緣層曝露出 來;以及 (b 3 )將該開口内之該第一絕緣層去除。 1 2.如申請專利範圍第7項所述之製作方法,其中該第 一絕緣層與該第二絕緣層係由氧化石夕所構成。 1 3.如申請專利範圍第7項所述之製作方法,其中該閘 極層係由多晶矽所構成。 III « »1 ϊί 1 0702-6183TWF ; 90Ρ17 ; Cherry.ptd 第12頁0702-6183TWF; 90P17; Cherry.ptd Page 11 519761 6. The scope of the patent application contains an opening to expose the first insulation layer located in the predetermined area; and (b 3) the first insulation in the opening Layer removed. 1 2. The manufacturing method as described in item 7 of the scope of patent application, wherein the first insulating layer and the second insulating layer are made of stone oxide. 1 3. The manufacturing method according to item 7 of the scope of patent application, wherein the gate layer is made of polycrystalline silicon. III «» 1 ϊί 1 0702-6183TWF; 90P17; Cherry.ptd Page 12
TW90128594A 2001-11-19 2001-11-19 MOS device having dual-gate insulation layer and its manufacturing method TW519761B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW90128594A TW519761B (en) 2001-11-19 2001-11-19 MOS device having dual-gate insulation layer and its manufacturing method
US10/382,842 US20030146478A1 (en) 2001-11-19 2003-03-07 MOS device with dual gate insulators and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90128594A TW519761B (en) 2001-11-19 2001-11-19 MOS device having dual-gate insulation layer and its manufacturing method

Publications (1)

Publication Number Publication Date
TW519761B true TW519761B (en) 2003-02-01

Family

ID=27801589

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90128594A TW519761B (en) 2001-11-19 2001-11-19 MOS device having dual-gate insulation layer and its manufacturing method

Country Status (1)

Country Link
TW (1) TW519761B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012075661A1 (en) * 2010-12-06 2012-06-14 中国科学院微电子研究所 Device with channel stress adjustable and manufacturing method thereof
US8384162B2 (en) 2010-12-06 2013-02-26 Institute of Microelectronics, Chinese Academy of Sciences Device having adjustable channel stress and method thereof
US8513770B2 (en) 2008-02-20 2013-08-20 Magnachip Semiconductor, Ltd. Anti-fuse and method for forming the same, unit cell of non volatile memory device with the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513770B2 (en) 2008-02-20 2013-08-20 Magnachip Semiconductor, Ltd. Anti-fuse and method for forming the same, unit cell of non volatile memory device with the same
TWI478286B (en) * 2008-02-20 2015-03-21 Magnachip Semiconductor Ltd Anti-fuse and method for forming the same, unit cell of non volatile memory device with the same
WO2012075661A1 (en) * 2010-12-06 2012-06-14 中国科学院微电子研究所 Device with channel stress adjustable and manufacturing method thereof
US8384162B2 (en) 2010-12-06 2013-02-26 Institute of Microelectronics, Chinese Academy of Sciences Device having adjustable channel stress and method thereof

Similar Documents

Publication Publication Date Title
US7652331B2 (en) Semiconductor device and method for fabricating the same
US7541656B2 (en) Semiconductor devices with enlarged recessed gate electrodes
US7316945B2 (en) Method of fabricating a fin field effect transistor in a semiconductor device
US20050167754A1 (en) Semiconductor device and method of manufacturing the same
JP2003318405A5 (en)
JP2006504267A (en) Double and triple gate MOSFET devices and methods of manufacturing these MOSFET devices
TW200924069A (en) Method of forming FINFET device
US7307311B2 (en) MOSFET device
JP2002270850A (en) Dual-gate field effect transistor
US6551883B1 (en) MOS device with dual gate insulators and method of forming the same
JP5012023B2 (en) Field effect transistor and manufacturing method thereof
US11075296B2 (en) Trench gate MOSFET and method of manufacturing the same
TW519761B (en) MOS device having dual-gate insulation layer and its manufacturing method
JP5596245B1 (en) Semiconductor device manufacturing method and semiconductor device
CN205282459U (en) Integrated circuit
US7709395B2 (en) Semiconductor device fabrication method
US7319060B2 (en) Semiconductor device and method of manufacturing the semiconductor device
US8552478B2 (en) Corner transistor and method of fabricating the same
JP5646116B1 (en) Semiconductor device manufacturing method and semiconductor device
JP6405026B2 (en) Semiconductor device manufacturing method and semiconductor device
JP2006237453A (en) Semiconductor device and manufacturing method thereof
JP6375316B2 (en) Semiconductor device manufacturing method and semiconductor device
JP2007287791A (en) Semiconductor device and manufacturing method thereof
JP3148227B2 (en) Method for manufacturing semiconductor device
CN114005755A (en) Fin type field effect transistor and manufacturing method thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees