JP5012023B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a fin-type field effect transistor in which electric field concentration from a gate electrode in an upper part of a semiconductor layer is reduced and leakage current is suppressed.

Conventionally, as disclosed in JP-A-64-8670 and JP-A-2002-118255, a double gate type fin field effect transistor (hereinafter referred to as a double gate FinFET) has been developed. It was. An ideal form of the double gate FinFET will be described with reference to a plan view of FIG. 21 and a cross-sectional view of FIG. 22A is a cross-sectional view taken along line AA ′ in FIG. 21, FIG. 22B is a cross-sectional view taken along line BB ′ in FIG. 21, 1 is a semiconductor substrate, 2 is a buried insulating layer, 3 is a semiconductor layer, and 4 is gate insulating. A film 5 is a gate electrode, 6 is a source / drain region, and 22 is a cap insulating film made of SiO ₂ . Wfin is the fin width, and Hfin is the fin height. FIG. 23 shows a case where the cap insulating film has a two-layer structure of a first cap insulating film 8 made of SiO ₂ and a second cap insulating film 9 made of Si ₃ N ₄ . FIG. 23A is an AA ′ cross section in FIG. 21, and FIG. 23B is a BB ′ cross section in FIG.

  By applying an appropriate voltage at the gate electrode, a channel region is formed in a portion facing the gate electrode 5 on the side surface of the semiconductor layer 3, and a current is conducted in the transistor.

  When the cap insulating film (8, 9, 22) is provided on the semiconductor layer 3, the capacitance between the gate electrode and the upper portion of the semiconductor is reduced, so that the electric field concentration on the upper corner 23 of the semiconductor layer is reduced. When the electric field concentration on the upper corner 23 of the semiconductor layer is relaxed, the leakage current due to GIDL (gate induced drain leakage) and the leakage current due to the parasitic transistor having a low threshold at the upper corner of the semiconductor layer are suppressed. Performance is improved.

  Problems of the conventional example will be described with reference to FIGS. 24 corresponds to the position of the A-A ′ cross section of FIG. 22A, and each drawing of FIG. 25 corresponds to the position of the A-A ′ cross section of FIG.

In order to form the transistor of FIG. 22, the cap insulating film 22 and the semiconductor layer 3 made of SiO ₂ are processed by etching into the form of FIG. After this step, prior to the step of forming the gate insulating film on the side surface of the semiconductor layer (semiconductor region), the side surface of the semiconductor layer is usually once oxidized (sacrificial oxidation) as a pretreatment of the gate insulating film forming step, The formed oxide film (sacrificial oxide film) is removed by wet etching using hydrofluoric acid or the like. The purpose of this is to form a high-quality gate insulating film by removing the contaminated layer and the damaged layer from the interface of the semiconductor layer forming the gate insulating film. However, since the cap insulating film is also etched by this wet etching, the cap insulating film 22 recedes as shown in FIG. 24B, and the upper corner of the semiconductor layer is exposed, as shown in FIG. As described above, the cap insulating film 22 disappears completely, and the upper corner of the semiconductor layer is exposed. If the gate insulating film and the gate electrode are formed in a state where the upper corner of the semiconductor layer is not covered with the cap insulating film and exposed, electric field concentration occurs in the upper corner of the semiconductor layer, and leakage current due to GIDL and parasitic transistors occurs.

In the case of the transistor of FIG. 23 as well, when the sacrificial oxide film is removed by wet etching using hydrofluoric acid or the like as a pretreatment in the gate insulating film formation step after being processed into the form of FIG. As shown in FIG. 25B, the first cap insulating film 8 made of SiO ₂ recedes to expose the upper corner of the semiconductor layer, or the first cap insulating film 8 disappears completely as shown in FIG. Then, if the cap insulating film 9 is lifted off and falls off and the upper corner of the semiconductor layer is exposed, the same problem occurs.

  Therefore, a structure and a manufacturing method are desired in which the upper corner of the semiconductor layer is covered with the cap insulating film even after the pretreatment of the gate insulating film forming step.

  According to the present invention, the following field effect transistor and a method for manufacturing the same can be provided.

(1) A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on the upper surface of the semiconductor region; and the upper portion of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
Of the cap insulating film covered with the gate electrode, at least a part of the side surface in the extending direction of the side surface of the semiconductor region in contact with the semiconductor region is made of SiO ₂ by wet etching using HF solution. A field effect transistor characterized by having a side etching resistant region having a low etching rate.

  (2) The side surface etching resistant regions are provided opposite to each other on the two opposite side surfaces covered with the gate electrode of the cap insulating film, and are sandwiched between the opposing side surface etching resistant regions in the cap insulating film. 2. The field effect transistor according to 1 above, wherein the field effect transistor has a central region made of a material different from the side etching resistant region at a position.

  (3) The field effect transistor according to (2) above, wherein the central region is made of a material having a dielectric constant lower than that of the side surface etching resistant region.

(4) The field effect transistor according to 2 or 3 above, wherein the central region is made of SiO ₂ .

  (5) The side surface etching-resistant region is provided on the side surface of the cap insulating film covered with the gate electrode over the entire length in the direction connecting the opposing source / drain regions. Any one of the field effect transistors.

(6) The field effect transistor according to any one of (1) to (5) above, wherein the side face etching resistant region is made of Si ₃ N ₄ .

  (7) The field effect transistor according to any one of (1) to (5), wherein the side etching resistant region is made of a material containing silicon, nitrogen, and oxygen.

(8) The cap insulating film according to any one of 1 to 7 above, wherein the cap insulating film has at least a top surface including a top surface etching-resistant region whose etching rate is lower than that of SiO _{2 with} respect to wet etching using an HF solution. Any one of the field effect transistors.

  (9) The field effect transistor according to (9), wherein the upper surface etching-resistant region constitutes at least a part of an upper surface of the cap insulating film covered with the gate electrode.

  (10) The electric field according to (8) above, wherein the upper surface etching-resistant region is provided over the entire length in the direction connecting the opposing source / drain regions on the upper surface of the cap insulating film covered with the gate electrode. Effect transistor.

(11) The field effect transistor according to any one of (8) to (10), wherein the upper surface etching-resistant region is made of Si ₃ N ₄ .

  (12) The field effect transistor according to any one of 8 to 10, wherein the upper surface etching-resistant region is made of a material containing silicon, nitrogen, and oxygen.

  (13) The field effect transistor according to any one of (1) to (12), wherein the cap insulating film has a substantially rectangular parallelepiped shape.

  (14) The field effect transistor as described in (7) or (12) above, wherein the nitrogen content in the material containing silicon, nitrogen and oxygen is 5 atomic% or more.

(15) The field effect transistor according to (1), wherein the cap insulating film is made of a material having an etching rate lower than that of SiO _{2 with} respect to wet etching using an HF solution.

(16) The field effect transistor as described in 15 above, wherein the entire cap insulating film is made of Si ₃ N ₄ .

(17) A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on the upper surface of the semiconductor region; and the upper portion of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
Si ₃ N ₄ regions provided on the upper surface and both side surfaces of the SiO ₂ region;
A field effect transistor comprising:

(18) A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on the upper surface of the semiconductor region; and the upper portion of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
SiON regions containing silicon, oxygen and 5 atomic% or more of nitrogen provided on both sides of the SiO ₂ region;
An Si ₃ N ₄ region provided on the upper surface of the SiO ₂ region and the SiON region;
A field effect transistor comprising:

(19) A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on the upper surface of the semiconductor region; and the upper portion of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
SiON region containing silicon, oxygen and 5 atomic% or more nitrogen provided on the upper surface and both side surfaces of the SiO ₂ region;
A field effect transistor comprising:

(20) A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on the upper surface of the semiconductor region; and the upper portion of the cap insulating film so as to straddle the semiconductor region and the cap insulating film A gate electrode extending laterally of the semiconductor region, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region;
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
Provided on both sides of the SiO ₂ region, and the _Si 3 _{N 4} regions protruding upwardly from the sides of the SiO ₂ region,
A field effect transistor comprising:

  (21) The field effect transistor according to any one of (1) to (20), wherein a plurality of semiconductor regions are arranged so that directions of channel currents flowing in the semiconductor regions are parallel to each other Field effect transistor.

(22) A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
An etching step of forming a patterned first insulating film on the semiconductor layer;
An insulating film sidewall made of a second insulating film in contact with a side surface of the first insulating film is patterned on the semiconductor layer exposed by an etching process for forming a patterned first insulating film. Providing a position near the first insulating film;
Etching the semiconductor layer using the first insulating film and the insulating film side wall made of the second insulating film as a mask to form a semiconductor region protruding upward with respect to the substrate plane;
A method for producing a field-effect transistor, comprising:

(23) forming a sacrificial oxide film on a side surface of the semiconductor region protruding upward with respect to the substrate plane;
And further removing the sacrificial oxide film by wet etching,
23. The field effect transistor according to 23, wherein an insulating film side wall made of the second insulating film is made of a material having a lower etching rate than a sacrificial oxide film formed on a side surface of the semiconductor region with respect to wet etching. Manufacturing method.

(24) A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
(A) Sacrificial oxidation formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces Providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;
(B) using the cap insulating film as a mask, and forming a semiconductor region projecting upward from the base body below the cap insulating film;
A method for producing a field-effect transistor, comprising:

(25) After the step (b),
(C) forming a sacrificial oxide film on a side surface of the semiconductor region;
(D) The method for producing a field effect transistor as described in 24 above, further comprising a step of removing the sacrificial oxide film by wet etching.

(26) forming a gate insulating film on a side surface of the semiconductor region from which the sacrificial oxide film is removed;
Depositing a gate electrode material and patterning the gate electrode material deposition film to form a gate electrode;
Forming a source / drain region by introducing impurities on both sides of the semiconductor region sandwiching the gate electrode;
The method for producing a field effect transistor according to 23 or 25, further comprising:

(27) The step (a) of providing a cap insulating film includes:
Providing a central region on the semiconductor layer;
Providing a side etching resistant region on the side surface of the central region by depositing a side etching resistant region material on the semiconductor layer and the central region and then performing etch back;
The method for producing a field effect transistor according to any one of the above 24 to 26, which comprises:

(28) The step of (a) providing a cap insulating film includes:
After depositing a central region material on the semiconductor layer and depositing a top surface etching resistant region material on the central region material, patterning the central region material and the top surface etching resistant region material and subjecting the central region to wet etching Providing a top etching resistant region having a lower etching rate than the sacrificial oxide film formed on the side surface of the semiconductor region;
Providing a side surface etching resistant region on the side surface of the central region and the top surface etching resistant region;
The method for producing a field effect transistor according to any one of the above 24 to 26, which comprises:

(29) The step of providing the side face etching-resistant region includes:
28. The method of manufacturing a field effect transistor according to 28, wherein the side surface etching resistant region material is deposited on the entire surface, followed by etching back.

  (30) The deposition of the side surface etching resistant region material and the upper surface etching resistant region material is performed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. A method for producing a field effect transistor according to any one of -29.

(31) The step of (a) providing a cap insulating film includes:
Providing a substantially rectangular parallelepiped cap insulating film material on the semiconductor layer;
Nitriding the side and top surfaces of the cap insulating film material and the semiconductor layer under the condition that the nitriding rate of the cap insulating film material is higher than the nitriding rate of the semiconductor layer;
Performing etch back, and forming a side surface subjected to nitriding of the cap insulating film material as a side surface etching resistant region, and a top surface subjected to nitriding processing of the cap insulating film material as a top surface etching resistant region;
The method for producing a field effect transistor according to any one of the above 24 to 26, which comprises:

(32) The step of (a) providing a cap insulating film includes:
A substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and a step of providing an upper surface etching-resistant region on the cap insulating film material;
Nitriding the side surface of the cap insulating film material and the semiconductor layer; and
Performing etch back, and forming a side surface on which the nitriding treatment of the cap insulating film material is performed as a side etching resistant region;
The method for producing a field effect transistor according to any one of the above 24 to 26, which comprises:

  (33) The method for producing a field effect transistor as described in 31 or 32 above, wherein the nitriding treatment is radical nitriding, thermal nitriding, or nitrogen ion implantation.

  (34) The field effect according to any one of (26) to (33), further comprising a step of removing a cap insulating film provided on a semiconductor region not covered with the gate electrode, of the cap insulating film. Type transistor manufacturing method.

  (35) The step (a) of providing the cap insulating film deposits a cap insulating film material made of a material having a lower etching rate than a sacrificial oxide film provided on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer. 27. The method of manufacturing a field effect transistor according to any one of 24 to 26, which is a step of patterning after the step.

(36) The method for manufacturing a field effect transistor according to any one of (24) to (35), wherein the wet etching is wet etching using an HF solution, and the sacrificial oxide film is made of SiO ₂ .

  In the transistor having the structure of the present invention, a region in which the upper corner of the semiconductor layer is covered with the cap sidewall insulating film is provided in at least a portion of the upper portion of the semiconductor layer. Since the gate electrode does not cover the semiconductor layer upper corner so as to surround the upper corner of the semiconductor layer, the parasitic transistor is suppressed and the leakage current is suppressed.

  In addition, a region where the upper corner of the semiconductor layer is covered with the cap sidewall insulating film is provided in at least a part of the upper portion of the semiconductor layer near the edge of the source / drain region. Therefore, the electric field concentration is suppressed and the leakage current due to GIDL is suppressed.

  In the present invention, since the corner portion on the upper surface of the semiconductor layer is covered with the first cap insulating film and the cap side wall insulating film, the sacrificial oxide film formed on the side surface of the semiconductor region prior to the formation of the gate insulating film is removed. When performing the pretreatment for performing the step, the first cap insulating film is not etched by the pretreatment for forming the gate insulating film, and the corner portion on the upper surface of the semiconductor layer is not exposed. For this reason, the electric field concentration from the gate electrode in the upper part of the semiconductor layer (semiconductor region) is alleviated, the leakage current due to GIDL is reduced, and the leakage current due to the parasitic transistor having a low threshold voltage formed at the upper corner of the semiconductor layer is suppressed. Is done.

Many insulating materials (typically materials containing nitrogen such as Si ₃ N ₄ , SiON, etc.) that are resistant to the sacrificial oxide etching process have a higher dielectric constant than SiO _2. By forming at least a part of the film that does not require resistance to the sacrificial oxide etching process by using a material having a lower dielectric constant than a material resistant to the sacrificial oxide etching process, Electric field concentration from the gate electrode in the upper part of the semiconductor layer can be relaxed.

Typically, in the present invention, when the first cap insulating film (center region) is formed of a material having a dielectric constant lower than that of the second cap insulating film (upper etching resistant region), the entire cap insulating film (first cap insulating film) is formed. Compared with the case where the film, the second cap insulating film, and the cap side wall insulating film (side etching resistant region) are made of Si ₃ N ₄ resistant to hydrofluoric acid, the capacitance between the upper part of the semiconductor layer and the gate electrode is larger. The electric field concentration from the gate electrode in the upper part of the semiconductor layer can be reduced. As a result, leakage current called GIDL (Gate Induced Drain Leakage) is reduced, and leakage current due to a parasitic transistor having a low threshold voltage formed at the upper corner of the semiconductor layer is also suppressed.

In the present invention, by performing nitriding treatment on the side surface of the cap insulating film material formed in advance, it is not necessary to deposit the cap side wall insulating film on the outer side surface of the cap insulating film formed in advance, and it is formed in advance. Since the cap sidewall insulating film is formed inside the side surface of the cap insulating film material, the width of the entire cap insulating film is suppressed, and as a result, the Fin formed by etching the semiconductor layer using the cap insulating film as a mask. The width of the layer (fin width Wfin) can be reduced. By reducing the fin width Wfin of the FinFET, the short channel effect is suppressed and the performance can be improved. Also, the nitridation process is superior in controllability of the thickness of a nitride film (or a region where a large amount of nitrogen is introduced into the SiO ₂ film) formed compared to the CVD process. Can be produced.

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(First embodiment)
On an SOI substrate (FIG. 1A) on which a buried insulating layer 2 and a semiconductor layer 3 are formed on a semiconductor substrate 1, a first cap insulating film material (intermediate region material) 8, a second cap insulating film material (upper surface) Etch-resistant region material) 9 is deposited (FIG. 1B).

The semiconductor substrate 1 is usually a silicon substrate. The buried insulating layer 2 is typically SiO ₂ and its film thickness is typically 50 nm to 400 nm. The semiconductor layer 3 is typically silicon and typically has a thickness of 20 nm to 200 nm. The material of the first cap insulating film 8 is typically SiO ₂ , and the material of the second cap insulating film 9 is typically Si _3.
N ₄ and these are deposited, for example, by CVD. The thicknesses of the first cap insulating film 8 and the second cap insulating film 9 are typically 10 nm to 50 nm, respectively.

  2C are top views of the fin-type field effect transistor, FIG. 2A is a cross-sectional view of the fin-type field effect transistor in the AA ′ direction, and FIG. 2B is BB ′. A sectional view in the direction is shown.

  The first cap insulating film material 8 and the second cap insulating film material 9 are processed so as to cover the region where the element region is formed by forming a resist pattern by normal photolithography and etching using the resist as a mask (see FIG. 2). The first cap insulating film material 8 may be etched using a resist as a mask, or after removing the resist, the second cap insulating film 9 may be etched using the mask.

A cap cover insulating film material (side face etching resistant region material) 10 is deposited on the entire surface (FIG. 3). The cap cover insulating film material 10 is made of a material that is resistant to the pretreatment for forming the gate insulating film (having an etching rate lower than that of SiO _{2 with} respect to wet etching with a hydrofluoric acid solution). The cap cover insulating film 10 is typically a Si ₃ N ₄ film deposited by a film forming technique such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The thickness of the cap cover insulating film 10 is typically 2 nm to 20 nm, and is usually in the range of 3 nm to 10 nm.

  The cap cover insulating film 10 is etched back by an etching process such as RIE, and the cap cover insulating film 10 is formed on the side walls of the first cap insulating film (center region) 8 and the second cap insulating film (upper surface etching resistant region) 9. Then, a cap side wall insulating film (side etching resistant region) 19 is formed (FIG. 4).

  Using the second cap insulating film 9 and the cap sidewall insulating film 19 as a mask, the semiconductor layer 3 is patterned by an etching process such as RIE (FIG. 5).

Similar to a normal MOSFET formation process, a gate insulating film 4 is formed, a gate electrode material is deposited and patterned to form a gate electrode 5, and a high-concentration impurity (As in the case of an n-channel transistor) is formed using the gate electrode as a mask. N-type dopants such as Sb, p-type dopants such as B and In in the case of p-channel transistors, which are usually introduced so that the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more) by ion implantation or the like, Source / drain regions 6 are formed to complete the transistor (FIG. 6).

  At this time, prior to the formation of the gate insulating film, the side surface of the silicon layer (semiconductor region) exposed by etching is once thermally oxidized to form a sacrificial oxide film, and the sacrificial oxide film is removed with dilute hydrofluoric acid. Even so, the side and top surfaces of the first cap insulating film 8 are covered with the hydrofluoric acid resistant cap side wall insulating film 19 and the second cap insulating film 9, respectively. One cap insulating film is never etched.

  Note that ion implantation (referred to as channel ion implantation) in the vicinity of a semiconductor region where a channel is formed may be performed when the sacrificial oxide film is provided. Further, channel ion implantation may be performed in other process steps.

Like the ordinary MOSFET creation process, the gate sidewalls 14, cobalt silicide, an interlayer insulating film 16 made of silicide region 15, SiO ₂ made of nickel silicide, a contact 17 made of a metal, the wiring 18 are formed successively. FIG. 7 is a sectional view and FIG. 8 is a plan view.

  The upper surface and the side surface of the first cap insulating film 8 are covered with a second cap insulating film 9 and a cap side wall insulating film 19 which are resistant to pretreatment for gate insulating film formation (removal of sacrificial oxide film by hydrofluoric acid), respectively. Therefore, the first cap insulating film 8 is not etched by the pretreatment for forming the gate insulating film.

Further, when the first cap insulating film 8 is formed of a material having a dielectric constant lower than that of the second cap insulating film 9 and lower than that of the cap side wall insulating film 19, for example, the entire cap insulating film (first cap insulating film) 8, the capacity of the upper part of the semiconductor layer and the gate electrode is reduced as compared with the case where the second cap insulating film 9 and the entire cap side wall insulating film 19 are made of Si ₃ N ₄ resistant to hydrofluoric acid. When this capacity is reduced, the electric field concentration from the gate electrode on the semiconductor layer is reduced. When the electric field concentration from the gate electrode in the upper part of the semiconductor layer is alleviated, leakage current called GIDL (Gate Induced Drain Leakage) is reduced, and a parasitic threshold voltage formed at the upper corner of the semiconductor layer is low. Leakage current is also suppressed.

(Second embodiment)
In the first embodiment, the cap sidewall insulating film (side etching resistant region) 19 is not formed by a film forming technique such as CVD, but the side surface of the first cap insulating film 8 is radical-nitrided, thermal-nitrided, nitrogen ion-implanted, etc. A method of forming the cap sidewall insulating film 19 having resistance to a pretreatment process such as sacrificial oxide film removal (having an etching rate lower than that of SiO _{2 with} respect to wet etching using an HF solution) by the modification technique of FIG. (In the first embodiment, the side surface etching-resistant region is provided on the side surface of the first cap insulating film 8, but in the second embodiment, the side surface of the first cap insulating film contains nitrogen by nitriding treatment. For this reason, in the second embodiment, the portion of the first cap insulating film that has not been subjected to nitriding treatment (side-etching resistance region). The part other than the ching area is the central area.)

  Similar to the first embodiment, on the SOI substrate in which the buried insulating layer 2 and the semiconductor layer 3 are formed on the semiconductor substrate 1, the first cap insulating film material 8 and the second cap insulating film material (upper surface etching resistant region material). 9 is deposited (same as in FIG. 1). Thereafter, as in the first embodiment, the element region is formed of the first cap insulating film material 8 and the second cap insulating film material 9 by forming a resist pattern by normal photolithography and etching using the resist as a mask. To cover the area to be covered (same as in FIG. 2).

  A side surface of the first cap insulating film 8 is nitrided using nitrogen radicals to form a modified layer (side surface etching resistant region material) 20. At this time, the surface of the semiconductor layer 3 is also nitrided (FIG. 9). The nitriding may be performed by a method other than radical nitriding, for example, thermal nitriding. The thickness of the modified layer is typically 1 nm to 5 nm.

The entire surface of the Si ₃ N ₄ film is etched back by RIE to remove the modified layer 20 on the semiconductor layer, and the side wall of the first cap insulating film 8 has a cap side wall insulating film (side resistance) formed of the modified layer 20. Etching region) 19 is formed (FIG. 10).

  The subsequent steps are the same as in the first embodiment. Using the second cap insulating film 9 and the cap sidewall insulating film 19 as a mask, the semiconductor layer 3 is patterned by an etching process such as RIE (FIG. 11).

Similar to a normal MOSFET formation process, a gate insulating film 4 is formed, a gate electrode material is deposited and patterned to form a gate electrode 5, and a high concentration impurity (in the case of an n-channel transistor, n in the case of an n-channel transistor) is formed. A p-type dopant in the case of a p-channel transistor (usually introduced so that the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more) is introduced by ion implantation or the like to form the source / drain region 6, A transistor is completed.

  At this time, prior to the formation of the gate insulating film, the side surface of the silicon layer exposed by etching is once thermally oxidized to form a sacrificial oxide film, and then the step of removing the sacrificial oxide film with dilute hydrofluoric acid may be performed. The side and top surfaces of the first cap insulating film 8 (central region) are covered with the hydrofluoric acid resistant cap side wall insulating film 19 and the second cap insulating film, respectively, so that the sacrificial oxide film removal step is performed. The first cap insulating film (center region) is not etched (FIG. 12).

Like the ordinary MOSFET creation process, the gate sidewalls 14, cobalt silicide, an interlayer insulating film 16 made of silicide region 15, SiO ₂ made of nickel silicide, a contact 17 made of a metal, to form the wiring 18. A cross-sectional view is shown in FIG. The plan view is the same as FIG. Moreover, the modification of material and a dimension is the same as 1st embodiment.

The modified layer 20 is not a complete Si ₃ N ₄ film, but may be a film in which a large amount of nitrogen (typically 5% or more, more preferably 15% or more) is introduced into SiO _2. good. The nitrogen content in these modified layers can be set to a desired content depending on the nitriding conditions.

  In the case of the first embodiment, since the cap sidewall insulating film 19 is provided on the side surface of the first cap insulating film 8, the entire cap insulating film (the first cap insulating film, the second cap insulating film 19) is formed by the thickness of the cap sidewall insulating film 19. The entire width including the cap insulating film and the cap side wall insulating film) in the fin width direction (the width in the horizontal direction in FIG. 5A: the width in the direction perpendicular to the channel current) is increased. In the embodiment, since the cap sidewall insulating film 19 is provided on the side surface inside the first cap insulating film 8, the entire width of the cap insulating film is suppressed, and as a result, the semiconductor layer is formed by etching using the cap insulating film as a mask. It becomes easy to reduce the width Wfin (fin width) of the Fin layer. In general, in a FinFET, as the fin width Wfin is smaller, the short channel effect is suppressed and the performance is improved. Therefore, the second embodiment is effective in improving the performance of the short channel transistor.

Further, since the nitriding process is superior in controllability of the thickness of a nitride film (or a region where a large amount of nitrogen is introduced into the SiO ₂ film) formed compared to the CVD process, the nitriding process is processed compared to the first embodiment. Excellent accuracy.

(Third embodiment)
In the first and second embodiments, a form in which the second cap insulating film 9 is not provided may be used. A case where the second cap insulating film 9 is not provided in the first and second embodiments is shown in FIGS. It is drawing corresponding to FIG. 6, FIG. 12, respectively.

  When the third embodiment is applied to the first embodiment, the upper portion of the first cap insulating film 8 is etched by the pretreatment for forming the gate insulating film, but the side surface is protected by the cap side wall insulating film. The cap insulating film does not recede by etching, and if the first cap insulating film 8 is thicker (typically 15 nm or more), the first cap insulating film 8 is protected by the cap side wall insulating film. Since it is not lost, the same effect as the first and second embodiments can be obtained.

  In the second embodiment, the second cap insulating film material 9 is provided. However, when the third embodiment is applied to the second embodiment, only the first cap insulating film material 8 is deposited, Nitriding treatment (radical nitridation, thermal nitridation, nitrogen ion implantation) may be performed on the upper surface and side surfaces of the one-cap insulating film material 8. In this case, the modified layer is formed on the upper surface and the side surface of the first cap insulating film 8. Subsequently, when the modified layer 20 on the semiconductor region is removed prior to the process of processing the semiconductor region by etching, for example, if the modified layer 20 on the cap insulating film is covered with a resist or the like, a completed transistor is obtained. In this case, a configuration having the modified layer 20 on the upper surface and side surfaces of the cap insulating film is obtained. This form is also effective in suppressing the exposure of the upper corner of the semiconductor and obtaining the effects of the invention.

  Note that when the third embodiment is applied to the second embodiment, the semiconductor layer is formed in a process corresponding to FIG. 9 if a condition in which the nitriding rate of the oxide film (first cap insulating film) is larger than the nitriding rate of the semiconductor layer is used. Since a thicker nitride film is formed on the first cap insulating film than above, the nitride film on the first cap insulating film is left after the nitride film on the semiconductor layer is removed, and the second cap insulating film Even when the deposition of 9 is omitted, a structure in which the upper and side surfaces of the first cap insulating film are covered with the nitride film can be formed.

(Fourth embodiment)
The first, second, and third embodiments may be used for manufacturing a FinFET that does not have the buried insulating layer 2. The manufacturing method is the same as that of the first, second, and third embodiments except that a normal bulk substrate is used instead of the SOI substrate and a step of forming the field insulating film 21 is included. In the present invention, the “base” means an arbitrary plane parallel (horizontal) to the substrate.

  In the first and second embodiments, the case where no embedded insulating layer is provided is shown in FIGS. It is drawing corresponding to FIG. 6, FIG. 12, respectively.

The field insulating film 21 is formed by etching a silicon substrate to form a Fin region (for example, it does not have a portion corresponding to the buried insulating layer 2 in FIGS. 5 and 11, and the thickness of the buried insulating layer 2 is below the semiconductor region 3. After that, the extended portion corresponds to a configuration in which the extended portion is connected to the semiconductor substrate 1). After that, for example, an insulating film is deposited (for example, deposition of SiO ₂ by CVD), and insulation by CMP using the second cap insulating film as a mask flattening the film (SiO 2 in the above example deposited by _CVD), (in the above example SiO 2 deposited by _CVD) an insulating film can be formed by selective etch back. At this time, a field insulating film 21 made of an insulating film (SiO ₂ deposited by CVD in the above example) is formed in a portion corresponding to the buried insulating layer 2 in FIGS. The

(Another embodiment of the invention)
The FinFET of each embodiment is a double gate type field effect transistor in which a thick cap insulating film is provided on a semiconductor region and a channel region is formed only on a side surface. The FinFET of each embodiment has a semiconductor region protruding upward with respect to the substrate plane, a cap insulating film provided on the upper surface of the semiconductor region, and a gate insulating film provided on the side surface of the semiconductor region. A gate electrode is provided extending from the upper part of the cap insulating film to the side of the semiconductor region so as to straddle the semiconductor region and the cap insulating film. Further, source / drain regions are provided on both sides of the gate electrode in the semiconductor region.

The FinFET cap insulating film of each embodiment is such that at least a part of the side surface in the extending direction of the side surface of the semiconductor region in contact with the semiconductor region has an etching rate higher than that of SiO _{2 with} respect to wet etching using an HF solution. Is a low side etching resistant region (at least a part of the side surface of the cap insulating film located in the direction in which the side surface of the semiconductor region extends upward is a side etching resistant region).

  The FinFET of each embodiment includes a step of forming a first insulating film, a step of providing an insulating film side wall made of a second insulating film in contact with a side surface of the first insulating film, a first insulating film, and a second insulating film. The semiconductor layer is etched using the insulating film (side wall of the insulating film) as a mask to form a semiconductor region protruding upward with respect to the substrate plane. The step of forming the first insulating film corresponds to, for example, the step of forming the central region of the first embodiment and the second embodiment. The step of forming the second insulating film corresponds to the step of forming the side face etching resistant region (cap side wall insulating film) of the first embodiment and the second embodiment.

The semiconductor substrate 1 is typically a silicon substrate. The buried insulating layer 2 is typically SiO ₂ and its film thickness is typically 50 nm to 400 nm. However, the effect of the invention does not change even if the material and film thickness of the buried insulating layer 2 have other configurations. The semiconductor layer 3 is typically silicon. The semiconductor layer may be silicon germanium, germanium, or other semiconductor material. Further, it may be a multilayer film made of silicon and a material other than silicon, or a multilayer film made of materials other than silicon. The thickness of the semiconductor layer 3 is typically 20 nm to 200 nm, but the effect of the invention does not change even if the film thickness has other configurations.

The second cap insulating film 9 and the cap side surface insulating film 19 are resistant to a pretreatment process prior to the formation of the gate insulating film, specifically, for example, removal of the sacrificial oxide film by hydrofluoric acid, dilute hydrofluoric acid, or buffered hydrofluoric acid. It is sufficient to use a material with a certain amount (hereinafter referred to as a material resistant to hydrofluoric acid). The term “resistance” as used herein means that the etching rate for the sacrificial oxide film (SiO ₂ film) is smaller than the etching rate for wet etching using a hydrofluoric acid solution, and typically the etching rate is ½ or less. Is preferable, and it is more preferable that it is 1/5 or less.

In the removal of the sacrificial oxide film, hydrofluoric acid solutions having various configurations and concentrations are used. As a material resistant to hydrofluoric acid, for example, wet etching at room temperature using a 1% solution dilute hydrofluoric acid, A material having an etching rate smaller than that of the SiO ₂ film formed by thermal oxidation may be selected. More typically, a material whose etching rate is 1/2 or less that of a SiO ₂ film formed by thermal oxidation with respect to wet etching at room temperature using 1% dilute hydrofluoric acid as a material resistant to hydrofluoric acid. Is preferable, and it is more preferable to select a material that is 1/5 or less.

The reason for this is a typical sacrificial oxide film removal process, resistance to the above-described wet etching at room temperature using a 1% dilute hydrofluoric acid solution (SiO 2 having an etching rate formed by thermal oxidation). If the material has 1/2 or less of ₂ films, more preferably 1/5 or less), the composition and concentration of the hydrofluoric acid solution actually used for removing the sacrificial oxide film is different from the 1% dilute hydrofluoric acid solution. As a result, even if the etching rate with respect to SiO ₂ or the etching rate with respect to a material having resistance to hydrofluoric acid is different from that in the case of wet etching at room temperature using 1% dilute hydrofluoric acid, it has the above-mentioned resistance to hydrofluoric acid. material (sufficiently smaller than SiO _2, has an etching rate) obtained sufficient etch resistance to achieve the effects of the invention believed, using 1% dilute hydrofluoric acid solution Resistance to wet etching with hot it is considered that it may be a reference for material selection.

  In addition, when the sacrificial oxide film is removed by an etching process other than wet etching, such as plasma etching or chemical dry etching, it has the above resistance to wet etching at room temperature using a 1% dilute hydrofluoric acid solution. As long as it is a material, it is generally resistant to etching in etching processes other than these wet etchings. Therefore, if resistance to wet etching at room temperature using a 1% dilute hydrofluoric acid solution is used as a criterion for material selection, good.

As a material resistant to hydrofluoric acid, a silicon compound having a nitrogen concentration of 5 atomic% or more is typically used. Typical examples include Si ₃ N ₄ and SiON, and a SiO ₂ film in which nitrogen atoms are introduced by radical nitridation or thermal nitridation.

In the present invention, the sacrificial oxide film is removed under the condition that the magnitude relationship between the etching rate of the material constituting the SiO ₂ and the side surface etching resistant region does not change. That is, the sacrificial oxide film is removed under the condition that the etching rate of the material constituting the side surface etching resistant region is lower than the etching rate of SiO ₂ .

  The material of the first cap insulating film 8 preferably has a dielectric constant lower than that of the cap side wall insulating film 19.

A typical example of satisfying these conditions is that the first cap insulating film 8 is formed of SiO ₂ , the second cap insulating film 9 and the cap side surface insulating film 19 are formed of Si ₃ N _4. A combination of these materials may also be used.

Further, the entire cap insulating film may be formed of a material resistant to the gate insulating film formation pretreatment. For example, the entire cap insulating film is formed of Si ₃ N ₄ resistant to etching with hydrofluoric acid. Even in this case, the problem that the cap insulating film is etched by the pretreatment for forming the gate insulating film can be solved. However, the capacitance between the gate electrode and the upper part of the semiconductor layer is large (because the relative dielectric constant of Si ₃ N ₄ is larger than that of SiO ₂ ), and the electric field concentrates on the upper part of the semiconductor layer. Compared with the case where is formed of a material having a low dielectric constant, the leakage current is increased.

  Note that when simply referred to as a cap insulating film in this specification, it means the whole insulating film provided on the semiconductor layer, which includes a first cap insulating film, a second cap insulating film, a cap sidewall insulating film, and the like. .

This will be described with reference to FIGS. 19 and 20 are enlarged views of the vicinity of the upper portion of the semiconductor layer in the cross sections of FIGS. 6 (a) and 7 (a). When the upper corner 23 of the semiconductor layer is not covered with the cap insulating film (FIGS. 20A and 20B), the capacitance C1 between the gate electrode and the semiconductor layer is very large, electric field concentration occurs, and leakage current is reduced. Increase. On the other hand, when the entire cap insulating film 24 is made of Si ₃ N ₄ (FIG. 19B), the surface of the cap insulating film is made of Si ₃ N ₄ and the central portion is made of Si ₃ N ₄ such as SiO _2. In the case of being formed of a material having a low dielectric constant (FIG. 19A), in any case, since the upper corner 23 of the semiconductor layer is covered with the cap insulating film, the capacitance C1 between the gate electrode and the semiconductor layer is as shown in FIG. , The electric field concentration is reduced and the leakage current is reduced. Further, comparing the cases of FIG. 19A and FIG. 19B, when the dielectric constant is low at the center of the cap insulating film as shown in FIG. 19A, the capacitance C1 between the gate electrode and the semiconductor layer is reduced. Since it is further smaller than that in the case of FIG. 19B, the effect on relaxation of electric field concentration and reduction of leakage current is further increased.

The electric field relaxation effect described with reference to FIG. 19A can be obtained if there is a region having a dielectric constant lower than that of the cap side wall insulating film in at least a part of the cap insulating film. A mode in which a region having a dielectric constant lower than that of the cap sidewall insulating film may be provided at least partially. For example, in the form of FIG. 19A, even if a very small part of the first cap insulating film close to the semiconductor region is formed by a region having a higher dielectric constant than SiO ₂ such as SiON or Si ₃ N _4. good. However, it is preferable that the volume ratio of the region having a low dielectric constant in the volume of the entire cap insulating film is larger because the electric field relaxation effect described with reference to FIG. Further, if a region having a low dielectric constant is provided in the vicinity of the upper corner of the semiconductor region, the electric field relaxation effect described with reference to FIG. 19A becomes prominent, and therefore, it is sandwiched between the cap sidewall insulating films in the cross section of FIG. It is preferable that a region having a dielectric constant lower than that of the cap sidewall insulating film is provided in the region where the dielectric constant is lower than that of the cap sidewall insulating film, particularly in a region sandwiched between the cap sidewall insulating films and in contact with the cap sidewall insulating film. The form which provides is preferable.

Further, the region having a dielectric constant lower than that of the cap sidewall insulating film may be formed of a material other than SiO ₂ that satisfies this condition, such as SiOF or an organic film. The region having a lower dielectric constant than the cap sidewall insulating film may be a cavity.

The cap sidewall insulating film 19 is typically a Si ₃ N ₄ film. The thickness of the cap sidewall insulating film 19 is typically 2 nm to 20 nm, and is usually in the range of 3 nm to 10 nm. However, it may not be in this range. In particular, when the cap sidewall insulating film 19 is formed by plasma nitriding or the like, it may be 3 nm or less, for example, 1 to 2 nm. Further, although there is a step of forming the cap side wall insulating film 19, even if a manufacturing method is used in which the cap side wall insulating film 19 is lost due to a pretreatment step or the like prior to the gate insulating film formation and does not remain in the completed transistor. Since the cap side wall insulating film 19 having high resistance to the pretreatment is once provided, the loss of the first cap insulating film is reduced, which is effective.

  In the drawings of the present specification, a case where the semiconductor region, the first cap insulating film, and the second cap insulating film are substantially rectangular parallelepipeds is illustrated as a typical example, but in actuality, the etching process, the thermal oxidation process, etc. You may have the form which shifted | deviated from the rectangular parallelepiped by the influence of the manufacturing process. For example, the corner portion of the semiconductor region may be rounded by a thermal oxidation process such as sacrificial oxidation or gate oxidation. Further, for example, due to the influence of an etching process such as RIE, the side surfaces of the respective components such as the semiconductor region, the first cap insulating film, and the second cap insulating film may have a taper or a gently curved surface.

  The fin width (the width Wfin of the semiconductor layer 3 in the horizontal direction in FIG. 7A) is usually 5 nm to 50 nm, typically 10 nm to 35 nm. However, in a fine transistor having a gate length of 50 nm or less, the fin width Wfin may be 5 nm or less.

  In the embodiment, the element region has a single rectangular shape. However, the element region may have a multi-fin structure in which a plurality of fins (semiconductor regions) are combined. In this case, the A-A ′ section in FIG. 14 has a shape corresponding to the A-A ′ section in each embodiment of the present invention. Each fin in FIG. 14 is arranged so that the directions of channel currents flowing in each fin are parallel to each other. In the field effect transistor of FIG. 14A, an independent gate electrode and source / drain region are provided for each fin. In the field effect transistor of FIG. 14B, in addition to the fins, the connection semiconductor region 31 that extends in the direction orthogonal to the direction of the channel current and is connected with the fins interposed therebetween is a part of the source / drain regions. As provided. Further, one gate electrode is formed so as to straddle the fins connected by the connecting semiconductor region 31.

  The gate electrode is made of polysilicon, or a conductive material such as metal or metal silicide.

  The channel formation region (the portion covered with the gate electrode) of the semiconductor region forming the fin region may or may not be doped with impurities. When the gate electrode is polysilicon, an n-type impurity is usually introduced into an n-channel transistor and an n-type impurity is introduced into a p-channel transistor.

  The object of the present invention is to prevent the upper corner of the semiconductor layer located under the cap insulating film (8, 9, 22) from being exposed by providing the cap side insulating film 19, so that the cap side surface insulation is provided. The film 19 does not need to cover the entire side surface of the cap insulating film (8, 9, 22), and only needs to cover the side surface of the cap insulating film in contact with the semiconductor layer, that is, the lower side surface of the cap insulating film. Similarly, a manufacturing process for covering only the side surface of the cap insulating film in contact with the semiconductor layer, that is, the lower side surface of the cap insulating film may be used. Examples of these are shown in FIGS.

26 (a), 26 (b), and 26 (c) are cross-sectional views corresponding to the steps and cross sections of FIGS. 4 (a), 5 (a), and 6 (a), respectively. In this embodiment, in the third embodiment in which the cap insulating film 22 is a single layer (typically made of SiO ₂ ), after the cap cover insulating film 10 is deposited on the whole, the cap cover insulating film 10 is etched by RIE or the like. In the step of forming the cap sidewall insulating film 19 by etching back by the process, when the etch back time is set long, the upper portion of the cap cover insulating film 10 on the side surface of the cap insulating film is etched and lost. Is done.

27 (a), 27 (b), and 27 (c) are cross-sectional views corresponding to the processes and cross sections of FIGS. 4 (a), 5 (a), and 6 (a), respectively. is there. In this embodiment, the cap insulating film has two layers (typically, a first cap insulating film 8 made of SiO ₂ and a second cap insulating film 9 made of Si ₃ N ₄ ). Similarly to the case of No. 26, after the cap cover insulating film 10 is deposited on the entire surface, the cap cover insulating film 10 is etched back by an etching process such as RIE, and in the step of forming the cap side wall insulating film 19, the etch back time Is set to be long, the upper portion of the cap cover insulating film 10 on the side surface of the cap insulating film is etched and lost.

  FIG. 28 is a plan view corresponding to the planes of FIGS. 6C and 8 and shows the positional relationship between the gate electrode 5 and the semiconductor layer 3. FIG. 29 is a cross-sectional view corresponding to the step and cross section of FIG.

  In the present invention, in the region covered with the gate electrode (symbol 25 in FIG. 28, hatched hatched portion), the upper corner of the semiconductor layer located under the cap insulating film (8, 9, 22) is exposed. Since the purpose is to prevent by providing the cap side surface insulating film 19, a structure and a manufacturing method in which the cap side surface insulating film 19 is provided in a region not covered by the gate electrode (a symbol 26 in FIG. 28, a halftone dot portion). Any structure and manufacturing method in which the cap side surface insulating film 19 is not provided may be used. Also, a structure and manufacturing method in which the cap side surface insulating film 19 is provided in a part of the region not covered by the gate electrode (symbol 26 in FIG. 28, halftone dot portion) and the cap side surface insulating film 19 is not provided in part. It may be used.

  In addition, the cap side insulating film 19 is not provided in the entire region of the cap insulating film covered with the gate electrode (symbol 25 in FIG. 28, hatched hatched portion), but the region covered with the gate electrode (see FIG. 28). The cap side surface insulating film 19 is not provided in a part of the symbol 25, the hatched hatched portion, but at least both side surfaces parallel to the source / drain connecting direction in the region 25 covered with the gate electrode (symbol in FIG. 28). 25, the hatched hatch portion), and a structure and a manufacturing method in which the cap side surface insulating film 19 is provided over a certain region may be used. A cap side surface insulating film 19 is provided in the central portion of the gate electrode and in the vicinity thereof (the lower portion and the vicinity of the position indicated by AA ′ in FIG. 28), and in the vicinity of the end portion of the gate electrode toward the source / drain region. Then, a structure in which the cap side surface insulating film 19 is not provided may be used.

  In the direction connecting the source / drain regions, if there is a region where the upper corner of the semiconductor region is not exposed even if only in a certain region, the leakage current due to the parasitic transistor at the upper corner of the semiconductor region is reduced. Therefore, even if the cap side surface insulating film 19 is not provided in the entire region of the cap insulating film covered by the gate electrode, the cap side surface insulating film 19 is provided at one location in the direction connecting the source / drain. If so, the effects of the invention can be obtained.

  That is, of the side surface covered with the gate electrode of the cap insulating film, the side surface etching resistant region may be provided over the entire length in the direction connecting the opposing source / drain regions (channel current direction), or only a part thereof. (All of the side surfaces covered with the gate electrode of the cap insulating film may be side etching resistant regions, or part of the side surfaces may be side etching resistant regions). .

  For the same reason, the upper surface etching-resistant region may be provided over the entire length of the upper surface covered with the gate electrode of the cap insulating film in the direction connecting the opposing source / drain regions (channel current direction). The upper surface of the cap insulating film covered by the gate electrode may be an upper surface etching resistant region, or a part of the upper surface may be an upper surface etching resistant region. May be)

  However, in order to obtain the GIDL suppressing effect in addition to the parasitic transistor suppressing effect, the semiconductor region is formed near the end of the source / drain region, for example, near the pn junction between the source / drain region and the channel forming region. It is desirable that a cap side surface insulating film 19 is provided thereon.

In the present specification, the “side surface” represents a surface substantially perpendicular to the substrate of each component (semiconductor region, central region, cap insulating film, SiO ₂ region). In particular, the “side surface of the cap insulating film covered with the gate electrode in the direction of extension of the side surface of the semiconductor region” is substantially perpendicular to the substrate and in the direction toward the source / drain region (channel current direction). Represents a parallel plane. Further, the “upper surface” represents a surface substantially parallel to the base of each component. However, it includes cases where they are not completely vertical or completely parallel due to process reasons. The cap insulating film of the present invention has a side surface in the extending direction of the semiconductor region (a side surface when the side surface of the semiconductor region is extended upward in the surface direction). In this specification, the side surface etching resistant region is formed on at least a part of the side surface defined as described above. Further, an upper surface etching resistant region and a side surface etching resistant region are formed on at least a part of the upper surface and the side surface, respectively.

  In this specification, when the top surface etching resistant region and the side surface side etching resistant region are in contact with each other, the side surface etching resistant region may cover the side surface of the top surface etching resistant region at a portion where both are connected (see FIG. 7 (a)), an upper surface etching resistant region may cover the upper surface of the side surface etching resistant region (FIG. 13A). Further, the side surface etching resistant region and the upper surface etching resistant region may be formed of a continuous material.

  In other words, in the present invention, the portion of the cap insulating film that is in contact with the cap insulating film may be an upper surface etching resistant region or a side surface etching resistant region. Whether this region is an upper surface etching resistant region or a side surface etching resistant region depends on the FinFET manufacturing method. For example, in the manufacturing method of the first embodiment, as shown in FIG. 7A, side etching resistant regions 19 are provided on the side surfaces of the central region 8 and the upper etching resistant region 9, and the upper corner of the cap insulating film is formed. Is a side etching resistant region. On the other hand, in the manufacturing method of the second embodiment, as shown in FIG. 13A, the upper surface etching resistant region 9 is provided on the upper surface of the central region 8 and the side surface etching resistant region 19, and the upper corner of the cap insulating film is formed. Is an etching resistant region on the upper surface.

In the present invention, in the cross section perpendicular to the channel current direction (the cross section perpendicular to the direction connecting the source / drain regions; for example, the cross section corresponding to the cross section of FIG. The region is connected, and the upper surface of the cap insulating film covers the entire upper surface with the etching resistant region, or the side surface etching resistant region and the upper surface etching resistant region are connected, and the etching resistance against the etching of the sacrificial oxide film of the cap insulating film Part (typically a part having no resistance to hydrofluoric acid, more typically a part of the cap insulating film that is not a side etching resistant region, more typically a part forming a central region, and more specifically, for example, When the entire top surface of the portion) composed of SiO ₂ covers the upper surface etch resistant area, the cap insulating film with etching resistance in its cross-section material Therefore, the effect of preventing the etching of the cap insulating film is great, which is particularly preferable.

  The first cap insulating film and the cap sidewall insulating film are arranged on the upper surface of the semiconductor region, and the bottom of the first cap insulating film and the bottom of the cap sidewall insulating film have the same height. However, a slight step that is not originally intended may be formed between the bottoms of the two due to a process reason, for example, a reason for the etching process of the first cap insulating film.

  In addition, when the sacrificial oxidation or the gate insulating film is formed, an insulating film having a very small thickness, which is thinner than the sacrificial oxide film or thinner than the gate insulating film, penetrates between the cap sidewall insulating film and the semiconductor region. However, these very thin insulating films do not significantly affect the effects of the invention and have little effect on the transistor characteristics. In the present specification, it is also described that the cap side wall insulating film and the semiconductor region are in contact with each other even when entering between the side wall insulating film and the semiconductor region. The same applies to the case where a very small gap generated by etching an insulating film having such a small thickness enters between the cap sidewall insulating film and the semiconductor region.

  FIG. 7B shows that the cap insulating films (first cap insulating film 8, second cap insulating film 9, and cap side surface insulating film 19) form the source / drain regions in the region 26 not covered with the gate electrode. FIG. 5 is a cross-sectional view of a form removed for forming a silicide region on a source / drain region.

  FIG. 29 is a cross section of a form in which a cap insulating film (first cap insulating film 8, second cap insulating film 9, cap side surface insulating film 19) remains in a part of the region 26 not covered with the gate electrode. This is a figure which is not removed prior to the source / drain region forming step or the silicide region forming step on the source / drain region, and is not covered by the gate electrode even when the transistor is completed. Part of the cap insulating film (the first cap insulating film 8, the second cap insulating film 9, and the cap side surface insulating film 19) remains. In this embodiment, for example, when the source / drain region is formed by oblique ion implantation from the side surface of the semiconductor layer, the cap insulating film on the source / drain region is not formed up to the end of the source / drain region of the silicide region. It is formed when it is not necessary to remove everything.

Note that the composition ratio of atoms in a material composed of a plurality of elements, for example, a material such as SiO ₂ or Si ₃ N ₄ , used as a component of the field effect transistor in each embodiment, is determined to some extent from the stoichiometric composition. It may be shifted. In particular, the composition of the Si ₃ N ₄ film used as a material resistant to hydrofluoric acid may deviate from the stoichiometric composition as long as necessary hydrofluoric acid resistance is obtained.

Moreover, even if other elements are mixed in the constituent material of the field effect transistor of the present invention such as SiO ₂ and Si ₃ N ₄ within the range satisfying the range of the etching rate defined in the present invention. good.

A channel concentration region (a portion of the semiconductor region sandwiched between the source / drain regions and covered with the gate electrode) may be subjected to low concentration channel ion implantation, or channel ion implantation may be performed. It does not have to be. A channel forming region adjacent to the first conductivity type source / drain region may have a halo region into which the second conductivity type impurity is introduced over a certain width.

Claims (16)

A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on an upper surface of the semiconductor region; and the semiconductor region extending from the upper part of the cap insulating film so as to straddle the semiconductor region and the cap insulating film. A gate electrode extending laterally, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
Of the cap insulating film covered with the gate electrode, at least a part of the side surface in the extending direction of the side surface of the semiconductor region in contact with the semiconductor region is made of SiO ₂ by wet etching using an HF solution. even Chi lifting a lower etching rate side etching resistant region,
On the two opposite side surfaces covered with the gate electrode of the cap insulating film, the side surface etching resistant region is provided oppositely, and at a position sandwiched between the opposed side surface etching resistant regions in the cap insulating film, A field effect transistor having a central region made of a material different from that of the side etching resistant region . 2. The field effect transistor according to claim 1 , wherein the central region is made of a material having a dielectric constant lower than that of the side surface etching resistant region. The central region, the field effect transistor according to claim 1 or 2, characterized in that of SiO _2. A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on an upper surface of the semiconductor region; and the semiconductor region extending from the upper part of the cap insulating film so as to straddle the semiconductor region and the cap insulating film. A gate electrode extending laterally, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
Si ₃ N ₄ regions provided on the upper surface and both side surfaces of the SiO ₂ region;
A field effect transistor comprising: A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on an upper surface of the semiconductor region; and the semiconductor region extending from the upper part of the cap insulating film so as to straddle the semiconductor region and the cap insulating film. A gate electrode extending laterally, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
SiON regions containing silicon, oxygen and 5 atomic% or more of nitrogen provided on both sides of the SiO ₂ region;
An Si ₃ N ₄ region provided on the upper surface of the SiO ₂ region and the SiON region;
A field effect transistor comprising: A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on an upper surface of the semiconductor region; and the semiconductor region extending from the upper part of the cap insulating film so as to straddle the semiconductor region and the cap insulating film. A gate electrode extending laterally, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
SiON region containing silicon, oxygen and 5 atomic% or more nitrogen provided on the upper surface and both side surfaces of the SiO ₂ region;
A field effect transistor comprising: A semiconductor region protruding upward with respect to the substrate plane; a cap insulating film provided on an upper surface of the semiconductor region; and the semiconductor region extending from the upper part of the cap insulating film so as to straddle the semiconductor region and the cap insulating film. A gate electrode extending laterally, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor region,
A field effect transistor having a source / drain region provided in the semiconductor region so as to sandwich the semiconductor region covered with the gate electrode, and a channel region formed on a side surface of the semiconductor region. ,
The cap insulating film includes a SiO ₂ region provided on the semiconductor region,
Provided on both sides of the SiO ₂ region, and the Si ₃ N ₄ regions protruding upwardly from the sides of the SiO ₂ region,
A field effect transistor comprising: A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
An etching step of forming a patterned first insulating film on the semiconductor layer;
An insulating film sidewall made of a Si ₃ N ₄ film in contact with a side surface of the first insulating film is patterned on the semiconductor layer exposed by an etching process for forming a patterned first insulating film. Providing a position near the first insulating film;
Etching the semiconductor layer using the first insulating film and the insulating film side wall made of the Si ₃ N ₄ film as a mask to form a semiconductor region protruding upward with respect to the substrate plane;
A method for producing a field-effect transistor, comprising: Forming a sacrificial oxide film on a side surface of the semiconductor region protruding upward with respect to the substrate plane;
And further removing the sacrificial oxide film by wet etching,
9. The electric field according to claim 8 , wherein an insulating film side wall made of the Si ₃ N ₄ film is made of a material having a lower etching rate than a sacrificial oxide film formed on a side surface of the semiconductor region with respect to wet etching. Method for producing effect transistor. A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
(A) Sacrificial oxidation formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces Providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;
(B) using the cap insulating film as a mask, and forming a semiconductor region projecting upward from the base body below the cap insulating film;
Have
(A) providing the cap insulating film comprises:
Providing a central region on the semiconductor layer;
Providing a side etching resistant region on the side surface of the central region by depositing a side etching resistant region material on the semiconductor layer and the central region and then performing etch back;
Method of manufacturing to that electric field-effect transistor, comprising a. A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
(A) Sacrificial oxidation formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces Providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;
(B) using the cap insulating film as a mask, and forming a semiconductor region projecting upward from the base body below the cap insulating film;
Have
(A) providing the cap insulating film comprises:
After depositing a central region material on the semiconductor layer and depositing a top surface etching resistant region material on the central region material, patterning the central region material and the top surface etching resistant region material and subjecting the central region to wet etching Providing a top etching resistant region having a lower etching rate than the sacrificial oxide film formed on the side surface of the semiconductor region;
Providing a side surface etching resistant region on the side surface of the central region and the top surface etching resistant region;
Method of manufacturing to that electric field-effect transistor, comprising a. The step of providing the side surface etching-resistant region includes:
12. The method of manufacturing a field effect transistor according to claim 11 , wherein the side surface etching resistant region material is deposited on the entire surface, followed by etching back. It said side deposition of etch-resistant regions material and a top etch resistant area material, chemical vapor deposition (CVD) or atomic layer deposition (ALD: atomic layer deposition) ~ claim 10, characterized in that it is carried out by a method 12 The method for producing a field effect transistor according to any one of the above. A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
(A) Sacrificial oxidation formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces Providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;
(B) using the cap insulating film as a mask, and forming a semiconductor region projecting upward from the base body below the cap insulating film;
Have
(A) providing the cap insulating film comprises:
Providing a substantially rectangular parallelepiped cap insulating film material on the semiconductor layer;
Nitriding the side and top surfaces of the cap insulating film material and the semiconductor layer under the condition that the nitriding rate of the cap insulating film material is higher than the nitriding rate of the semiconductor layer;
Performing etch back, and forming a side surface subjected to nitriding of the cap insulating film material as a side surface etching resistant region, and a top surface subjected to nitriding processing of the cap insulating film material as a top surface etching resistant region;
Method of manufacturing to that electric field-effect transistor, comprising a. A method of manufacturing a field effect transistor having a semiconductor region protruding upward from a substrate plane and having a channel region formed on a side surface,
(A) Sacrificial oxidation formed on the side surface of the semiconductor region with respect to wet etching on the semiconductor layer having a pair of side surfaces perpendicular to the semiconductor layer and facing each other, and in contact with the semiconductor layer on the pair of side surfaces Providing at least one cap insulating film having a side etching resistant region having an etching rate lower than that of the film;
(B) using the cap insulating film as a mask, and forming a semiconductor region projecting upward from the base body below the cap insulating film;
Have
(A) providing the cap insulating film comprises:
A substantially rectangular parallelepiped cap insulating film material on the semiconductor layer, and a step of providing an upper surface etching-resistant region on the cap insulating film material;
Nitriding the side surface of the cap insulating film material and the semiconductor layer; and
Performing etch back, and forming a side surface on which the nitriding treatment of the cap insulating film material is performed as a side etching resistant region;
Method of manufacturing to that electric field-effect transistor, comprising a. 16. The method of manufacturing a field effect transistor according to claim 14 , wherein the nitriding treatment is radical nitriding, thermal nitriding, or nitrogen ion implantation.

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