TWI524531B - Fin-type field effect transistor (finfet) and method of fabricating a semiconductor device - Google Patents

Description

Fin field effect transistor and method of manufacturing semiconductor device

The present invention relates to the fabrication of integrated circuits, and more particularly to a fin field effect transistor and a method of fabricating a semiconductor device.

In order to pursue higher component density, better performance and lower cost, the semiconductor industry has evolved into a nanotechnology process node. As the evolution progresses, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs such as fin-type field-effect transistor devices. A typical fin-type field effect crystal system is formed by extruding one of the tantalum layers of one of the substrates and extending from a very thin vertical "fin" at a substrate (or fin or fin-like structure). ) formed. This fin typically includes a crucible and forms the body of the transistor device. The channels of the transistor are formed within the vertically extending fins. The gate is formed (eg, wrapped) over the fin. This type of gate allows for greater control of the channel. However, there is still a need for greater control of the gate. The method of performing the above control includes the use of a completely gate-all-around and/or omega structure or a quasi-surround structure. Similarly, the fabrication of the quasi-surround structure is subject to process challenges when it is introduced into the SOI substrate on the insulating layer.

Therefore, in the current structure of the gate structure with better control conditions When the method is sufficient for some uses, additional improvements may still be required.

According to an embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a substrate having a fin extending from a first surface, wherein the fin includes one of a first composition having a semiconductor material a region and a second region of the overlying second composition having a semiconductor material, wherein the second composition is different from the first composition; modifying the first region of the fin to reduce the semiconductor material a quantity of the first composition; and forming a gate structure on the second region of the fin.

According to still another embodiment, the present invention provides a method of fabricating a semiconductor device, including: providing a main semiconductor substrate; growing a first epitaxial layer on the main semiconductor substrate; growing a second epitaxial layer on the first Forming a fin element including the first epitaxial layer and the second epitaxial layer; etching the first epitaxial layer of the fin element to form the second protrusion having less than the fin element One of the widths of one of the widths of one of the crystal layers; and a channel region forming a transistor in the second epitaxial layer of the fin element.

According to another embodiment, the present invention provides a fin field effect transistor, comprising: a substrate; a fin portion disposed on the substrate, wherein the fin portion includes an inactive region and one of the inactive regions a dry zone, and an active zone on the dry zone, wherein the dry zone has a first width and the active zone has a second width, the first width being less than the second width, and wherein the dry zone has a first composition and the active region has a second composition different from the first composition; and a gate structure disposed on the active region.

In order to make the above objects, features and advantages of the present invention more obvious It is to be understood that the following detailed description of the preferred embodiments and the accompanying drawings are set forth below.

100‧‧‧Manufacture method

102, 104, 106, 108 ‧ ‧ steps

200‧‧‧Semiconductor device

202‧‧‧Fin

204‧‧‧Active Area

206‧‧‧ dry area

208‧‧‧inactive area

210‧‧‧ gate structure

210a‧‧‧ gate dielectric layer

210b‧‧‧gate electrode layer

210c‧‧‧Interface

212‧‧‧gate electrode

214‧‧‧Isolation components

400‧‧‧Manufacture method

402, 404, 406, 408, 410‧‧‧ steps

502‧‧‧Substrate

504‧‧‧ body layer

506‧‧‧ first floor

508‧‧‧ first floor

602‧‧‧Fin

604‧‧‧active area

606‧‧‧ dry area

608‧‧‧inactive area

1000‧‧‧Manufacturing method

1002, 1004, 1006, 1008, 1010, 1012‧ ‧ steps

1102‧‧‧Fin

1104‧‧‧Oxidation zone

1202‧‧‧Fin

1204‧‧‧Oxidation zone

1402‧‧‧Isolation components

1502‧‧ ‧ dry area

1602‧‧ ‧ dry area

1702‧‧‧ Dry area

1704‧‧‧Oxidized materials

1800‧‧‧Fin field effect transistor

1802‧‧‧ Dry area

1804‧‧‧Oxidation Department

1806‧‧‧Semiconductor Materials Division

1808‧‧‧ spacer elements

1810‧‧‧Dielectric/Interlayer Dielectric Layer

1900‧‧‧Fin type field effect transistor device

1902‧‧‧ Dry area

1904‧‧‧Oxidation Department

1904a‧‧‧ first

1904b‧‧‧ second

1906‧‧‧Semiconductor Materials Division

2000‧‧‧Fin type field effect transistor device

2002‧‧‧ dry area

2004‧‧‧Oxidation Department

2006‧‧‧Semiconductor Materials Division

2100‧‧‧Fin type field effect transistor device

2102‧‧‧ Dry area

2104‧‧‧Oxidation Department

2106‧‧‧Semiconductor Materials Division

2200‧‧‧Fin type field effect transistor device

2202‧‧‧ Dry area

2204‧‧‧Oxidation Department

2206‧‧‧Semiconductor Materials Division

2300‧‧‧Fin type field effect transistor device

2302‧‧‧ Dry area

2302a‧‧‧ first

2302b‧‧‧ second

2304‧‧‧Oxidation Department

2306‧‧‧Semiconductor Materials Division

2400‧‧‧Fin type field effect transistor device

2402‧‧‧ Dry area

2404‧‧‧Oxidation Department

2406‧‧‧Semiconductor Materials Division

2500‧‧‧Fin type field effect transistor device

2502‧‧ ‧ dry area

2504‧‧‧Oxidation Department

2506‧‧‧Semiconductor Materials Division

Wa‧‧‧Width

Ws‧‧‧Width

Ws1‧‧‧Width

Ws2‧‧‧Width

Ws3‧‧‧Width

Wp‧‧‧Width

T1‧‧‧ thickness

T2‧‧‧ thickness

1 is a flow chart showing a method of fabricating a fin field effect transistor device (finFET device) in accordance with an embodiment of the present invention.

2 is a perspective view showing a fin field effect transistor device in accordance with an embodiment of the present invention. It is worth noting that, as discussed below, only one portion of a fin field effect transistor component (e.g., one quarter of a gate structure) is shown.

Figure 3 is a cross-sectional view showing a fin field effect transistor device in accordance with another embodiment of the present invention.

4 is a flow chart showing a method of fabricating a fin field effect transistor device having an etched stem region in accordance with an embodiment of the present invention.

Figures 5-9 are a series of cross-sectional views showing one embodiment of a fin field effect transistor device fabricated in accordance with one or more of the fabrication methods illustrated in Figure 4.

Figure 10 is a flow chart showing a method of fabricating a fin field effect transistor device having an oxidized stem region in accordance with an embodiment of the present invention.

Figures 11-17 are a series of cross-sectional views showing various embodiments of a fin field effect transistor device fabricated in accordance with one or more of the fabrication methods illustrated in Figure 10.

18a, 18b, 19a, 19b, 20a, 20b, 21a, 21b, 22a, 22b, 23a, 23b are a series of cross-sectional views showing one or more of the manufacturing methods in accordance with one embodiment of the present invention The steps produce a plurality of embodiments of a fin field effect transistor device.

24a, 24b, 25a, 25b are a series of cross-sectional views showing a p-channel fin field effect transistor device fabricated in one or more steps in a fabrication method in accordance with one embodiment of the present invention. Multiple embodiments.

It will be appreciated that a number of different embodiments, or examples, are provided below for performing different features of the present invention. Specific examples of components and setup scenarios are described below for the purpose of simplifying the present invention. However, such elements and arrangements are for illustrative purposes only and are not intended to limit the invention. Furthermore, the formation of the first component on or in a second component in the description may include the implementation of the first component in direct contact with the second component, and also includes the first component and the second component. The implementation of additional components is included between the components such that there is no direct contact between the first component and the second component. Multiple components may be arbitrarily shown in different sizes for the purposes of simplicity and clarity.

1 is a flow chart showing a method 100 of fabricating a fin field effect transistor device (FinFET device) in accordance with various aspects of the present invention. It will be appreciated that additional steps may be performed before, during or after the fabrication method 100 as shown in FIG. 1, and in other embodiments of the method, some of the steps described below may be substituted or eliminated. As described below, the description of a fin field effect transistor device refers to any fin-based, multi-gate transistor including a nanowire transistor (fin-based, multi-gate). Transistor). The fin field effect transistor devices described herein can be located within a microprocessor, memory cell, and/or other integrated circuitry.

Manufacturing method 100 begins at step 102 by first providing a semiconductor substrate. The substrate may be an elemental semiconductor material such as crystalline germanium and/or germanium, such as a compound semiconductor material including tantalum carbide or gallium arsenide, such as including gallium phosphide, indium phosphide, indium arsenide, and/or germanium. A III-V semiconductor material of indium, such as an alloy semiconductor material including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or a combination thereof. The semiconductor substrate can include a plurality of regions that are suitably doped (eg, p-type conductivity or n-type conductivity). The semiconductor substrate may not be an SOI substrate, or in other words, a bulk semiconductor substrate. In other embodiments, the semiconductor substrate is an insulating layer overlying SOI substrate. The substrate can include a plurality of epitaxial layers and is, for example, referred to as a multilayer substrate.

Manufacturing method 100 then proceeds to step 104 to form a fin element (or fin) that extends from one of the substrates. A plurality of fins may be formed such that a plurality of isolation regions such as shallow trench isolation (STI) elements may be interposed between the fins. Such fins may comprise any suitable material such as a scorpion (skull fin). In one embodiment, the fins may comprise multiple layers of one or more epitaxial layers grown on the body semiconductor substrate and/or the body semiconductor substrate itself. The fins may be formed by any suitable process including deposition, lithography, etching, epitaxy, and/or other suitable processes. An example of a lithography process can include forming a photoresist layer (resist) to cover the substrate (eg, on a germanium layer or other epitaxial layer), exposing the photoresist to form a pattern, performing an exposure post-baking process, And developing the photoresist to form including One of the photoresists shields the component. The fins may then be formed using a reactive ion etching process and/or other suitable process to etch the germanium layer. Alternatively, the fins may be formed by a dual pattern lithography (DPL) process. The double pattern lithography is a method of forming a pattern on a substrate by dividing the pattern into two staggered patterns. Double pattern lithography achieves a higher density of components such as fins. A variety of double pattern lithography including double exposure (e.g., using two sets of reticle), spacers forming adjacent elements, and removing elements to form a pattern of spacers, a fixed resist, and/or other suitable double patterns of suitable processes can be used. Lithography. Again, each fin may comprise multiple layers (eg, a host semiconductor substrate and a covered epitaxial layer). Alternatively, a fin can be epitaxially grown in the opening in the shallow trench isolation element. For example, the openings or holes can be made by etching the fins in the substrate, the shallow trench spacers are filled in the spaces between the fins, and then the fins are removed by etching. These openings are formed.

Manufacturing method 100 then proceeds to step 106 to form a stem region within the fin structure (also referred to as the fin) extending from the substrate. This dry zone includes the area of the fin below the active area of the fin. The active region of the fin can provide a channel region for the transistor device associated with the fin (ie, the fin field effect transistor). The width of the dry zone may be reduced, partially oxidized, fully oxidized, and/or reduced by conductive regions below the active region of the fin, as compared to the active region (notably, The dimensions of the fin relative to the gate length of the device are referred to below as widths as shown in the cross-sectional views discussed below. Several embodiments for forming a dry zone will be further explained below.

The dry zone may be formed in a portion of the fin having a particular composition, such as a composition different from the active region of the fin. In an embodiment, The dry zone includes one of a composition that is selectively etched and/or selectively oxidized compared to the composition of the active region of the fin. The dry zone can include a first epitaxial layer and the active zone can include a second epitaxial layer. One of the fin regions may be located below the dry region. In an embodiment, the inactive region may have a composition of a body semiconductor substrate.

In one embodiment, the dry zone is formed in a replacement-gate or gate-last method (eg, modifying a previously formed fin). In one embodiment, after the fin is formed, a dummy gate is formed thereon. A spacer element and a surrounding interlayer dielectric layer can form and surround the dummy gate structure. This dummy gate structure is then removed to form a trench. The formation of the dry regions (e.g., etching and or oxidation) can be performed within the openings provided by the trenches.

The method 100 then proceeds to step 108 to form a gate structure on the active region of the fin. The gate structure can be formed by a replacement gate or gate final method (e.g., formed in the aforementioned trench). The gate structure may include a gate dielectric layer, a gate electrode layer, and/or other suitable film layers such as a cap layer, an interface layer, a work function layer, a diffusion/barrier layer, and the like. The gate structure and/or fins may be patterned such that the gate structure may wrap around one of the fin structures. For example, the gate structure can contact at least three surfaces of the active region of at least the fin structure (eg, the top surface and the opposite sides). In another embodiment, the gate may wrap around or quasi-around the fin structure such that the gate structure contacts a fourth surface (eg, the bottom surface) of the active region of the fin structure. Hereinafter, such a gate can be referred to as an omega-gate or quasi-around gate structure.

The gate dielectric layer can include, for example, hafnium oxide, tantalum nitride, high dielectric materials, other suitable dielectric materials, and/or combinations thereof. Examples of high dielectric constant dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, ceria-oxidized aluminum alloy, other suitable high dielectric constant dielectric materials, and/or Or a combination thereof. The gate electrode includes any suitable material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel telluride, cobalt telluride, titanium nitride, tungsten nitride, TiAl, TiAlN, TaCN, TaC. , TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate last or replacement gate method can be employed to form the gate structure. A plurality of source/drain region elements may be formed over the extensions on both sides of the active region of the fin structure. Such source/drain regions may be formed by ion cloth values, diffusion, laser tempering, epitaxial growth, and/or other suitable processes.

The manufacturing method 100 can be carried out by any of the following methods of the manufacturing method 400 and the manufacturing method 1000 as shown in FIGS. 4 and 10, respectively. The efficacy of some of the embodiments of the method of manufacture 100, or portions thereof, may include, for example, improving the subthreshold slope (swing). An improvement in the subcritical slope can increase the Ion/Ioff ratio of the associated transistor. This reduces supply voltage and/or power consumption. Manufacturing method 100 or portions thereof may also provide an improvement in Drain-Induced Barrier Lowering (DIBL) of the associated transistor, which may also improve device performance.

Figures 2-3 show a portion of one embodiment of a semiconductor device 200 having a fin 202. The semiconductor device 200 is illustrated as a fin field effect transistor device (eg, a transistor) or any portion thereof (eg, a fin). It is to be noted that FIG. 2 shows only one part of the semiconductor device 200. For example That is, only one quarter or one quarter of the circle of the semiconductor device 200 is displayed (for example, one side of the center line facing the fin 202 and one side of the side line of the center line of the fin), and Its mirroring is not shown. It will be further appreciated that in other embodiments of semiconductor device 200, additional components may be added to semiconductor device 200, and portions of the following components may be replaced or eliminated.

The fin portion 202 includes a passive region 204, a stem region 206, and a passive region 208. A channel of the semiconductor device 200 may be formed in the active region 204. The dry zone 206 as shown may have a width Ws that is less than the width Wa of the active zone 204 and/or the width Wp of the inactive zone 208. The width Wp can be substantially equal to the width Wa. The width Ws may be about 1-99% of the width Wa and/or the width Wp. In one embodiment, the width Ws is about 40-60% of the width Wa and/or the width Wp. In another embodiment, the width of the fins (Wa and/or Wp) may be about 10 nanometers and the width of the dry region Ws may be about 5 nanometers. In yet another example, in one embodiment, the width (Wa and/or Wp) of the fins may be about 6 nanometers, and the width Ws of the dry regions may be about 3 nanometers. In one embodiment, reducing the width Ws by about 50% provides a reduction of about 10 times Ioff.

The illustrated gate structure (and portions thereof) is located on the fin 202 and surrounds it. The gate structure 210 can include a gate dielectric layer 210a and a gate electrode 210b. However, there may be several other layers of film. A source/drain region 212 is formed adjacent the gate structure 210. In one embodiment, the source/drain region 212 is an epitaxial growth semiconductor. An isolation element 214, such as one of shallow trench isolation (STI) elements, is formed adjacent the fin.

It should be noted that in an embodiment, the semiconductor device 200 is not formed on an insulating layer overlying SOI substrate. For example, semiconductor equipment The spacer 200 can be formed on a body (eg, a semiconductor) substrate. In other embodiments, the semiconductor device 200 is formed on an insulating layer overlying SOI substrate.

It is to be noted that the dry zone 204 as shown in Figures 2 and 3 is for illustrative purposes only and is not intended to limit the scope of the invention. For example, other embodiments in accordance with the present invention will be discussed below, and include a dry zone having a reduced width fin material or a width substantially similar to the width of the active and/or inactive regions of the device. A dry area of width.

As previously mentioned, the semiconductor device 200 can have an improvement in performance compared to a conventional fin field effect transistor device having a fixed width fin and/or no dry region. For example, in one embodiment, the formation of a dry zone has the aforementioned effect of reducing Ioff. In another example, in one embodiment, the formation of a dry region improves the saturated sub-threshold voltage slope (SSat). In yet another example, in one embodiment, the formation of a stem improves the drain induced barrier (DIBL).

Referring to FIG. 4, a method 400 of fabricating a fin field effect transistor device (FinFET device) is shown. This fabrication method 400 can be an embodiment of the fabrication method 100 and can be substantially similar to the fabrication method 100 and/or semiconductor device 200 discussed above, which corresponds to the context of Figures 1, 2, and 3. Figures 5, 6, 7, 8, and 9 show cross-sectional views of one or more steps of an exemplary embodiment of a fin field effect transistor (also along the a-a plane) corresponding to fabrication method 400.

Manufacturing method 400 proceeds to step 402 by providing a substrate having at least one epitaxial layer. This substrate can be substantially similar to the above-described case of Figures 1, 2 and/or 3. The substrate may comprise a plurality of film layers, such as a bulk layer having one or more epitaxial layers formed thereon. In an embodiment The main layer and the epitaxial layer have different compositions. For example, in one embodiment, the substrate includes a silicon bulk substrate having a SiGe layer (eg, formed by epitaxial growth or other deposition) deposited thereon. Another semiconductor layer, such as a layer of germanium, may be formed on the germanium layer (eg, formed by epitaxial growth or other deposition). However, the present invention is not limited to the combination of 矽/矽锗. For example, any combination of semiconductor materials can be formed in a multi-film substrate. In one embodiment, the semiconductor material comprises a III-V material. Examples of semiconductor materials include germanium (Ge), germanium (SiGe), germanium carbide (SiGeC), tantalum carbide (SiC), germanium (Si), and/or other suitable materials. As shown below, the criteria for selecting a semiconductor material can include differences in oxidation rate and/or etch rate between the materials used (eg, etch rate/oxidation rate in the active and/or inactive regions of the fin). The difference between the etching/oxidation rate of the dry region of the fin).

Referring to the example shown in FIG. 5, a substrate 502 is first provided. The substrate 502 is a multi-layer substrate. The substrate 502 includes a bulk layer 504, a first layer 506 and a second layer 508. The first layer 506 and/or 508 may be formed by an epitaxial growth process. The first layer 506 can be referred to as a stem-region forming layer. The first layer 506 can have a composition that is different from one of the body layer 504 and/or the second layer 508. The oxidation rate and/or etch rate of the first layer 504 can be different than the oxidation rate and/or etch rate of the second layer 508 and/or the body layer 504. In one embodiment, the first layer 506 includes a composition having an increased etch rate and/or oxidation rate compared to the composition of the body layer 504 and/or the second layer 508. In one embodiment, body layer 504 and second layer 508 comprise substantially similar compositions. In an embodiment, the body layer 504 For 矽, the second layer 508 is 矽 and the first layer 506 is 矽锗 (SiGe). In another embodiment, the body layer 504 and/or the second layer may be suitably doped (eg, P-type germanium).

Manufacturing method 400 then proceeds to step 404 to form one or more fins on the substrate. Such fins can be formed substantially similarly to the above described examples of Figures 1, 2 and/or 3. The fins may each be a multi-layered fin (eg, including a plurality of layers and/or compositions). Referring to an example as shown in FIG. 6, the fins 602 are formed in the substrate 502. The fin 602 includes a body layer 504, a first layer 506, and a second layer 508. The fin 602 can also include a defined active region 604, a stem region 606, and an inactive region 608. These areas will be discussed in detail in the steps below.

Manufacturing method 400 then proceeds to step 406 to form an isolation region adjacent and between the fin structures. This isolation region can be formed substantially similarly to the above described examples of Figures 1, 2 and/or 3. This isolation region can include shallow trench isolation (STI) elements. In one embodiment, the isolation region comprises a dielectric material such as hafnium oxide. In an embodiment, step 406 can be implemented prior to step 404. Referring to the example shown in FIG. 7, an isolation element 214 is disposed on the substrate 502 adjacent to the fin 602. In one embodiment, the spacer element 214 has a top surface that is substantially coplanar with one of the surfaces of the dry region 606. In one embodiment, the isolation element 214 has a top surface that is non-coplanar with one surface of the dry region 606 (eg, below or below it).

Manufacturing method 400 then proceeds to step 408 to form a dry zone within the fin. In an embodiment. The dry zone is formed by etching a dry zone forming region of the fin. In an embodiment, reactive ion etching, wet etching, dry etching, or the like may be employed. And/or a suitable etching process etches the dry region forming region. The etch can form a reduced width at the fin of the dry region (the width of the fin can correspond to the size of the active region of the fin defining the length of the gate). The etching may provide that one of the fin regions has a width that is less than a width of the active region and/or a width of the lower inactive region. Referring to the example shown in FIG. 8, the dry region 606 of the fin is etched (ie, the first layer 506 is etched) such that the width Ws is reduced. In one embodiment, the width Ws can be about 1-99% of the width Wa and/or the width Wp. In one embodiment, the width Ws is about 40-60% of the width Wa and/or the width Wp.

Manufacturing method 400 then proceeds to step 410 where a gate structure is formed on the active region of the fin. The active area of the fin covers the dry area of the fin provided in step 408. This gate structure can be substantially similar to the above described with reference to Figures 1, 2 and 3. In one embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer. Referring to the example of FIG. 9, the gate structure 210 is disposed on the active area of the fin 604. The gate structure 210 includes a gate dielectric layer 210b and a gate electrode layer 210a.

In one embodiment, step 410 includes using a gate last or replacement gate method to form a metal gate structure. In one embodiment, a dummy gate (eg, polysilicon) structure is formed on the fins prior to formation of the dry regions of the fins (eg, by etching at step 408). A portion of the dummy gate structure is then removed, leaving the surrounding spacer and the material of the dielectric material (eg, the interlayer dielectric layer) defining a trench that can be used to form the replacement gate. The removal of the dummy gate (e.g., polysilicon) reveals the underlying fin structure. Referring to step 408, the exposed fins are then etched to form the aforementioned dry regions. A self-aligned etch for etching the dry regions of the fins is thus provided.

Referring to Figure 10, a method 1000 of fabricating a fin field effect transistor device (FinFET device) is shown. The fabrication method 1000 can be an embodiment of the fabrication method 100 and can be substantially similar to the fabrication method 100 and/or semiconductor device 200 discussed above, which corresponds to the context of Figures 1, 2, and 3. Figures 5, 6, 7, 8, 11 and 12 show one of the exemplary embodiments of a fin field effect transistor (also a cross-sectional view along the aa plane in Figure 2) corresponding to one of the fabrication methods 1000 or A cross-sectional view of multiple steps.

Manufacturing method 1000, in step 1002, provides a host semiconductor substrate having a plurality of (eg, two) epitaxial layers formed thereon. Step 1002 can be substantially similar to that of the above-described step 402 of Figure 14 in general similarity. Figure 5 depicts an exemplary embodiment and is as previously described. Manufacturing method 1000 then proceeds to step 1004 to form a fin or fins extending from one of the substrates. The fins include one or several epitaxial layers and a host semiconductor material. Step 1004 can be substantially similar to the above-described step 404 of FIG. Figure 6 shows an exemplary embodiment and is as previously described. Manufacturing method 1000 then proceeds to step 1006 to form an isolation region adjacent and/or between the fin structures. Step 1006 can be substantially similar to the above-described step 406 of FIG. Figure 7 shows an exemplary embodiment and is as previously described.

Manufacturing method 1000 then proceeds to step 1008 to form a dry zone within the fin. Step 1008 can be substantially similar to the above-described step 408 of FIG. Figure 8 depicts an exemplary embodiment and is as previously described. In one embodiment, the dry zone is formed by reducing the width of one of the dry zone forming regions of the fin by referring to the above-described situation illustrated in FIG.

Manufacturing method 1000 then proceeds to step 1010 to oxidize the dry zone. In one embodiment, the dry region is oxidized after referring to the above-described dry region etching process of the above step 1008. In another embodiment, the dry region can be oxidized prior to or prior to etching. In one embodiment, the dry zone includes a ruthenium that can be oxidized to helium oxygen (SiGeO). However, it may also include other compositions such as cerium oxide, SiGeCO, SiCO, GeO, and/or other suitable oxides.

In one embodiment, the dry zone is partially oxidized. FIG. 11 illustrates an embodiment of one of the fins 1102 having an oxidized region 1104 formed by a partial oxidation-dry region 606. Oxidation zone 1104 does not extend through dry zone 606. The dry zone 606 can have a width Ws that is generally similar to the foregoing. In one embodiment, the oxidized region 1104 is SiGeO. However, it may also include other compositions such as cerium oxide, SiGeCO, SiCO, GeO ₂ , and/or other suitable oxides.

In another embodiment, the dry zone is completely oxidized. Figure 12 depicts an embodiment of one of the fins 1202 having one of the substantially dry regions 606. Oxidation zone 1204 extends through dry zone 606. The dry zone 606 can have a width Ws that is generally similar to the foregoing. In one embodiment, the oxidized region 1204 is SiGeO. However, it may also include other compositions such as cerium oxide, SiGeCO, SiCO, GeO ₂ , and/or other suitable oxides.

Manufacturing method 1000 then proceeds to step 1012 to form a gate structure on the active region of the fin. Step 1012 can be substantially similar to the above-described scenario of step 410 of FIG. The active area of the fin covers the dry area of the fin provided by steps 1008 and 1010. Referring to the example shown in FIG. 13, the gate structure 210 is disposed on the active area of the fin 1102. The gate structure 210 includes a gate dielectric layer 210b and a gate electrode layer 210a. It is worth noting that Figure 13 shows the shape A gate structure is formed on the fin 1102. In other embodiments, a substantially similar gate structure including a fully oxidized dry region 606 can be formed on the fin 1202.

In one embodiment, step 1012 includes forming a metal gate in the gate last or replacement gate technique. In one embodiment, a dummy gate (eg, polysilicon) structure is formed on the fins prior to forming or processing the dry regions of the fins (eg, etching and/or oxidation in steps 1008 and/or 1010). A portion of the dummy gate structure is then removed leaving a spacer and dielectric material (eg, an interlayer dielectric layer) on the substrate and defining a trench for forming a replacement gate. The removal of the dummy gate structure reveals the fin structure. The exposed fin structure is then etched and/or oxidized by reference to steps 1008 and/or 1010 described above to form a dry region. This provides a self-aligned process of the dry regions of the fins, such as etching.

In an embodiment as described in the foregoing manufacturing method 1000 and as shown in the seventh, eighth, ninth, eleventh, and twelfth embodiments, the top surface of the isolation region formed between the plurality of fins is substantially coplanar with one of the bottom surfaces of the dry region. . However, other types as described below may also be included.

For example, in other embodiments of step 1006 of fabrication method 1000, an isolation region is formed. The isolation region can be formed and adjacent to the fin such that the isolation structure has a top surface that lies on a plane of the bottom surface of the dry region of the fin. FIG. 14 is an example and illustrates a top surface of an isolation element 1402 having a bottom surface that is located on a first epitaxial layer 506 and a corresponding dry region 606. The spacer element 1402 can be substantially similar to the above-described first, second, and/or third figures. This isolation region can include a shallow trench isolation (STI) structure. In one embodiment, the isolation region comprises a dielectric material such as hafnium oxide.

In such an embodiment, the manufacturing method 1000 then proceeds to the steps 1008, forming a dry zone in the fin. Step 1008 can generally be similar to the foregoing scenario of step 408 of FIG. However, when the isolation region covers one of the sidewalls of the dry region of the fin, one of the dry regions is not etched. FIG. 15 illustrates that the first epitaxial layer 506 is etched to form a dry region 1502. The dry zone 1502 includes a first portion having a width Ws and a second portion having a width Ws2 that may be substantially similar to the width Wp. In an embodiment, the dry zone 1502 can be generally below the center of the second layer 508.

In one embodiment, the fabrication method 1000 then proceeds to step 1010 to oxidize the dry region (having a first portion exposed through the etch and a second portion under the top surface of the isolation structure). Substantially similar to the foregoing with reference to step 1010, in one embodiment, the dry region includes a ruthenium that can be oxidized to helium oxygen (SiGeO). However, it may also include other compositions such as cerium oxide, SiGeCO, SiCO, GeO2, and/or other suitable oxides.

In one embodiment, the dry zone is completely oxidized. Figure 16 shows an embodiment of a fin having one of the complete dry regions 1602. This oxidized zone extends through the width of the dry zone. In one embodiment, the fully oxidized dry zone 1602 can be generally concentrated below the center of the second layer 508.

In one embodiment, the dry zone is partially oxidized. Figure 17 depicts an embodiment of a fin having one of the partially dried regions 1702. This partially oxidized dry region 1702 includes an oxidized material 1704 that does not extend through the dry region (eg, one of the remaining semiconductor materials 506). In one embodiment, the oxidized material 1704 is germanium oxide (SiGeO) and the semiconductor material 506 of the dry region 1702 is germanium. However, it may also include other constituents such as tantalum and niobium oxide, silicon germanium carbide and SiGeCO, tantalum carbide and SiCO, germanium and germanium oxide (GeO), and/or other suitable semiconductors and their oxides. It is noted that the partially oxidized dry zone 1702 can be generally concentrated below the center of the second layer 508.

Manufacturing method 1000 then proceeds to step 1012 to form a gate structure on the active region of the fin. Step 1012 can be generally similar to that described above. It is to be noted that Fig. 13 shows a gate structure formed on the fin 1102. In some embodiments, a substantially similar gate structure is formed on a fin having one of the dry regions of elements 1602 and/or 1702.

An exemplary embodiment as shown in Figures 16 and/or 17 can provide the effect of reducing the capacitance value between the gate structure and the substrate.

Figures 11-17 illustrate several embodiments of a fin field effect transistor device or portions thereof that may be formed using the aforementioned fabrication method 1000 of Figure 10. However, these embodiments are not intended to limit the invention, and may also form other types of fin field effect transistors. For example, different types of dry zones include portions of the dried regions and fins that may be formed, the amount of oxidation, or the like. Figures 18-25 are a few examples, but are not intended to limit the invention. The apparatus of Figures 18-25 can be formed using one or more of the manufacturing methods 1000. The 18a, 19a, 20a, 21a, 22a, 23a, 24a, and 25a are a cross-sectional view (e.g., along the line a-a in Fig. 2). The 18a, 19a, 20a, 21a, 22a, 23a, 24a, and 25a are a cross-sectional view (e.g., along the line b-b in Fig. 2). In other words, it is a cross-sectional view of the fin from the source to the drain.

Please refer to Figures 18a and 18b for a fin field effect transistor (FinFET) 1800. The fin field effect transistor 1800 includes a substrate having a passive region 608 and an active region 604. 502. A stem region 1802 of the fin is disposed between the inactive region 608 and the active region 604. A plurality of isolation elements 1402 are disposed adjacent the fins. The spacer elements 1402 include a top surface that is lower than the top surface of the dry region 1802. The gate structure 210 is disposed over the active region 604 of the fin. The gate structure 210 includes an interface layer 210c, a gate dielectric layer 210a, and a gate electrode layer 210b. In one embodiment, the gate electrode layer 210b is a metal gate electrode. In one embodiment, the gate dielectric layer 210a is a high-k dielectric material. The intermediate layer 210c may comprise a dielectric material such as yttria and or other suitable material. A spacer element 1808 is disposed on a sidewall of the gate structure 210. In one embodiment, the spacers 1808 are dielectric materials such as tantalum nitride, hafnium oxide, hafnium oxynitride, and/or combinations thereof. Such spacers 1808 can be formed by conventional conventional processes including deposition of epitaxial and heteroepitaxial epitaxy and etching including wet etching processes and/or dry etching processes. The spacer material can be separated by physical weather deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure. Chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), and/or other known processes are deposited.

A dielectric layer 1810, also referred to as an interlayer dielectric layer (ILD), is deposited over the substrate. The interlayer dielectric layer 1810 may include, for example, TEOS oxide, un-doped silicon glass, or such as borophosphoquinone glass (BPSG), fused glass (FSG). ), phosphonium glass (PSG), doped silicon oxide of borax glass (BSG), and/or other known materials. The interlayer dielectric layer can be cured by a plasma enhanced chemical vapor deposition (PECVD) Processes or other known techniques are formed.

A source/drain region 212 is disposed adjacent to the gate structure. The source/drain regions 212 can be substantially similar to the previous implementations of Figures 1, 2, and/or 3.

The dry region 1802 of the fin includes an oxidized portion 1804 and a semiconductor material portion 1806. In one embodiment, the oxidized portion 1804 is formed substantially similar to the step 1010 of the fabrication method 1000. (It is worth noting that the dry zone 1802 has a width that is substantially similar to the width of the inactive zone 608 and/or the active zone 604). The oxidized portion 1804 has a thickness t1 of about 5-30 nm. The oxidized portion 1804 extends such that it is below the source/drain region 212. The semiconductor material portion 1806 can be one of the unoxidized portions of the fin portion (eg, the portion of the oxidized portion 1804 can be an oxide of the composition of the semiconductor material portion 1806). In one embodiment, the oxidized portion 1804 is germanium oxide (SiGeOx) and the semiconductor material portion 1806 is germanium. However, it is also possible to combine other semiconductor materials and their oxides.

Referring to Figures 19a and 19b, another embodiment of a fin field effect transistor device 1900 that can be formed using one or more of the foregoing methods of fabrication of the present invention is shown. The fin field effect transistor device 1900 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 1902 of the fin is disposed between the inactive region 608 and the active region 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 1902 of the fin includes an oxidized portion 1904 and a semiconductor material portion 1906. In one embodiment, the oxidized portion 1904 is formed substantially similar to the step 1010 of the fabrication method 1000. The oxidized portion 1904 includes a first portion 1904a having a width Ws and a second portion 1904b having a larger one width Ws2. width Ws can be substantially similar to the aforementioned implementation. Ws2 can be substantially similar to the implementation of Wa and/or Wp described above in Figures 2 and 3. The oxidized portion 1904 has a thickness t1 of about 5-30 nm. The oxidized portion 1904 extends such that it is below the source/drain region 212. The semiconductor material portion 1906 can be one of the unoxidized portions of the fin (eg, the portion of the oxidized portion 1904 can be an oxide of the composition of the semiconductor material portion 1906). In one embodiment, the oxidized portion 1904 is germanium oxide (SiGeOx) and the semiconductor material portion 1906 is germanium. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

Referring to Figures 20a and 20b, another embodiment of a fin field effect transistor device 2000 formed using one or more of the foregoing methods of fabrication of the present invention is shown. The fin field effect transistor device 2000 includes a substrate 502 having an inactive region 608 and an active region 604. A dry zone 2002 of the fin is disposed between the inactive zone 608 and the active zone 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 2002 of the fin includes an oxidized portion 2004 and a semiconductor material portion 2006. In one embodiment, the oxidized portion 2004 is substantially similar to the step 1010 of the method of manufacturing 1000. The oxidized portion 2004 includes a width having a width that is substantially similar to the width of the inactive region 608 and/or the active region 604 of the fin. The semiconductor material portion 2006 may be one of the unoxidized portions of the fins (for example, a portion of the oxidized portion 2004 may be an oxide of a composition of the semiconductor material portion 2006). In one embodiment, the oxidized portion 2004 is germanium oxide (SiGeO) and the semiconductor material portion 2006 is germanium. Oxidation The portion 2004 has a thickness t1 of about 5-30 nm. The oxidized portion 2004 extends such that it is not located below all of the source/drain regions 212. In one embodiment, the oxidized portion 2004 is located only below one of the source/drain regions 212. An oxide (e.g., helium oxygen) is provided under a channel region. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions 212 is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

Referring to Figures 21a and 21b, another embodiment of a fin field effect transistor device 2100 formed using one or more of the foregoing fabrication methods of the present invention is shown. The fin field effect transistor device 2100 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 2102 of the fin is disposed between the inactive region 608 and the active region 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 2102 of the fin includes an oxidized portion 2104 and a semiconductor material portion 2106. In one embodiment, the oxidized portion 2104 is formed substantially similar to the step 1010 of the fabrication method 1000. The oxidized portion 2104 includes a first portion 2104a having a width Ws and a second portion 2104b having a larger one width Ws2. The width Ws can be substantially similar to the aforementioned implementation. Ws2 can be substantially similar to the implementation of Wa and/or Wp described above in Figures 2 and 3. The dry zone 2102 having a difference in thickness can be formed by referring to the method of the foregoing embodiment as shown in Figures 1, 4 and 10. The oxidized portion 2104 has a thickness t1 of about 5-30 nm. The semiconductor material portion 2106 may be one of the unoxidized portions of the fin portion (for example, the portion of the oxidized portion 2104 may be a half An oxide of the composition of the conductor material portion 2106). In one embodiment, the oxidized portion 2104 is germanium oxide (SiGeOx) and the semiconductor material portion 2106 is germanium. The oxidized portion 2104 extends such that it is not located below all of the source/drain regions 212. In one embodiment, the oxidized portion 2104 is located only below one of the source/drain regions 212. An oxide (e.g., helium oxygen) is provided under a channel region. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions 212 is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

Referring to Figures 22a and 22b, another embodiment of a fin field effect transistor device 2200 formed using one or more of the foregoing fabrication methods of the present invention is shown. The fin field effect transistor device 2200 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 2202 of the fin is disposed between the inactive region 608 and the active region 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 2202 of the fin includes an oxidized portion 2204 and a semiconductor material portion 2206. In one embodiment, the oxidized portion 2204 is formed substantially similar to the step 1010 of the fabrication method 1000. The width of the dry region 2202 of the fin may be substantially similar to the width of the active region and/or the inactive region of the dry region. In one embodiment, the oxidized portion 2204 is germanium oxide (SiGeO) and the semiconductor material portion 2206 is germanium. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions 212 is about 5-10 nm. In an embodiment, at the source / The semiconductor material below the bungee zone is 矽.

Referring to Figures 23a and 23b, another embodiment of a fin field effect transistor device 2300 formed using one or more of the foregoing methods of fabrication of the present invention is shown. The fin field effect transistor device 2300 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 2302 of the fin is disposed between the inactive region 608 and the active region 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 2302 of the fin includes an oxidized portion 2304 and a semiconductor material portion 2306. In one embodiment, the oxidized portion 2304 is formed substantially similar to the step 1010 of the fabrication method 1000.

The dry region 2302 of the fin includes a first portion 2302a having a width Ws and a second portion 2302b having a larger one width Ws3. The width Ws3 can be substantially similar to the implementation of the aforementioned width Wa and/or width Wp as in Figures 2 and 3. These different widths can be formed by reference to the dry zone etching process as described in the foregoing embodiments of Figures 1, 4 and 10. The semiconductor material portion 2306 can be an unoxidized portion of the fin (eg, a portion of the oxidized portion 2304 can be an oxide of a composition of the semiconductor material portion 2306). In one embodiment, the oxidized portion 2304 is germanium oxide (SiGeOx) and the semiconductor material portion 2306 is germanium. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions 212 is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

Please refer to Figures 24a and 24b, showing the use of the present invention. Another embodiment of one of the fin field effect transistor devices 2400 formed by one or more of the foregoing fabrication methods. The fin field effect transistor device 2400 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 2402 of the fin is disposed between the inactive region 608 and the active region 604. The isolation element 1402, the gate structure 210, the spacer element 1808, the interlayer dielectric layer 1810, and the source/drain regions 212 can be substantially similar to the foregoing implementations of Figures 18a and 18b.

The dry region 2402 of the fin includes an oxidized portion 2404 and a semiconductor material portion 2406. In one embodiment, the oxidized portion 2404 is formed substantially similar to the step 1010 of the fabrication method 1000. The oxidized portion 2404 includes one width having a width that is substantially similar to the active and/or inactive regions of the fin. The oxidized portion 2404 can have a thickness t1 of between about 5 and 30 nanometers. The oxidized portion 2404 extends such that it is below the source/drain region 212. The semiconductor material portion 2406 can be a portion of the fin that is not oxidized (eg, a portion of the oxidized portion 2404 can be an oxide of a composition of the semiconductor material portion 2406). In one embodiment, the oxidized portion 2404 is germanium oxide (SiGeO) and the semiconductor material portion 2406 is germanium. It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

Referring to Figures 25a and 25b, another embodiment of a fin field effect transistor device 2500 formed using one or more of the foregoing methods of fabrication of the present invention is shown. The fin field effect transistor device 2500 includes a substrate 502 having an inactive region 608 and an active region 604. A dry region 2502 of the fin is disposed between the inactive region 608 and the active region 604. Isolation element 1402, gate structure 210, spacer element 1808, interlayer dielectric layer 1810, and source/drain region 212 The foregoing implementations of Figures 18a and 18b can be generally similar.

The dry region 2502 of the fin includes an oxidized portion 2504 and a semiconductor material portion 2506. In one embodiment, the oxidized portion 2504 is formed substantially similar to the step 1010 of the method 1000. The oxidized portion 2504 includes a width having a width that is substantially similar to the active and/or inactive regions of the fin. The dry zone 2502 can also include one of the aforementioned regions having a narrower width, such as the one shown in FIG. The oxidized portion 2504 extends such that it is below the source/drain region 212. The semiconductor material portion 2506 can be an unoxidized portion of the fin (eg, a portion of the oxidized portion 2504 can be an oxide of a composition of the semiconductor material portion 2506). In one embodiment, the oxidized portion 2504 is germanium oxide (SiGeO) and the semiconductor material portion 2506 is germanium. In the illustrated embodiment, more oxide (e.g., oxidized portion 2504) is formed beneath the source/drain region 212 (e.g., active region 604). It is worth noting that a layer of semiconductor material is located below the source/drain region 212 (e.g., active region 604). In one embodiment, the thickness of the semiconductor material under the source/drain regions is about 5-10 nm. In one embodiment, the semiconductor material underlying the source/drain regions is germanium.

In summary, the above described methods and apparatus of the present invention provide various embodiments for applying to one of the dry regions of one of the fin elements of a fin field effect transistor. It is to be noted that the various embodiments disclosed are susceptible to various implementations, and many changes, substitutions and alterations are made in the embodiments without departing from the scope of the invention.

Accordingly, it will be appreciated that a method of fabricating a semiconductor device is provided in one of the larger embodiments discussed herein. The method includes providing a substrate having a fin extending from a first surface (eg, a top surface). The fin includes A first region having a first composition of semiconductor material and a second region overlying the second composition having a semiconductor material. The second composition is different from the first composition. For example, in one embodiment, the first composition is ruthenium and the second composition is ruthenium. The method is then performed to modify the first region of the fin to reduce the width of one of the first compositions of the semiconductor material. An exemplary method of modifying the first region of the fin includes etching the first region to reduce its width, oxidizing the first region or portion of the first region to reduce a width of the conductive material portion of the first region, And/or other methods. In another embodiment, the method includes etching the first region and oxidizing the first region. The method then continues to form a gate structure on the second region of the fin.

In yet another embodiment, the method continues to form a dummy gate structure on the fin and remove the dummy gate structure to form a trench. The etching of the first region can then be performed by etching the first region located within the trench. This allows self-alignment of a dry zone or a reduction in the width of one of the fins.

In still another embodiment, forming the gate structure includes forming an interface between the gate structure and a top surface of the second region, a first side, a second side, and a bottom surface. Such a gate structure can be referred to as an Omega gate structure or a quasi-surround gate structure. In one embodiment, forming the gate structure includes depositing a gate dielectric material on a sidewall of the first region of the fin. A channel region associated with the gate structure may be formed in the fin. In an embodiment, the channel region is located only in the second region of the fin.

In another broad embodiment, the invention features a method of fabricating a semiconductor device comprising providing a host semiconductor substrate. The bulk semiconductor substrate may include a substrate of a non-insulating layer overlying cerium (SOI) substrate. Then grow one A first epitaxial layer (eg, germanium) is on the main semiconductor substrate, and a second epitaxial layer (eg, germanium) is grown on the first epitaxial layer. Next, forming a fin element including the first epitaxial layer and the second epitaxial layer. The first epitaxial layer of the fin element is then etched to form a dry region having a width less than one of the widths of one of the second epitaxial layers of the fin element. A channel region of a transistor is then formed in the second epitaxial layer of the fin element.

In one embodiment, etching the first epitaxial layer is a selective etch such that the second epitaxial layer is substantially unetched. In one embodiment, the method further includes forming a gate structure on the second epitaxial layer of the fin element, wherein the gate structure contacts at least four surfaces of the second epitaxial layer of the fin element (For example, the bottom surface is included to provide a quasi-surround or Omega gate structure). The method further includes oxidizing the dry region after etching the first epitaxial layer.

In the present invention, a plurality of devices are provided that include a fin field effect transistor having a substrate and a fin disposed on the substrate. The fin includes an inactive area, a dry area on the inactive area, and an active area on the dry area. The dry zone has a first width and the active zone has a second width. The first width is less than the second width. The dry zone has a first width and the active zone has a second width. The first width is less than the second width. The dry zone and the active zone also have different compositions. A gate structure is disposed on the active area.

In one embodiment, the substrate is a bulk semiconductor substrate (eg, a non-insulating layer overlying a germanium substrate). In one embodiment, the gate structure includes a metal gate electrode formed by, for example, a replacement gate technique. In one embodiment, the gate structure contacts a top surface of the active region of the fin, a first side, and a The second side and a bottom surface. Therefore, in an embodiment, the gate structure can be a quasi-surround or Omega gate structure.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Manufacture method

102, 104, 106, 108 ‧ ‧ steps

Claims (5)

A method of fabricating a semiconductor device, comprising: providing a substrate having a fin extending from a first surface, wherein the fin includes a first region of a first composition having a semiconductor material and an overlying semiconductor material a second region of the second composition, wherein the second composition is different from the first composition; modifying the first region of the fin to reduce a quantity of the first composition of the semiconductor material; And forming a gate structure on the second region of the fin, wherein modifying the first region comprises etching a first composition of the semiconductor material in the first region to reduce a width of the first region, And the modifying further comprises oxidizing the first region after the etching. The method of fabricating a semiconductor device according to claim 1, further comprising: forming a dummy gate structure on the fin; and removing the dummy gate structure to form a trench, wherein the etching is performed A zone is performed by etching the first zone located within the trench. The method of fabricating a semiconductor device according to claim 1, wherein the forming the gate structure comprises forming an interface between the gate structure and a top surface of the second region, a first side, and a second side And between the bottom surfaces. A method of manufacturing a semiconductor device, comprising: providing a main semiconductor substrate; growing a first epitaxial layer on the main semiconductor substrate; growing a second epitaxial layer on the first epitaxial layer; Forming a fin element including the first epitaxial layer and the second epitaxial layer; etching the first epitaxial layer of the fin element to form a width of one of the second epitaxial layers having less than the fin element a dry region of one of the widths; and forming a channel region of a transistor in the second epitaxial layer of the fin element, wherein etching the first epitaxial layer into a selective etch, such that the second epitaxial layer The layer is substantially unetched; and after etching the first epitaxial layer, the dry region is oxidized. A fin field effect transistor includes: a substrate; a fin portion disposed on the substrate, wherein the fin portion includes an inactive region, a dry region on the inactive region, and the dry region An active area, wherein the dry area has a first width and the active area has a second width, the first width is less than the second width, and wherein the dry area has a first composition and the active area has a second composition different from the first composition; and a gate structure disposed on the active region, wherein the dry region under the gate structure is at least partially oxidized.