CN114005395A - Image real-time display fault-tolerant system, method and chip - Google Patents
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Abstract
The invention is suitable for the technical field of image display, and provides an image real-time display fault-tolerant system, a method and a chip, wherein the image real-time display fault-tolerant system comprises an image frame processing unit, a display data buffer area, a display time sequence controller and a display fault-tolerant controller, the image frame processing unit is used for sending image data to the display data buffer area in frame units, the display data buffer area is used for caching the image data and pre-caching the image data based on pre-caching action, the display time sequence controller is used for triggering frame resetting action and pre-caching action in a data blanking area of a display time sequence and sending read image data in a data effective area of the display time sequence, the display fault-tolerant controller is used for monitoring whether the data effective area of the display time sequence of the display data buffer area is in an empty state or not in real time, if the data effective area is in the empty state, the display time sequence controller is controlled to start to read the image data from the position of a pixel point of a current pixel point to the front N lines, thereby ensuring the image display effect.
Description
Technical Field
The invention belongs to the technical field of image display, and particularly relates to a fault-tolerant system, a fault-tolerant method and a fault-tolerant chip for image real-time display.
Background
In an image display system, a display image is generally transmitted in units of frames, pixel by pixel, line by line in a display order from left to right, from top to bottom, into a display data buffer, and a display controller reads image data from the display buffer in real time based on a time-series format of resolution and transmits the read image data to an image display apparatus. In the display process of one frame of image, the display time sequence comprises a data effective area and a data blanking area, and the display controller continuously reads data in the display data buffer area in the data effective area and must ensure that the display data buffer area has cache data. If the display data buffer area does not have the buffer data, the display image is torn due to the display dislocation of the subsequent image data. Therefore, fault tolerance processing must be performed for the real-time display system.
The traditional real-time display fault-tolerant method is mainly characterized in that when no cache data exists in a display data buffer area, the last data or random data or previous frame data and the like are used as substitutes of current missing data, the amount of the missing data is counted until the cache data is updated to a certain amount by the data in the data buffer area, the updated data with the same amount of counting is discarded, and then the data is recovered for real-time transmission. However, this method has a certain limitation in engineering application, because when the error occurs, it usually needs a certain time to update the image data, and the new data is buffered while the data is being supplemented, and then the same amount of new data is discarded, which often results in a large amount of supplemented data, and the phenomenon that the display data buffer area does not have buffered data is likely to occur again. In addition, if the last data or random data is adopted as the substitute of the missing data, the effect is not particularly good, and the adoption of the previous frame data has certain difficulty in engineering implementation and is not paid.
Disclosure of Invention
The invention aims to provide a fault-tolerant system, a fault-tolerant method and a fault-tolerant chip for image real-time display, and aims to solve the problem that the existing fault-tolerant technology for real-time display cannot ensure the display effect.
In one aspect, the present invention provides a fault tolerant system for real time display of images, the system comprising:
the image frame processing unit is used for sending the image data to the display data buffer area by taking a frame as a unit;
the display data buffer area is connected with the image frame processing unit and is used for caching the received image data and pre-caching the image data based on a pre-caching action;
the display time sequence controller is connected with the display data buffer area and is used for triggering a frame resetting action and the pre-caching action in a data blanking area of a display time sequence and sending image data read from the display data buffer area in a data effective area of the display time sequence;
and the display fault-tolerant controller is connected with the display data buffer area and is used for monitoring whether the display data buffer area is in an empty state in the data effective area or not in real time, and if the display data buffer area is in the empty state, controlling the display time sequence controller to start to read image data from the pixel point position of the current pixel point position in N lines ahead.
Preferably, the display data buffer area sets a buffer space with M lines of pixel depth in a row unit to pre-buffer the image data, wherein M is greater than or equal to N is greater than or equal to 1, M is a real number, and N is an integer.
Preferably, the display data buffer is a synchronous FIFO memory.
Preferably, an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer, or between the image frame processing unit and the display timing controller, to implement crossing of clock domains.
Preferably, the display fault-tolerant controller is configured to monitor whether the synchronous FIFO memory is in an empty state in the data valid area in real time, and if the synchronous FIFO memory is in the empty state, control the synchronous FIFO memory to skip an N-line-length read address forward, so that the display timing controller starts reading image data from a current read address.
In another aspect, the present invention provides a real-time image fault-tolerant method based on the above real-time image display fault-tolerant system, where the method includes:
the image frame processing unit sends image data to the display data buffer area in a frame unit;
the display data buffer region buffers the received image data;
the display time sequence controller triggers a frame resetting action and a pre-caching action in a data blanking area of a display time sequence so that the display data buffer area pre-caches image data based on the pre-caching action;
and the display fault-tolerant controller monitors whether the display data buffer area is in an empty state in the data effective area of the display time sequence in real time, and if the display data buffer area is in the empty state, the display fault-tolerant controller controls the display time sequence controller to start reading image data from the pixel point position of the current pixel point position in N rows ahead, and sends the read image data.
Preferably, before the display data buffer pre-buffers the image data based on the pre-buffering action, the method includes:
the display data buffer area is used for setting a buffer space with M lines of pixel depth in a line unit to pre-buffer image data, wherein M is more than or equal to N and more than or equal to 1, M is a real number, and N is an integer.
Preferably, the display data buffer is a synchronous FIFO memory.
Preferably, an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer, or between the image frame processing unit and the display timing controller, to implement crossing of clock domains.
In another aspect, the invention also provides a chip, wherein the chip is provided with the image real-time display fault-tolerant system as claimed in any one of claims 1 to 5.
The image real-time display fault-tolerant system provided by the invention comprises an image frame processing unit, a display data buffer area, a display time sequence controller and a display fault-tolerant controller, wherein the image frame processing unit is used for sending image data to the display data buffer area by taking a frame as a unit, the display data buffer area is used for caching the received image data and pre-caching the image data based on a pre-caching action, the display time sequence controller is used for triggering a frame resetting action and a pre-caching action in a data blanking area of a display time sequence and sending the image data read from the display data buffer area in a data effective area of the display time sequence, the display fault-tolerant controller is used for monitoring whether the data effective area of the display time sequence of the display data buffer area is in an empty state or not in real time, and if the data effective area is in the empty state, the display time sequence controller is controlled to read the image data from the pixel point position of the current pixel point position N lines ahead, thereby ensuring the image display effect.
Drawings
FIG. 1A is a schematic structural diagram of a fault-tolerant system for real-time image display according to an embodiment of the present invention;
FIG. 1B is a diagram of an example of a real-time image display fault-tolerant system according to an embodiment of the present invention;
FIG. 1C is a comparison graph of the effect of supplementing 1 line of image data by the fault tolerant system based on the image for real-time display according to an embodiment of the present invention;
FIG. 1D is a comparison graph of the effect of supplementing 2 lines of image data by the fault tolerant system based on the image for real-time display according to an embodiment of the present invention;
FIG. 1E is a comparison graph of the effect of supplementing 1 line of image data twice by the fault tolerant system based on the image in real time according to an embodiment of the present invention; and
fig. 2 is a flowchart illustrating an implementation of a fault-tolerant method for displaying images in real time according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The following detailed description of specific implementations of the present invention is provided in conjunction with specific embodiments:
the first embodiment is as follows:
fig. 1A is a schematic structural diagram of a fault-tolerant system for real-time image display according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, which is detailed as follows:
as shown in fig. 1A, the image real-time display fault-tolerant system includes an image frame processing unit 11, a display data buffer 12, a display timing controller 13 and a display fault-tolerant controller 14, wherein the image frame processing unit, the display timing controller and the display fault-tolerant controller are respectively connected to the display data buffer, the image frame processing unit is used for sending image data to the display data buffer in units of frames, the display data buffer is used for buffering the received image data and pre-buffering the image data based on a pre-buffering action, the display timing controller is used for triggering a frame resetting action and a pre-buffering action in a data blanking area of a display timing sequence and sending the image data read from the display data buffer in a data valid area of the display timing sequence, the display fault-tolerant controller is used for monitoring whether the data valid area of the display timing sequence of the display data buffer is empty or not in real time, and if the current pixel point position is in the empty state, controlling the display time sequence controller to start reading the image data from the pixel point position of the current pixel point position N lines ahead.
In the embodiment of the present invention, the image frame processing unit sequentially transfers the image data to the display data buffer in the order from left to right and from top to bottom in units of frames, and of course, the image data may also perform optimization processing on pixels during the transfer process, and the like, which is not limited herein.
The data buffered by the display data buffer may include a buffer space for buffering the image data, and preferably, the display data buffer sets a buffer space of M lines of pixel depths in units of lines to pre-buffer the image data. Wherein, M is more than or equal to N and more than or equal to 1, M is a real number, and N is an integer. It is noted here that M can be a fraction greater than 1 to improve fault tolerance with less cache cost.
Preferably, the display data buffer is a synchronous FIFO (first in first out) memory to enable pre-buffering of image data. Specifically, the depth of the synchronous FIFO memory is M lines of pixel depth. Considering that the image frame processing unit and the display data buffer may not be in a clock domain, it is preferable that an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer, or between the image frame processing unit and the display timing controller, to implement crossing of the clock domains.
The display time sequence controller mainly realizes the switching control of a data blanking area and a data effective area of various display resolution time sequences, triggers a frame resetting action in the data blanking area of each frame, the frame resetting action is used for clearing the image data remained in the previous frame, triggers a pre-caching action after the frame resetting action is completed and before the display time sequence controller is switched to the data effective area, the pre-caching action is used for indicating the display data buffer area to pre-cache the image data for subsequent fault-tolerant control, and when the display time sequence controller enters the data effective area, the cached image data is read from the display data buffer area and is sent to a display device.
The display fault-tolerant controller is mainly used for error detection and pixel replacement, the display fault-tolerant controller monitors whether a data effective area of a display data buffer area in a display time sequence is in an empty state in real time, if the data effective area is in a non-empty state, image data are read from the display data buffer area and sent, and if the data effective area is in the empty state, the display fault-tolerant controller controls a display time sequence controller to read the image data from the pixel point position of the current pixel point position to the pixel point position of the previous N lines without discarding subsequent image data. Preferably, the display fault-tolerant controller is configured to monitor whether the synchronous FIFO memory is in an empty state in the data valid area in real time, and if the synchronous FIFO memory is in the empty state, control the synchronous FIFO memory to skip forward by a read address of N lines, so that the display timing controller starts reading the image data from the current read address. The continuity between adjacent lines of most application scene images is considered, and the display effect of the images can be ensured. Most importantly, through the mechanism, N lines of display time can be provided for updating the subsequent image data to be displayed, equivalent substitute data does not need to be discarded, the problem that the subsequent image display has the same quality again can be effectively avoided, and the smooth display of one frame of image is effectively ensured.
Fig. 1B is a diagram of an example of an actual application of the image real-time display fault-tolerant system, in fig. 1B, an asynchronous FIFO memory is used to implement the spanning from an image processing domain to an image display domain, a synchronous FIFO memory is used to implement a display data buffer, fault-tolerant processing is performed by monitoring the empty state of the synchronous FIFO memory in real time, and the synchronous FIFO memory is used to read address skip to implement fault-tolerant substitution of image data.
FIG. 1C is a comparison graph of the effect of supplementing 1 line of image data by the fault-tolerant system based on the image real-time display, in FIG. 1C, the left graph is normal display data, and the right graph is empty when reading the 6 th pixel (35) of the 4 th line of the display data buffer, and is supplemented with 1 line of image data; FIG. 1D is a comparison graph of the effect of supplementing 2 lines of image data based on the image real-time display fault-tolerant system, in FIG. 1D, the left graph is normal display data, and the right graph is empty in the display data buffer when the 6 th pixel (35) of the 4 th line is read, and is supplemented with 2 lines of image data; fig. 1E is a comparison graph of the effect of two times of supplementing 1 line of image data based on the image real-time display fault-tolerant system, in fig. 1E, the left graph is normal display data, the right graph shows that the display data buffer area is empty when the 6 th pixel (35) of the 4 th line is read, 1 line of image data is supplemented, and the display data buffer area is empty again when the 4 th pixel (43) of the 7 th line is read, and 1 line of image data is supplemented.
In an embodiment of the present invention, an image real-time display fault-tolerant system includes an image frame processing unit, a display data buffer, a display timing controller and a display fault-tolerant controller, wherein the image frame processing unit is configured to send image data to the display data buffer in units of frames, the display data buffer is configured to buffer the received image data and pre-buffer the image data based on a pre-buffering action, the display timing controller is configured to trigger a frame resetting action and a pre-buffering action in a data blanking area of a display timing and send the image data read from the display data buffer in a data valid area of the display timing, the display fault-tolerant controller is configured to monitor whether the data valid area of the display timing of the display data buffer is empty or not in real time, and if the data valid area is empty, the display timing controller is configured to start reading the image data from a pixel point position N lines ahead of a current pixel point position, thereby ensuring the image display effect.
Example two:
fig. 2 shows an implementation flow of the image real-time display fault-tolerant method provided by the second embodiment of the present invention, and for convenience of description, only the relevant parts of the second embodiment of the present invention are shown, which are detailed as follows:
in step S201, the image frame processing unit transmits image data to the display data buffer in units of frames.
In the embodiment of the present invention, the image frame processing unit sequentially transfers the image data to the display data buffer in the order from left to right and from top to bottom in units of frames, and of course, the image data may also perform optimization processing on pixels during the transfer process, and the like, which is not limited herein.
In step S202, the display data buffer buffers the received image data.
In the embodiment of the present invention, the display data buffer includes a buffer space for buffering the image data, and preferably, the display data buffer sets a buffer space with a depth of M lines of pixels in units of lines to implement pre-buffering of the image data. Wherein, M is more than or equal to N and more than or equal to 1, M is a real number, and N is an integer. It is noted here that M can be a fraction greater than 1 to improve fault tolerance with less cache cost. Preferably, the display data buffer employs a synchronous FIFO (first in first out) memory to achieve pre-buffering of image data. Specifically, the depth of the synchronous FIFO memory is M lines of pixel depth. Considering that the image frame processing unit and the display data buffer may not be in a clock domain, it is preferable that an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer or between the image frame processing unit and the display timing controller to implement crossing of the clock domain.
In step S203, the display timing controller triggers a frame reset operation and a pre-buffer operation in the data blanking region of the display timing, so that the display data buffer pre-buffers the image data based on the pre-buffer operation.
In the embodiment of the invention, a display time sequence controller mainly realizes the switching control of a data blanking area and a data effective area of various display resolution time sequences, triggers a frame resetting action in the data blanking area of each frame, the frame resetting action is used for clearing the image data remained in the previous frame, triggers a pre-buffering action after the frame resetting action is completed and before the display time sequence controller is switched to the data effective area, the pre-buffering action is used for indicating a display data buffer area to buffer M lines of image data for subsequent fault-tolerant control, and the display time sequence controller reads the buffered image data and sends the buffered image data to a display device when entering the data effective area.
In step S204, the display fault-tolerant controller monitors whether the data valid area of the display data buffer in the display time sequence is in an empty state in real time, and if the data valid area is in the empty state, controls the display time sequence controller to start reading the image data from the pixel point position of the current pixel point position N lines ahead, and sends the read image data.
In the embodiment of the invention, the display fault-tolerant controller is mainly used for error detection and pixel replacement, the display fault-tolerant controller monitors whether a data effective area of a display data buffer area in a display time sequence is in an empty state in real time, if the data effective area is in a non-empty state, image data are read from the display data buffer area, the read image data are sent, and if the data effective area is in the empty state, the display fault-tolerant controller is controlled to start to read the image data from pixel point positions of N lines ahead of the current pixel point position without discarding subsequent image data. In other words, the display fault-tolerant controller utilizes a mechanism of supplementing the current lacking data by the image sent line data to resist the display tearing problem caused by the lack and dislocation of the image data, and simultaneously utilizes the mechanism to reserve the line-level cache time and supplement the subsequent image data in time, thereby solving the display problem caused by the untimely transmission of the instantaneous image data. Preferably, the display fault-tolerant controller is configured to monitor whether the synchronous FIFO memory is in an empty state in the data valid area in real time, and if the synchronous FIFO memory is in the empty state, control the synchronous FIFO memory to skip forward by a read address of N lines, so that the display timing controller starts reading the image data from the current read address. The continuity between adjacent lines of most application scene images is considered, and the display effect of the images can be ensured. Most importantly, through the mechanism, N lines of display time can be provided for updating the subsequent image data to be displayed, equivalent substitute data does not need to be discarded, the problem that the subsequent image display has the same quality again can be effectively avoided, and the smooth display of one frame of image is effectively ensured.
In the embodiment of the invention, the image frame processing unit sends the image data to the display data buffer area by taking a frame as a unit, the display data buffer area buffers the received image data, the display time sequence controller triggers a frame resetting action and a pre-buffering action in a data blanking area of a display time sequence so as to enable the display data buffer area to pre-buffer the image data based on the pre-buffering action, the display fault-tolerant controller monitors whether a data effective area of the display time sequence of the display data buffer area is in an empty state in real time, and if the data effective area is in the empty state, the display time sequence controller is controlled to start to read the image data from the pixel point position of a current pixel point position to the N lines ahead, thereby ensuring the image display effect.
Example three:
in an embodiment of the present invention, a chip is provided, where the chip is provided with the image real-time display fault-tolerant system described in the first embodiment.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A fault tolerant system for real time display of images, said system comprising:
the image frame processing unit is used for sending the image data to the display data buffer area by taking a frame as a unit;
the display data buffer area is connected with the image frame processing unit and is used for caching the received image data and pre-caching the image data based on a pre-caching action;
the display time sequence controller is connected with the display data buffer area and is used for triggering a frame resetting action and the pre-caching action in a data blanking area of a display time sequence and sending image data read from the display data buffer area in a data effective area of the display time sequence;
and the display fault-tolerant controller is connected with the display data buffer area and is used for monitoring whether the display data buffer area is in an empty state in the data effective area or not in real time, and if the display data buffer area is in the empty state, controlling the display time sequence controller to start to read image data from the pixel point position of the current pixel point position in N lines ahead.
2. The system of claim 1, wherein the display data buffer sets a buffer space of M lines of pixel depth in units of lines to pre-buffer the image data, wherein M ≧ N ≧ 1, M is a real number, and N is an integer.
3. The system of claim 1, wherein the display data buffer is a synchronous FIFO memory.
4. The system of claim 3, wherein an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer or between the image frame processing unit and the display timing controller to enable clock domain crossing.
5. The system as claimed in claim 3, wherein the display fault-tolerant controller is configured to monitor whether the synchronous FIFO memory is empty in the data valid area in real time, and if so, control the synchronous FIFO memory to skip forward by N-line length read addresses, so that the display timing controller reads image data from a current read address.
6. A real-time image fault-tolerant method based on the real-time image display fault-tolerant system of any one of claims 1-5, wherein the method comprises:
the image frame processing unit sends image data to the display data buffer area in a frame unit;
the display data buffer region buffers the received image data;
the display time sequence controller triggers a frame resetting action and a pre-caching action in a data blanking area of a display time sequence so that the display data buffer area pre-caches image data based on the pre-caching action;
and the display fault-tolerant controller monitors whether the display data buffer area is in an empty state in the data effective area of the display time sequence in real time, and if the display data buffer area is in the empty state, the display fault-tolerant controller controls the display time sequence controller to start reading image data from the pixel point position of the current pixel point position in N rows ahead, and sends the read image data.
7. The method of claim 6, wherein the display data buffer, prior to pre-buffering image data based on the pre-buffering action, comprises:
the display data buffer area is used for setting a buffer space with M lines of pixel depth in a line unit to pre-buffer image data, wherein M is more than or equal to N and more than or equal to 1, M is a real number, and N is an integer.
8. The method of claim 6, wherein the display data buffer is a synchronous FIFO memory.
9. The method of claim 6, wherein an asynchronous FIFO memory is included between the image frame processing unit and the display data buffer or between the image frame processing unit and the display timing controller to enable clock domain crossing.
10. A chip provided with a fault tolerant system for real time display of images according to any of claims 1-5.
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