CN111383609A - Time sequence control method, time sequence controller and display device - Google Patents
Time sequence control method, time sequence controller and display device Download PDFInfo
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- CN111383609A CN111383609A CN201811644451.3A CN201811644451A CN111383609A CN 111383609 A CN111383609 A CN 111383609A CN 201811644451 A CN201811644451 A CN 201811644451A CN 111383609 A CN111383609 A CN 111383609A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention relates to a time sequence control method, a time sequence controller and a display device, wherein the method comprises the following steps: s1: sequentially outputting pixel voltage data of each row of pixel units in the current frame image; s2: reading and latching pixel voltage data of any row of pixel units in the current frame image; s3: and collecting pixel voltage data of the pixel units in any row, and outputting the data in a field blanking area between frames. The time sequence control method and the time sequence controller of the invention increase the high frequency signal with the frequency close to the display area in the vertical blanking area through the preset time sequence control instruction, thereby avoiding the generation of noise caused by the high and low frequency switching of the signal when the display area is switched with the vertical blanking area, and the picture display of the liquid crystal panel is not influenced because the picture is not displayed in the vertical blanking area. In addition, the noise caused by the switching of high and low frequencies of the signals can be eliminated without replacing components or adding a new pin design and only by performing time sequence adjustment in the original signals, and the cost cannot be increased.
Description
Technical Field
The invention belongs to the technical field of liquid crystal panels, and particularly relates to a time sequence control method, a time sequence controller and a display device.
Background
The conventional liquid crystal display panel generally includes a Timing Controller (TCON), a source Driver (source Driver), and a Gate Driver (Gate Driver), wherein the Timing Controller (TCON) mainly processes each frame of image data to generate a data signal and a control signal corresponding to each frame of image data, the control signal includes an output enable signal (OE1) for controlling the Gate Driver to output a Gate (Gate) signal, the Gate (Gate) signal is at a low voltage when the output enable signal (OE1) is at a high level, the Gate (Gate) signal is at a high voltage when the output enable signal (OE1) is at a low level, and the source Driver converts the received data signal into a data voltage to be written into a corresponding pixel on the liquid crystal display panel when the data signal is transmitted to the source Driver.
In the process of displaying on the liquid crystal display panel, after the transmission of each frame of image data is finished, a field blanking (V blanking) area exists between the current frame and the next frame of signals. Generally, effective image data is transmitted in a display area, the signal frequency can reach several hundred megahertz, image data is not transmitted in a field blanking area, and the image data is a low-frequency signal, so that when the display area is switched to the field blanking area, the signal frequency is obviously reduced, and capacitance or inductance on a printed circuit board (printed circuit board) can generate a delicate hum, generate noise, and influence the customer experience and the product taste.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a timing control method, a timing controller and a display device. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a time sequence control method, which comprises the following steps:
s1: sequentially outputting pixel voltage data of each row of pixel units in the current frame image;
s2: reading and latching pixel voltage data of any row of pixel units in the current frame image;
s3: and collecting pixel voltage data of the pixel units in any row, and outputting the data in a field blanking area between frames.
In an embodiment of the present invention, the step S3 further includes:
s4: and when the output of the signals of the field blanking area is finished, sequentially outputting the pixel voltage data of each row of pixel units in the next frame of image.
In an embodiment of the present invention, the S1 includes:
s11: receiving first pixel voltage data of a first row of pixel units in the current frame image;
s12: latching the first pixel voltage data;
s13: collecting pixel voltage data of the first row of pixel units and outputting the pixel voltage data to a source driver;
s14: receiving second pixel voltage data of a second row of pixel cells in the current frame image, and repeating S12 and S13 until pixel voltage data of a last row of pixel cells of the current frame image is output to the source driver.
In an embodiment of the present invention, the S11 further includes:
reserving a set time, wherein the set time is equal to the output time of the pixel voltage data of the pixel units of a plurality of rows.
In an embodiment of the present invention, the S2 includes:
and when the pixel voltage data of the last row of pixel units in the current frame image is output, reading and latching the pixel voltage data of the last row of pixel units in the current frame image.
In an embodiment of the present invention, the S3 includes:
and collecting the pixel voltage data of the last row of pixel units, and repeatedly outputting the pixel voltage data of the last row of pixel units in the field blanking area.
The present invention also provides a timing controller, comprising:
the time sequence setting module is used for setting and storing a time sequence control instruction;
the latch module is used for receiving and latching the pixel voltage data of each row of pixel units in the current frame image according to the time sequence control instruction and receiving and latching the pixel voltage data output in the vertical blanking area according to the time sequence control instruction;
and the acquisition output module is used for acquiring and outputting the pixel voltage data in the latch module according to the time sequence control instruction.
In an embodiment of the present invention, the timing control instruction includes a first timing control instruction and a second timing control instruction, where the first timing control instruction is used to control normal display of a current frame image, and the second timing control instruction is used to control signal output of a field blanking region between frames.
In an embodiment of the present invention, the pixel voltage data output in the vertical blanking area includes pixel voltage data of any row of pixel units in the current frame image.
The invention also provides a display device comprising the timing controller according to any one of the above embodiments.
Compared with the prior art, the invention has the beneficial effects that:
1. the time sequence control method and the time sequence controller of the invention increase the high frequency signal with the frequency close to the display area in the vertical blanking area through the preset time sequence control instruction, thereby avoiding the generation of noise caused by the high and low frequency switching of the signal when the display area is switched with the vertical blanking area, and the picture display of the liquid crystal panel is not influenced because the vertical blanking area does not display the picture.
2. The time sequence control method and the time sequence controller of the invention do not need to replace components or add new pin designs, and only carry out time sequence adjustment in the original signals, thus eliminating the noise caused by the switching of high and low frequencies of the signals without increasing the cost.
Drawings
FIG. 1 is a flow chart of a timing control method according to an embodiment of the present invention;
FIG. 2a is a timing diagram of a timing control method according to an embodiment of the present invention;
FIG. 2b is an enlarged view of area A in FIG. 2 a;
FIG. 3 is a timing diagram of another timing control method according to an embodiment of the present invention;
FIG. 4 is a timing diagram of another timing control method according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a timing controller according to an embodiment of the present invention.
Detailed Description
The present disclosure is further described with reference to specific examples, but the embodiments of the present disclosure are not limited thereto. Referring to fig. 1, fig. 1 is a flowchart illustrating a timing control method according to an embodiment of the present invention, where the timing control method includes:
s1: sequentially outputting pixel voltage data of each row of pixel units in the current frame image;
s2: reading and latching pixel voltage data of any row of pixel units in the current frame image;
s3: and collecting pixel voltage data of the pixel units in any row, and outputting the data in a field blanking area between frames.
Further, after the S3, the method further includes:
s4: and when the output of the signals of the field blanking area is finished, sequentially outputting the pixel voltage data of each row of pixel units in the next frame of image.
Specifically, the S1 includes:
s11: receiving first pixel voltage data of a first row of pixel units in the current frame image;
s12: latching the first pixel voltage data;
s13: collecting pixel voltage data of the first row of pixel units and outputting the pixel voltage data to a source driver;
s14: receiving second pixel voltage data of a second row of pixel cells in the current frame image, and repeating S12 and S13 until pixel voltage data of a last row of pixel cells of the current frame image is output to the source driver.
Specifically, the S2 includes:
and when the pixel voltage data of the last row of pixel units in the current frame image is output, reading and latching the pixel voltage data of the last row of pixel units in the current frame image.
Specifically, the S3 includes:
and collecting the pixel voltage data of the last row of pixel units, and repeatedly outputting the pixel voltage data of the last row of pixel units in the field blanking area.
Example one
Referring to fig. 2a and fig. 2b, fig. 2a is a timing diagram of a timing control method according to an embodiment of the invention, and fig. 2b is an enlarged view of an area a in fig. 2 a. As shown in fig. 2a and 2b, the internal valid data (internal DE) is a control signal built in the Timing Controller (TCON), wherein a high level indicates valid pixel voltage data. The TP is a latch module, the rising of the TP represents latching pixel voltage data, the falling represents outputting the pixel voltage data to a memory latch in the time sequence controller, and the low-voltage differential signal interface mini-LVDS is an acquisition output module which is used for acquiring the pixel voltage data in the memory latch and outputting the pixel voltage data to a source driver.
Generally, a frame of image is represented by 1frame in the timing diagram, and a line of display is terminated when the display pointer is displayed from the first pixel point in the first row of the upper left corner of the display panel until the last pixel point in the upper right corner of the display panel, and this line of display is represented by 1line in the timing diagram.
In this embodiment, referring to fig. 2a and fig. 2b, the timing control process of the nth frame image (N frame) is taken as an example to illustrate the timing control method according to the embodiment of the present invention. The time sequence control method comprises the following steps:
step 1: outputting the Nth frame of image data to a time sequence controller;
step 2: the latch module TP in the timing controller receives and latches the first pixel voltage data D1 of the pixel unit in the first row of the nth frame image, and stores it in the memory latch;
and step 3: the low-voltage differential signaling interface mini-LVDS collects first pixel voltage data D1 stored in the memory lock latch and outputs the first pixel voltage data D1 to the source electrode driver;
and 4, step 4: the latch module TP receives and latches the second pixel voltage data D2 of the pixel units in the second row of the nth frame image, and stores the data into the memory latch;
and 5: the low-voltage differential signal interface mini-LVDS collects second pixel voltage data D2 stored in the memory lock latch and outputs the second pixel voltage data D2 to the source electrode driver;
step 6: repeating the step 2 to the step 3 until the latch module TP receives and latches the last row of pixel voltage data D2160 of the last row (last line) of pixel units of the image of the nth frame and stores the data into the memory lock latch, and the low voltage differential signaling interface mini-LVDS collects the last row of pixel voltage data D2160 stored in the memory lock latch and outputs the data to the source driver, and the image of the nth frame is completely output;
and 7: the low-voltage differential signal interface mini-LVDS collects the last row of pixel voltage data D2160 stored in the memory lock latch and repeatedly outputs the data in the vertical blanking area;
specifically, the nth frame image enters the vertical blanking area after being output, the last row of pixel voltage data D2160 is stored in the memory lock latch in step 6, and the memory state is still maintained after entering the vertical blanking area, at this time, the last row of pixel voltage data D2160 stored in the memory lock latch is collected through the low voltage differential signaling interface mini-LVDS, and is repeatedly output in the vertical blanking area until the vertical blanking area is finished.
And 8: and when the output of the vertical blanking interval signal is finished, outputting the pixel voltage data of the (N + 1) th frame image to the source driver according to the steps.
In this embodiment, the data repeatedly written in the vertical blanking region is derived from the last row of pixel voltage data D2160 in the normal display data stored in the memory lock latch, and the frequency of repeated writing can be adjusted by setting the timing control command without additionally manufacturing a new signal.
Preferably, the pixel voltage data of the row pixel units repeatedly written in the field blanking area has the same frequency as the pixel voltage data of the row pixel units in the image display area.
Example two
Fig. 3 is a timing diagram of another timing control method according to an embodiment of the invention. As shown in the figure, in the present embodiment, the steps of the timing control method are as follows:
step 1: outputting the Nth frame of image data to a time sequence controller;
step 2: the latch module TP in the timing controller receives and latches the first pixel voltage data D1 of the pixel unit in the first row of the nth frame image, and stores it in the memory latch;
and step 3: the low-voltage differential signaling interface mini-LVDS collects first pixel voltage data D1 stored in the memory lock latch and outputs the first pixel voltage data D1 to the source electrode driver;
and 4, step 4: repeating the step 2 to the step 3 until the latch module TP receives and latches the last row of pixel voltage data D2160 of the last row (last line) of pixel units of the image of the nth frame and stores the data into the memory lock latch, and the low voltage differential signaling interface mini-LVDS collects the last row of pixel voltage data D2160 stored in the memory lock latch and outputs the data to the source driver, and the image of the nth frame is completely output;
and 5: after the nth frame image is output, the nth frame image enters a field blanking area, and the latch module TP receives and latches mth row pixel voltage data Dm of mth row pixel units of the nth frame image and stores the mth row pixel voltage data Dm into a memory latch;
step 6: the low-voltage differential signal interface mini-LVDS collects the pixel voltage data Dm of the mth row stored in the memory lock latch and repeatedly outputs the pixel voltage data Dm in the vertical blanking area;
it should be noted that the mth row of pixel voltage data Dm is pixel voltage data of any row of pixel units in the nth frame image, and is not limited to the last row of pixel voltage data D2160. That is, in the vertical blanking region, by setting the timing control command, the pixel voltage data of the pixel unit of an arbitrary row can be repeatedly output.
And 7: and when the signal output of the vertical blanking area is finished, outputting the pixel voltage data of the image of the (N + 1) th frame to the source driver.
Further, the S11 is preceded by:
reserving a set time, wherein the set time is equal to the output time of the pixel voltage data of the pixel units of a plurality of rows.
For the display panel including the GOA driving circuit, since it takes time to charge the GOA driving circuit, a set time equal to an output time of pixel voltage data of several rows of pixel units is reserved, so the display panel of the GOA driving circuit delays the output of the pixel voltage data of several rows of pixel units.
EXAMPLE III
Referring to fig. 4, fig. 4 is a timing diagram of another timing control method of the display panel including the GOA driving circuit according to the embodiment of the present invention, where dellay represents pixel voltage data of delayed output.
In this embodiment, the steps of the timing control method are as follows:
step 1: delaying the output time of pixel voltage data of four rows of pixel units;
step 2: a latch module TP in the time schedule controller receives and latches first pixel voltage data D1 of a first row of pixel units of an N frame image and stores the first pixel voltage data into a memory lock latch, and a low differential signal interface mini-LVDS acquires the first pixel voltage data D1 stored in the memory lock latch and outputs the first pixel voltage data to a source driver;
and step 3: repeating the step 2 until the latch module TP receives and latches the last row of pixel voltage data D2160 of the last row (lastline) of pixel units of the nth frame image and stores the data into the memory lock latch, and the low-voltage differential signal interface mini-LVDS collects the last row of pixel voltage data D2160 stored in the memory lock latch and outputs the data to the source driver, and the nth frame image is completely output;
and 4, step 4: after the nth frame image is output, entering a vertical blanking area, and in the same step 7 of the first embodiment, repeatedly outputting the last line of pixel voltage data D2160 of the nth frame image in the vertical blanking area until the vertical blanking area is finished;
it should be noted that, in step 4, that is, after the nth frame image is output, the image enters the vertical blanking area, which may be similar to steps 5 to 6 of the second embodiment, the pixel data of any row of pixel units of the nth frame image is repeatedly output in the vertical blanking area, not limited to the last row of pixel voltage data D2160, until the vertical blanking area is finished.
And 5: and when the output of the vertical blanking interval signal is finished, outputting the pixel voltage data of the (N + 1) th frame image to the source driver according to the steps.
The timing control method of the embodiment adds the high-frequency signal with the frequency close to that of the display area in the vertical blanking area through the preset timing control instruction, thereby avoiding the generation of noise caused by the high-frequency and low-frequency switching of the generated signal when the display area is switched with the vertical blanking area, and not influencing the picture display of the liquid crystal panel because the picture is not displayed in the vertical blanking area.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a timing controller according to an embodiment of the present invention, and as shown in the drawing, the timing controller according to the embodiment includes:
the time sequence setting module 1 is used for setting and storing a time sequence control instruction;
specifically, the timing control instruction includes a first timing control instruction and a second timing control instruction, where the first timing control instruction is used to control normal display of a current frame image, and the second timing control instruction is used to control signal output of a vertical blanking region between frames.
The latch module 2 is used for receiving and latching the pixel voltage data of each row of pixel units in the current frame image according to the time sequence control instruction, and is used for receiving and latching the pixel voltage data output in the vertical blanking area according to the time sequence control instruction;
the pixel voltage data output by the vertical blanking area comprises pixel voltage data of any row of pixel units in the current frame image.
And the acquisition output module 3 is used for acquiring and outputting the pixel voltage data in the latch module according to the time sequence control instruction.
Specifically, in the normal display process of the image, the timing setting module 1 sends a first timing instruction, the latch module 2 latches pixel voltage data of each row of pixel units of the current frame image, and the acquisition and output module 3 acquires the latched pixel voltage data according to the first timing control instruction and outputs the acquired pixel voltage data to the source driver. In the vertical blanking area, the timing setting module 1 sends out a second timing instruction, the latch module 2 latches pixel voltage data of any row of pixel units of the previous frame of image, and the acquisition and output module 3 acquires the latched pixel voltage data of any row of pixel units of the previous frame of image according to the second timing control instruction and outputs the data in the vertical blanking area.
The embodiment of the invention also provides a display device which comprises the time sequence controller.
The time sequence control method and the time sequence controller of the invention do not need to replace components or add new pin designs, and only carry out time sequence adjustment in the original signals, thus eliminating the noise caused by the switching of high and low frequencies of the signals and not increasing the cost.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions may be made without departing from the spirit of the invention, which should be construed as belonging to the scope of the invention.
Claims (10)
1. A timing control method, comprising:
s1: sequentially outputting pixel voltage data of each row of pixel units in the current frame image;
s2: reading and latching pixel voltage data of any row of pixel units in the current frame image;
s3: and collecting pixel voltage data of the pixel units in any row, and outputting the data in a field blanking area between frames.
2. The timing control method according to claim 1, further comprising, after the S3:
s4: and when the output of the signals of the field blanking area is finished, sequentially outputting the pixel voltage data of each row of pixel units in the next frame of image.
3. The timing control method according to claim 1, wherein the S1 includes:
s11: receiving first pixel voltage data of a first row of pixel units in the current frame image;
s12: latching the first pixel voltage data;
s13: collecting pixel voltage data of the first row of pixel units and outputting the pixel voltage data to a source driver;
s14: receiving second pixel voltage data of a second row of pixel cells in the current frame image, and repeating S12 and S13 until pixel voltage data of a last row of pixel cells of the current frame image is output to the source driver.
4. The timing control method according to claim 3, further comprising, before the step S11:
reserving a set time, wherein the set time is equal to the output time of the pixel voltage data of the pixel units of a plurality of rows.
5. The timing control method according to claim 1, wherein the S2 includes:
and when the pixel voltage data of the last row of pixel units in the current frame image is output, reading and latching the pixel voltage data of the last row of pixel units in the current frame image.
6. The timing control method according to claim 5, wherein the step S3 includes:
and collecting the pixel voltage data of the last row of pixel units, and repeatedly outputting the pixel voltage data of the last row of pixel units in the field blanking area.
7. A timing controller, comprising:
the time sequence setting module is used for setting and storing a time sequence control instruction;
the latch module is used for receiving and latching the pixel voltage data of each row of pixel units in the current frame image according to the time sequence control instruction and receiving and latching the pixel voltage data output in the vertical blanking area according to the time sequence control instruction;
and the acquisition output module is used for acquiring and outputting the pixel voltage data in the latch module according to the time sequence control instruction.
8. The timing controller according to claim 7, wherein the timing control instructions comprise a first timing control instruction for controlling normal display of a current frame image and a second timing control instruction for controlling signal output of a field blanking region between frames.
9. The timing controller of claim 8, wherein the pixel voltage data outputted from the vertical blanking region comprises pixel voltage data of any row of pixel units in a current frame image.
10. A display device comprising the timing controller according to any one of claims 7 to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114005395A (en) * | 2021-10-11 | 2022-02-01 | 珠海亿智电子科技有限公司 | Image real-time display fault-tolerant system, method and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5699076A (en) * | 1993-10-25 | 1997-12-16 | Kabushiki Kaisha Toshiba | Display control method and apparatus for performing high-quality display free from noise lines |
| CN101452683A (en) * | 2007-12-05 | 2009-06-10 | 联咏科技股份有限公司 | Electric voltage generating system |
| CN101727810A (en) * | 2008-10-16 | 2010-06-09 | 索尼株式会社 | Drive circuit for display panel, display panel module, display device, and method for driving display panel |
| CN103258511A (en) * | 2012-02-20 | 2013-08-21 | 乐金显示有限公司 | Timing controller and liquid crystal display device comprising same |
| CN103377628A (en) * | 2012-04-30 | 2013-10-30 | 乐金显示有限公司 | Liquid crystal display and method of driving the same |
| KR20180078996A (en) * | 2016-12-30 | 2018-07-10 | 엘지디스플레이 주식회사 | Circuit for driving data of the display device |
-
2018
- 2018-12-29 CN CN201811644451.3A patent/CN111383609A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5699076A (en) * | 1993-10-25 | 1997-12-16 | Kabushiki Kaisha Toshiba | Display control method and apparatus for performing high-quality display free from noise lines |
| CN101452683A (en) * | 2007-12-05 | 2009-06-10 | 联咏科技股份有限公司 | Electric voltage generating system |
| CN101727810A (en) * | 2008-10-16 | 2010-06-09 | 索尼株式会社 | Drive circuit for display panel, display panel module, display device, and method for driving display panel |
| CN103258511A (en) * | 2012-02-20 | 2013-08-21 | 乐金显示有限公司 | Timing controller and liquid crystal display device comprising same |
| CN103377628A (en) * | 2012-04-30 | 2013-10-30 | 乐金显示有限公司 | Liquid crystal display and method of driving the same |
| KR20180078996A (en) * | 2016-12-30 | 2018-07-10 | 엘지디스플레이 주식회사 | Circuit for driving data of the display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114005395A (en) * | 2021-10-11 | 2022-02-01 | 珠海亿智电子科技有限公司 | Image real-time display fault-tolerant system, method and chip |
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Application publication date: 20200707 |
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