CN101777313B - Driving method and device of liquid crystal display panel and time controller of liquid crystal display panel - Google Patents
Driving method and device of liquid crystal display panel and time controller of liquid crystal display panel Download PDFInfo
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Abstract
The invention discloses a driving method and device of a liquid crystal display (LCD) panel and a time controller of the LCD panel, aiming to eliminate image blur while not changing the commercial standard driver, in particular eliminate sample and hold artifact. The time controller of the invention is used to control a plurality of source drivers and gate drivers on a LCD panel module. The time controller of the invention contains a data processing module and a control signal generating module, wherein the data processing module is used to generate a data signal containing image data and black data; and the control signal generating module is used to generate a plurality of initial level signals, a first gate activating signal and a second gate activating signal, wherein the initial level signal series is used to input the data signal in the source drivers, the first gate activating signal and the second gate activating signal correspond to different activating times, and the first gate activating signal and the second gate activating signal are selectively output to the gate drivers.
Description
Technical field
The present invention relates to keep the settling mode of the movable image fuzzy (motion image blur) of type display device (hold type display device), refer to a kind of driving method and device and relevant time controller of liquid crystal panel especially.
Background technology
For keeping type display device (hold type display device); For example: active matrix liquid crystal display (active matrix liquid crystal display; AMLCD), movable image fuzzy (motion image blur) is the subject under discussion for coming into question widely.The origin cause of formation that movable image is fuzzy comprises: slow excessively liquid crystal reaction time, the capacitance variations of pixel and so-called " take a sample and keep false shadow " (sampleand hold artifact).
According to known techniques, the above two all can be by utilizing voltage overdrive methods such as (voltage overdrive) to solve.Yet; The latter is owing to be sampling characteristic and the user's of these active matrix liquid crystal display the level and smooth combination of moving trace (smooth motion tracking) characteristic of vision system; Be difficult for handling, so still be present in LCD on the market widely.In the known techniques about sampling with keep the solution and the imperfection of false shadow.For example in a convention solution, be to destroy visual sense of continuity, in the hope of destroying sampling and the effect of keeping false shadow by the data that off and on data of overall image are substituted by full shadow picture.Yet this convention solution has the image brilliance problem of deepening significantly.
In addition, the solution that known techniques provided often needs quite complicated controlling mechanism and expends quite high research and development or manufacturing cost, therefore is unfavorable for importing product on the market.
Summary of the invention
Technical matters to be solved by this invention provides a kind of driving method of liquid crystal panel and the time controller of device and liquid crystal panel, can get off to eliminate image fog in the situation of not changing commercially available standard drive, especially eliminates sampling and keeps false shadow.
In order to solve above technical matters, the invention provides following technical scheme:
The present invention provides a kind of driving method, and in order to drive a liquid crystal panel module, this liquid crystal panel module has plural source electrode driver.Driving method of the present invention includes: produce a data signals that is loaded with image data and black data; A plurality of horizontal start signals are provided, and each of these horizontal start signals has one first pulse signal and one second pulse signal; According to these first pulse signals, this image data is loaded on these source electrode drivers in regular turn; According to these second pulse signals, this black data is loaded on these source electrode drivers; One data load signal is provided, and this data load signal has one the 3rd pulse signal and one the 4th pulse signal; According to the 3rd pulse signal, the image data output that these source electrode drivers will load; And according to the 4th pulse signal, the black data output that these source electrode drivers will load.
The present invention provides a kind of drive unit, and in order to drive a liquid crystal panel, it includes: plural source electrode driver, in order to drive the plural source electrode line of this liquid crystal panel; The plural number gate pole driver is in order to drive the plural gate line of this liquid crystal panel; And a time controller, in order to produce plural horizontal start signal, one first gate enable signal and one second gate enable signal, wherein, these horizontal start signals systems are exported to these source electrode drivers respectively; This first gate enable signal and this second gate enable signal are the corresponding different activation time, and are optionally exported to these gate pole drivers.
The present invention also provides a kind of time controller, and in order to control plural source electrode driver and the plural gate pole driver on the liquid crystal panel module, it includes: a data processing module is used for producing a data signals that is loaded with image data and black data; And a control signal generating module, in order to produce plural horizontal start signal, one first gate enable signal and one second gate enable signal, wherein, these horizontal start signals systems are in order to be loaded on these source electrode drivers with this data signals; This first gate enable signal and this second gate enable signal are the corresponding different activation time, and are optionally exported to these gate pole drivers.
The driving method of the liquid crystal panel that the present invention adopts and the time controller of device and liquid crystal panel; Can be under the situation of not changing commercially available standard drive; Insert and eliminate image fog by the time control of the driver of liquid crystal panel being carried out black-tape, especially eliminate sampling and keep false shadow.
Description of drawings
Fig. 1 is the synoptic diagram of the drive unit of a kind of liquid crystal panel of being provided according to the present invention one first embodiment.
Fig. 2 is the synoptic diagram according to the time controller that one embodiment of the invention provided.
Fig. 3 is the sequential chart according to signal relevant with horizontal direction in the driving method that one embodiment of the invention provided.
Fig. 4 is the sequential chart of signal relevant with vertical direction among the embodiment shown in Figure 3.
Fig. 5 is the functional block diagram of a driver.
Fig. 6 shows the synoptic diagram of black for showing liquid crystal panel 10 part show images and part.
Fig. 7 is an embodiment synoptic diagram of data processing module among Fig. 2.
Fig. 8 is the synoptic diagram of an embodiment of control signal generating module among Fig. 2.
Fig. 9 is the synoptic diagram of an embodiment of control signal generating module 810 among Fig. 8.
Fig. 1 is to be the synoptic diagram of an embodiment of output switch unit 870 among Fig. 8.
Figure 11 is the synoptic diagram of the drive unit of a kind of liquid crystal panel of being provided according to the present invention one second embodiment.
Figure 12 is the sequential chart of signal relevant with vertical direction among the embodiment shown in Figure 11.
[primary clustering symbol description]
10 liquid crystal panels, 100,200 drive units
110,210 time controllers, 112 data processing modules
114 control signal generating module
120-1～120-R, 220-1～220-4 source electrode driver
130-1～130-m, 230-1～230-4 gate pole driver
140,150 RCAs, 510 translation buffers
530 accurate translation circuit of 520 line breech locks
540 digital analog converters, 550 output buffers
710,871,872,905,909 multiplexers
810,820,830,840,850,860 control signal generating unit
870 output switch units, 873 phase inverters
901,902 counters, 903,907 comparers
904 or logic lock 906 D type flip-flops
Vin input image signal CLKH, the CLKV frenquency signal
DATA data signals DATA0 source book
OE-1, OE-2, OE-3, OE-4, OE_UP, OE_DN gate enable signal
OE
HThe activation time of gate enable signal
OEB is corresponding to the gate enable signal of black data
OED is corresponding to the gate enable signal of image data
P
B1, P
B2, P
B3... The horizontal initial pulse of black data
P
D1, P
D2, P
D3... The horizontal initial pulse of image data
The output data of SD.OUT source electrode driver
The horizontal start signal of STH-1～STH-R
The vertical start signal of STV
STV
BThe vertical initial pulse of black data
STV
DThe vertical initial pulse of image data
T
INVThe time interval between the horizontal line image data
T
SDThe operation period of single source electrode driver
TP data load signal
TP
BThe black data load pulses
TP
DThe image data load pulses
Embodiment
Please refer to Fig. 1 and Fig. 2.Fig. 1 is the synoptic diagram of the drive unit 100 of a kind of liquid crystal panel of being provided according to the present invention one first embodiment, wherein drive unit 100 comprise a time controller 110, plurality of sources driver (source driver) 120-r (r=1,2,3 ..., R) and a plurality of gate pole driver (gate driver) 130-s (s=1,2 ..., n, (n+1) ..., m).Drive unit 100 is in order to driving liquid crystal panel 10, and generally speaking, drive unit 100 is to be arranged on the liquid crystal panel 10 and to form a liquid crystal panel module.Fig. 2 is the function block schematic diagram of an embodiment of time controller 110 shown in Figure 1, wherein time controller 110 comprise a data processing module 112, with a control signal generating module 114.Data processing module 112 is used to import among the raw data DATA0 of image signal Vin and inserts black data, and output data signal DATA.Control signal generating module 114 is to produce source electrode driver 120-r and the required controlling signal Ctrl_sigs of gate driver 130-s according to the synchronizing signal In_sig among the input image signal Vin, and controlling signal Ctrl_sigs comprises horizontal start signal STH-1～STH-R, data load (data load) signal TP, vertical start signal STV and gate pole enable signal OE_UP and OE_DN etc.
According to present embodiment, source electrode driver 120-r and gate pole driver 130-s system are used for driving the source electrode line (being data line) and the gate line of liquid crystal panel 10 respectively.Time controller 110 horizontal start signal STH-1～STH-R of output and data load signal TP are to source electrode driver 120-1～120-R; Wherein, Horizontal start signal STH-1～STH-R receives corresponding data among the data signals DATA in order to Controlling Source driver 120-1～120-R respectively in regular turn, and data load signal TP system exports received data in order to Controlling Source driver 120-r via the output terminal of source electrode driver 120-r.Time controller 110 is also exported vertical start signal STV and gate pole enable signal OE_UP and OE_DN to gate pole driver 130-s; Vertical start signal STV is sent to gate pole driver 130-m in regular turn by gate pole driver 130-1; Gate enable signal OE_UP system is in order to the gate activation time of control grid driver 130-1～130-n, and gate enable signal OE_DN system is in order to the gate activation time of control grid driver 130-(n+1)～130-m.The controlling signal of being exported by time controller 110 come Controlling Source driver 120-r and gate driver 130-s controlling mechanism will in hereafter it.
Please refer to Fig. 3 and Fig. 4.Fig. 3 is for according to a kind of sequential chart that is used for eliminating signal relevant with horizontal direction in the liquid crystal panel drive method of image fog that one embodiment of the invention provided, and Fig. 4 is the sequential chart of signal relevant with vertical direction among the embodiment shown in Figure 3.This driving method method can be applicable to drive unit shown in Figure 1 100, and can be by utilizing drive unit 100 (especially time controller 110) to implement.According to present embodiment, data processing module 112 produces a data signals DATA who is loaded with (carry) image data and black data, and is as shown in Figure 3.Data processing module 112 receives the raw data DATA0 among the input image signal Vin; This raw data DATA0 has above-mentioned image data; Data processing module 112 inserts black data between raw data DATA0 per two horizontal image datas; Mean in this so-called black data and to make liquid crystal panel 10 show black or near the image data of black; And the length of the black data that inserts must be greater than the number of the data line that single source electrode driver drove, and the time interval T between each horizontal line image data
INVNeed operation period T greater than single source electrode driver
SD, so that these source electrode drivers can normally operate.
The a plurality of horizontal start signal STH-1 that control signal generating module 114 produces, STH-2, STH-3 ..., with STH-R exported to respectively source electrode driver 120-1,120-2,120-3 ..., and 120-R.As shown in Figure 3; Each horizontal start signal STH-r (r=1,2,3 ..., R) have horizontal initial pulse PD_r of image data and the horizontal initial pulse PB_r of black data, wherein the horizontal initial pulse of black data is non-existent in the conventional horizontal start signal.As shown in Figure 3, horizontal start signal STH-1, STH-2, STH-3 ..., with STH-R have the horizontal initial pulse P of image data respectively
D1, P
D2, P
D3..., and PDR, the spacing that occurs in regular turn all equals the operation period T of single source electrode driver
SDThe horizontal initial pulse PDr of image data among horizontal start signal STH-r system in order to control with correspond among the data signals DATA source electrode driver 120-r (r=1,2,3 ..., R) image data be loaded on source electrode driver 120-r.Because data signals DATA originally just transmits the image data that corresponds to each source electrode driver with serial mode in regular turn, time controller 110 produces the horizontal initial pulse P of image data that occurs in regular turn respectively
D1, P
D2, P
D3..., and PDR, the image data that corresponds to each source electrode driver 120-r among the data signals DATA is inputed in the corresponding source electrode driver in regular turn.
Fig. 5 is the function block schematic diagram of a conventional source driver.As shown in Figure 5, source electrode driver 120-r comprises translation buffer (Shift Register) 510, line breech lock (Line Latch) 520, position accurate translation (Level Shift) circuit 530, digital analog converter 540 and output buffer 550.Source electrode driver 120-r is general source electrode driver, in this field, has common knowledge the knowledgeable and should know its structure and mode of operation.Briefly; Translation buffer 510 is according to horizontal start signal STH-r and frenquency signal CLKH; The data of data signals DATA are inputed to line breech lock 520 in regular turn; Data are temporary in the line breech lock 520, and when treating that line breech lock 520 receives the load pulses of data load signal TP, the data that are temporary in line breech lock 520 just can be via the accurate translation circuit in position 530, digital analog converter 540, and output buffer 550 outputs.
The data load signal TP that time controller 110 produces has image data load pulses TP
DUtilizing the horizontal initial pulse P of image data
D1, P
D2, P
D3..., in regular turn the corresponding part in the image data is respectively loaded on after the line breech lock 520 of these source electrode drivers 120-r with PDR, time controller 110 utilizes the image data load pulses TP among the data load signal TP
D, control the image data (promptly being arranged in the data of line breech lock) that whole source electrode driver 120-r will load simultaneously and export liquid crystal panel 10 to.In image data load pulses TP
DThe image data that is triggered loads in the running, and the accurate translation circuit 530 in position carries out accurate translation running in position and digital-to-analogue conversion respectively with digital analog converter 540, exports the image data that is loaded to liquid crystal panel 10 via output buffer 550 more at last.As shown in Figure 3, in receiving image data load pulses TP
DAfterwards, the data SD.OUT that these source electrode drivers 120-r is exported is image data, and before next data load pulse appearred in data load signal TP, the data SD.OUT that these source electrode drivers 120-r is exported remained unchanged.So, seeing through the gate enable signal OE_UP be used for controlling these gate pole drivers and OE_DN respectively according to the demonstration of preset time activation image data, time controller 110 just can drive liquid crystal panel 10 these image datas of demonstration.
As shown in Figure 3, horizontal start signal STH-1, STH-2, STH-3 ..., have simultaneously the horizontal initial pulse P of black data that occurs more respectively with STH-R
B1, P
B2, P
B3..., and PB_R.Time controller 110 utilizes the horizontal initial pulse PB_r of black data among these horizontal start signal STH-r, controls these source electrode drivers 120-r and simultaneously the black data among the data signals DATA is loaded on these source electrode drivers 120-r.For example: r=1, then time controller 110 utilizes the horizontal initial pulse P of black data
B1_ see through translation buffer 510 control line breech locks 520, with this black data of breech lock.Again for example: r=R, then time controller 110 utilizes the horizontal initial pulse PB_R of black data to see through translation buffer 510 control line breech locks 520, with this black data of breech lock.The data load signal TP that time controller 110 is produced has more black data load pulses TP
BUtilizing the horizontal initial pulse P of these black datas
B1, P
B2, P
B3..., simultaneously black data is loaded on after the line breech lock 520 of these source electrode drivers 120-r with PB_R, time controller 110 utilizes the black data load pulses TP among the data load signal TP
B, control these source electrode drivers 120-r output black data simultaneously, before next data load pulse occurred, the data SD.OUT of these source electrode drivers 120-r output remained unchanged.So, seeing through the gate enable signal OE_UP be used for controlling these gate pole drivers and OE_DN respectively according to the demonstration of preset time activation image data, time controller 110 just can drive liquid crystal panel 10 these black datas of demonstration.
Can know that by above-mentioned explanation time controller 110 is except utilizing the horizontal initial pulse PD_r of image data and the image data load pulses TP among the data load signal TP among these horizontal start signal STH-r respectively
DControl that these source electrode drivers 120-r loads and the image output data, time controller 110 utilizes the horizontal initial pulse PB_r of black data and the black data load pulses TP among the data load signal TP among these horizontal start signal STH-r in addition respectively
BControlling these source electrode drivers 120-r loads and the output black data.The data load signal TP that it should be noted that present embodiment has image data load pulses TP
DWith black data load pulses TP
B, and black data load pulses TP
BIn the traditional data loading signal, be non-existent.
The running of carrying out according to above-mentioned contents that source electrode driver 120-r exported about these gate pole drivers below is described.As shown in Figure 3, OE
HRepresent the activation time of gate enable signal; When wherein on behalf of the gate enable signal, OED be image data corresponding to the data of these source electrode drivers 120-r output, when on behalf of the gate enable signal, OEB then be black data corresponding to the data of these source electrode drivers 120-r output.As shown in Figure 4, time controller 110 produces a vertical start signal STV in addition and inputs to gate pole driver 130-1, and makes vertical start signal STV be passed to gate pole driver 130-m from gate pole driver 130-1 in order.Vertical start signal STV has the vertical initial pulse STV of an image data
DAnd the vertical initial pulse STV of at least one black data
B, the vertical initial pulse STV of image data wherein
DSystem is in order to image data displaying, and the vertical initial pulse STV of black data
BSystem is in order to show black data.Gate enable signal OED and gate pole enable signal OEB that time controller 110 produces optionally export gate pole driver 130-1～130-n to by RCA 140; Or export gate pole driver 130-(n+1)～130-m to by RCA 150; Wherein gate enable signal OED is created in when the output data SD.OUT of these source electrode drivers 120-r is image data, and gate enable signal OEB is created in when the output data SD.OUT of these source electrode drivers 120-r is the black data.Please note at this; Gate enable signal OE_UP on Fig. 1 and Fig. 4 is meant the gate enable signal that is transferred to gate pole driver 130-1～130-n by RCA 140; And gate enable signal OE_DN is meant the gate enable signal that is transferred to gate pole driver 130-(n+1)～130-m by RCA 150, and time controller 110 suitably switches output gate enable signal OED and gate pole enable signal OEB to RCA 140 and RCA 150.
Among the embodiment as shown in Figure 1, under frenquency signal CLKV control, the vertical initial pulse STV of image data of vertical start signal STV
DBegin to transmit downwards line by line from gate pole driver 130-1, as the vertical initial pulse STV of image data
DThe position is between gate pole driver 130-1 to 130-n the time; Time controller 110 exports gate enable signal OED to gate pole driver 130-1～130-n by RCA 140; Because the time of gate enable signal OED activation is when the output data SD.OUT of source electrode driver 120-r is image data; Therefore, along with the vertical initial pulse STV of image data
DFrom gate pole driver 130-1 transmission downwards line by line, the gate line of liquid crystal panel 10 just is enabled line by line, and then makes liquid crystal panel 10 image data among the video data signal DATA line by line; And as the vertical initial pulse STV of image data
DWhen being passed to gate pole driver 130-(n+1), time controller 110 promptly changes by RCA 150 and exports gate enable signal OED to gate pole driver 130-(n+1)～130-m, that is to say, as the vertical initial pulse STV of image data
DThe position is when gate pole driver 130-(n+1) is between 130-m; Time controller 110 is to export gate enable signal OED to gate pole driver 130-(n+1)～130-m; And the gate line that makes liquid crystal panel 10 be connected to gate pole driver 130-(n+1)～130-m is enabled line by line, and then the image data in the video data signal line by line.On the other hand, as the vertical initial pulse STV of image data
DBe passed to gate pole driver 130-(n+1) afterwards, time control 110 is to export gate enable signal OEB to gate pole driver 130-1～130-n by RCA 140, and produces the vertical initial pulse STV of one or more black datas
BBegin to transmit downwards line by line from gate pole driver 130-1 since activation time of gate enable signal OEB be when the output data SD.OUT of source electrode driver 120-r is black data, therefore, along with the vertical initial pulse STV of image data
BFrom gate pole driver 130-1 transmission downwards line by line, the gate line of liquid crystal panel 10 just is enabled line by line, and then makes liquid crystal panel 10 black data among the video data signal DATA line by line; Likewise, as the vertical initial pulse STV of black data
BWhen being passed to gate pole driver 130-(n+1); Time controller 110 promptly changes by RCA 150 and exports gate enable signal OEB to gate pole driver 130-(n+1)～130-m, and makes gate line that liquid crystal panel 10 is connected to gate pole driver 130-(n+1)～130-m line by line by the vertical initial pulse STV of black data
BWith the activation of gate pole enable signal OEB institute, and then the black data in the video data signal line by line.
In the foregoing description, because the vertical initial pulse STV of black data
BPossibly can't make the liquid crystal molecule of liquid crystal panel 10 be diverted to the arrangement mode of corresponding black data fully, so time controller 110 produces the vertical initial pulse STV of more than one black datas
B, be used for guaranteeing that the liquid crystal molecule of liquid crystal panel 10 display units fully is diverted to the arrangement mode corresponding to black data, show black positively to make liquid crystal panel 10.
Can know via above-mentioned explanation; Time controller 110 utilizes horizontal start signal STH-1～STH-R and data load signal TP to come Controlling Source driver 120-1～120-R respectively; The image data of DATA and black in the loading data signal, and time controller 110 produces the vertical initial pulse STV of an image data in an image time (frame time)
DAnd the vertical initial pulse STV of at least one black data
B, and suitably make the vertical initial pulse STV of image data
DAnd the vertical initial pulse STV of black data
BBe positioned at different gate pole driver group, and the corresponding gate enable signal of output is to gate pole driver group, for example, as the vertical initial pulse STV of image data
DWhen being positioned at gate pole driver 130-1～130-n, make the vertical initial pulse STV of black data
BBe positioned at gate pole driver 130-(n+1)～130-m, and export gate enable signal OED, and output gate enable signal OEB is to gate pole driver 130-(n+1)～130-m to gate pole driver 130-1～130-n; Otherwise, as the vertical initial pulse STV of image data
DWhen being positioned at gate pole driver 130-(n+1)～130-m, make the vertical initial pulse STV of black data
BBe positioned at gate pole driver 130-1～130-n; And output gate enable signal OED is to gate pole driver 130-(n+1)～130-m; And export gate enable signal OEB to gate pole driver 130-1～130-n, thus, liquid crystal panel 10 is according to the vertical initial pulse STV of image data
DUnderstand the quilt vertical initial pulse STV of black data thereafter with the image that gate pole enable signal OED is shown
BOEB changes to black image with the gate pole enable signal; Be the picture of black region and make liquid crystal panel 10 demonstrate part for the imagery zone part; Please refer to Fig. 6; Fig. 6 shows that promptly liquid crystal panel 10 part show images and part show the synoptic diagram of black, and time controller 110 may command liquid crystal panels 10 show black-tape (zone that promptly shows black) everywhere circularly in turn along vertical direction in full frame.Closely bound up with visual sense of continuity owing to take a sample with the origin cause of formation system that keeps false shadow, and above-mentioned black-tape inserts the machine-processed visual sense of continuity that can destroy, so the present invention can eliminate above-mentioned sampling by this and keep the image fog that false shadow causes.
Please refer to Fig. 7; Fig. 7 is an embodiment synoptic diagram of data processing module among Fig. 2; Data processing module 112 comprises a multiplexer 710, and multiplexer 710 has two input ends, respectively in order to receive raw data DATA0 and the black data among the input image signal Vin; At this black data is the numerical value that presents black that can make liquid crystal panel; And be stored in advance in the buffer (not illustrating) of time controller 110, the data enable signal DE among the input image signal Vin is then as the controlling signal of multiplexer 710, when data enable signal DE is the accurate position of high logic; Multiplexer 710 is selected output raw data DATA0; Otherwise when data enable signal DE was the accurate position of low logic, 710 of multiplexers were selected the output black data; Because raw data DATA0 is serial data and only is the interval actual image data that has of the accurate position of high logic at data enable signal DE; Under this mechanism, the data signals DATA that the output terminal of multiplexer 710 is exported is raw data DATA0 and between per two horizontal image datas, inserts black data, and meaning i.e. (Horizontal Blanking Interval) insertion black data between the horizontal clear area of source book DATA0.
Fig. 8 is the synoptic diagram of an embodiment of control signal generating module among Fig. 2; As shown in Figure 8; Control signal generating module 114 comprises a plurality of control signal generating unit 810～860; Each control signal generating unit system is in order to according to a sync signal In_sig and a setting value among the input image signal Vin; Produce the control signal of one source pole driver 120-r or gate driver 130-s, for example, control signal generating unit 810 is to produce horizontal start signal STH-1 according to the data enable signal DE among setting value V_STH-1 and the sync signal In_sig.Please refer to Fig. 9; Fig. 9 is the synoptic diagram of an embodiment of control signal generating module 810 among Fig. 8, and control signal generating module 810 comprises counter 901 and 902, comparer 903 and 907 or logic lock (OR Gate) 904, multiplexer 905 and 909 and D type flip-flop 909.Data enable signal DE system inputs to the replacement end (RST) of counter 901, when counter 901 runs into the rising edge of data enable signal DE, and the count value of promptly resetting; Comparer 903 continues the count value of count pick up device 901 outputs and makes it to compare with setting value V_STH-1; When the count value of counter 901 equates with setting value V_STH-1; Comparer be output logic signal " 1 " to or logic lock 904, and make or the control end of logic lock 904 output logic signal " 1 " to multitask devices 905; When the control end of multiplexer 905 is received logic signal " 1 "; Promptly export the received signal of input end of counterlogic signal " 1 ", and the input end of multiplexer 905 counterlogic signals " 1 " system receives the output data of multiplexer 909, at this moment; The received controlling signal of the control end of multiplexer 909 is logic signal " 0 "; Therefore, multiplexer 909 signal (being the accurate position of high logic VDD) that the input end of counterlogic signal " 0 " is received exports multiplexer 905 to, and makes the input end of the accurate position of the multiplexer high logic of 905 outputs VDD to D type flip-flop 906; And then the horizontal start signal STH-1 that D type flip-flop 906 output terminals are exported is raised to the accurate position of high logic VDD; At this moment, horizontal start signal STH-1 meeting counter reset 902, and comparer 907 can compare the count value and the pulse width PW of counter 907; When the count value of counter 907 equates with pulse width PW; Comparer 907 is the control end of output logic signal " 1 " to multitask device 909, and then makes multiplexer 909 change the signal that input end received (promptly low logic accurate position GND) of output counterlogic signal " 1 ", and then the horizontal start signal STH-1 that D type flip-flop 906 output terminals are exported is returned to low high logic accurate position GND; At this; The value of pulse width PW is the pulse width of horizontal start signal STH-1, and generally speaking, the pulse width of horizontal start signal STH-1 is 1 frequency.Though Fig. 9 is in order to the control signal generating module in the key diagram 8 810, in the enforcement, the control signal generating module 820～860 among Fig. 8 all can be similar or the framework that is same as the control signal generating module 810 among Fig. 9 reach.In one embodiment, employed setting value V_STH-1～V_STH-R in the control signal generating module 114, V_TP, V_STV, V_OED, and V_OEB be stored in all in advance in the buffer (not illustrating) of time controller 110.
As shown in Figure 8; Gate enable signal OED that control signal generating unit 850 produced and the gate enable signal OEB system that control signal generating unit 860 produced are output as gate enable signal OE_UP and gate pole enable signal OE_DN via an output switch unit 870; Wherein, Gate enable signal OE_UP system is in order to exporting RCA 140 to, and gate enable signal OE_DN system is in order to export RCA 150 to.Please refer to Figure 10, Figure 10 is the synoptic diagram of an embodiment of output switch unit 870 among Fig. 8.Output switch unit 870 is to be made up of multiplexer 871, multiplexer 872 and phase inverter 873; Gate enable signal OED and gate pole enable signal OEB input in multiplexer 871 and the multiplexer 872; And switching controls signal SW is directly inputted into the control end of multiplexer 871 and input to the control end of multiplexer 872 via reverser 873; Switching controls signal SW system is used to the output that reasonable time point switches multiplexer 871 and multiplexer 872; In one embodiment, switching controls signal SW can produce according to the sync signal In_sig among the input image signal Vin.
Figure 11 is the synoptic diagram of the drive unit 200 of a kind of liquid crystal panel of being provided according to the present invention one second embodiment, and wherein present embodiment system is the variant of this first embodiment.In a second embodiment; Time controller 210 is to export gate enable signal OE-1～OE-4 respectively to gate pole driver 230-1～230-4; And shown in Figure 12 be the sequential chart of signal relevant among the embodiment of Figure 11 with vertical direction, be noted that the TGD shown in Figure 12 represents the operation period of single gate pole driver; And time controller 210 to be operation period TGD with gate pole driver be chronomere makes gate enable signal OE-1～OE-4 does switching between the two at the gate enable signal OED performance of image data (promptly corresponding to) and gate pole enable signal the OEB performance of black data (promptly corresponding to); For example, when gate enable signal OE-1 was gate enable signal OED, gate enable signal OE-2～OE-4 then was gate enable signal OEB; Behind an operation period TGD; Gate enable signal OE-1 switches to gate enable signal OEB, and gate enable signal OE-2 switches to gate enable signal OED, and gate enable signal OE-3～OE-4 all remains unchanged.In a second embodiment, except time controller 210 produces the gate enable signal to some difference of mechanism of each gate pole driver, all the other principles all are same as first embodiment, just repeat no more at this.
Compared to known techniques; Driving method provided by the present invention can be under the situation of not changing commercially available standard drive with device and relevant time controller; Insert and eliminate image fog by the time control of the driver of liquid crystal panel being carried out black-tape, especially eliminate sampling and keep false shadow.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. driving method, in order to drive a liquid crystal panel module, this liquid crystal panel module has plural source electrode driver, it is characterized in that, and it includes:
A data signals that is loaded with image data and black data is provided;
A plurality of horizontal start signals are provided, and each of these horizontal start signals has one first pulse signal and one second pulse signal;
According to these first pulse signals, this image data is loaded on these source electrode drivers in regular turn;
According to these second pulse signals, this black data is loaded on these source electrode drivers;
One data load signal is provided, and this data load signal has one the 3rd pulse signal and one the 4th pulse signal;
According to the 3rd pulse signal, the image data output that these source electrode drivers will load; And
According to the 4th pulse signal, the black data output that these source electrode drivers will load.
2. driving method as claimed in claim 1 is characterized in that, after this image data whole being loaded on these source electrode drivers according to these first pulse signals, and the image data output that root will load according to the 3rd pulse signal.
3. driving method as claimed in claim 1 is characterized in that, after this black data whole being loaded on these source electrode drivers according to these second pulse signals, and the black data output that root will load according to the 4th pulse signal.
4. driving method as claimed in claim 1 is characterized in that, these second pulse signal systems make this black data be loaded on these source electrode drivers simultaneously.
5. like claim 1 described driving method, it is characterized in that this liquid crystal panel module has more plural gate pole driver, this driving method more includes:
One first gate enable signal and one second gate enable signal are provided; The output data that this first gate enable signal system corresponds to these source electrode drivers is during for this image data, and the output data that this second gate enable signal system corresponds to these source electrode drivers is during for this black data; And
Optionally utilize this first gate enable signal and this second gate enable signal to control these gate pole drivers.
6. driving method as claimed in claim 5 is characterized in that, more includes:
In an image time, provide two vertical start signals in regular turn through these gate pole drivers.
7. drive unit, is characterized in that it includes in order to drive a liquid crystal panel:
The plural number source electrode driver is in order to drive the plural source electrode line of this liquid crystal panel;
The plural number gate pole driver is in order to drive the plural gate line of this liquid crystal panel; And
One time controller, in order to produce plural horizontal start signal, one first gate enable signal and one second gate enable signal, wherein, these horizontal start signals are exported to these source electrode drivers respectively; When the data of corresponding these source electrode driver outputs of this first gate enable signal are image data; When the data of corresponding these source electrode driver outputs of this second gate enable signal are black data, optionally exported to these gate pole drivers according to different enable signals.
8. drive unit as claimed in claim 7 is characterized in that, this time controller is more in order to be loaded with the data signals of this image data and this black data according to an input image data generation one.
9. drive unit as claimed in claim 8; It is characterized in that; Each of these horizontal start signals has one first pulse signal and one second pulse signal; These first pulse signals system is in order to being loaded on these source electrode drivers with this image data in regular turn, and these second pulse signals systems are in order to be loaded on these source electrode drivers with this black data.
10. drive unit as claimed in claim 9; It is characterized in that; This time controller more produces a data load signal; This data load signal has one the 3rd pulse signal and one the 4th pulse signal, and the 3rd pulse signal is exported this image data in order to control these source electrode drivers, and the 4th pulse signal is in order to control these source electrode drivers with this black data output.
11. drive unit as claimed in claim 7 is characterized in that, this time controller is exported two vertical start signals to these gate pole drivers in an image time.
12. a time controller in order to control plural source electrode driver and the plural gate pole driver on the liquid crystal panel module, is characterized in that it includes:
One data processing module is used for producing a data signals that is loaded with image data and black data; And
One control signal generating module, in order to produce plural horizontal start signal, one first gate enable signal and one second gate enable signal, wherein, these horizontal start signals are in order to this data signals is loaded on these source electrode drivers; When the output data of corresponding these source electrode drivers of this first gate enable signal is this image data; When the output data of corresponding these source electrode drivers of this second gate enable signal is this black data, optionally exported to these gate pole drivers according to different enable signals.
13. time controller as claimed in claim 12; It is characterized in that; Each of these horizontal start signals has one first pulse signal and one second pulse signal; These first pulse signal systems are in order to load these source electrode drivers with this image data in regular turn, and these second pulse signal systems are in order to be loaded on these source electrode drivers with this black data.
14. time controller as claimed in claim 13; It is characterized in that; This control signal generating module more produces a data load signal; This data load signal has one the 3rd pulse signal and one the 4th pulse signal, and the 3rd pulse signal system exports this image data in order to control these source electrode drivers, and the 4th pulse signal system is in order to control these source electrode drivers with this black data output.
15. time controller as claimed in claim 14 is characterized in that, this control signal generating module is more exported two vertical start signals to these gate pole drivers in an image time.
16. time controller as claimed in claim 12 is characterized in that, this control signal generating module system produces these horizontal start signals, this first gate enable signal and this second gate enable signal according to the sync signal in the input image signal.
17. time controller as claimed in claim 16; It is characterized in that; This control signal generating module comprises plural control signal generating unit, and these control signal generating unit system is respectively according to producing these horizontal start signals, this first gate enable signal and this second gate enable signal one of in this synchronizing signal and the plural setting value.
18. time controller as claimed in claim 12 is characterized in that, this data processing module inserts this black data in lying between the horizontal clear area of an input image signal, to produce this data signals.
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| CN2009100006134A CN101777313B (en) | 2009-01-08 | 2009-01-08 | Driving method and device of liquid crystal display panel and time controller of liquid crystal display panel |
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| CN2009100006134A CN101777313B (en) | 2009-01-08 | 2009-01-08 | Driving method and device of liquid crystal display panel and time controller of liquid crystal display panel |
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| CN101777313B true CN101777313B (en) | 2012-05-23 |
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| CN109493824B (en) * | 2018-12-28 | 2021-11-02 | 北京集创北方科技股份有限公司 | Source driver, display device and driving method thereof |
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