CN117472801B

CN117472801B - Video memory bandwidth optimization method, device and system and BMC system

Info

Publication number: CN117472801B
Application number: CN202311825836.0A
Authority: CN
Inventors: 丁月; 魏红杨; 周玉龙
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-03-01
Anticipated expiration: 2043-12-28
Also published as: CN117472801A

Abstract

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a system, and a BMC system for optimizing video memory bandwidth. The method comprises the following steps: reading a read video memory address and a write video memory address of the video memory respectively; under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient; under the condition that the video memory bandwidth is insufficient, the predicted pixel block information of the current frame image is fed back to the host computer so as to display pixels; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain predicted pixel block information. According to the method, the problem of insufficient video memory bandwidth can be made up by feeding back the predicted pixel block information under the condition of insufficient video memory bandwidth, smooth display pictures are ensured, the problems of flower points, black points and the like are avoided, and the impression experience of a user is ensured.

Description

Video memory bandwidth optimization method, device and system and BMC system

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a system, and a BMC system for optimizing video memory bandwidth.

Background

The local display of the general server is usually processed by an integrated graphics card in a BMC (Baseboard Management Controller, motherboard management controller) system and then output to a display for display. The video memory used by the integrated video card is usually part of the memory space of the BMC system. When the load of the BMC system is higher, the utilization rate of the BMC system memory is higher, and correspondingly, the condition of insufficient system memory bandwidth can also occur. Because the video memory used by the integrated video card is a part of the BMC system memory, when the system memory has insufficient bandwidth, the read-write of the video memory is also influenced, so that the read-write time sequence of the video memory is abnormal, namely the write video memory is slower than the read video memory. For example: the latest display data is not written into the video memory in time, but the host computer reads the data of the video memory to obtain and display the image data of the previous frame, and the like, so that the phenomenon of screen display or black block appears on the local display screen, and the visual experience of a user is influenced.

Disclosure of Invention

The invention provides a video memory bandwidth optimization method, a device, a system and a BMC system, which are used for solving the problems that in the prior art, when the memory bandwidth of the BMC system is insufficient, the read-write time sequence of the video memory is abnormal, the display effect is affected and poor look and feel experience is brought to a user.

The invention provides a video memory bandwidth optimization method, which comprises the following steps:

reading a read video memory address and a write video memory address of the video memory respectively;

under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient;

under the condition that the video memory bandwidth is insufficient, the predicted pixel block information of the current frame image is fed back to a host computer so as to display pixels; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information.

The method for optimizing the video memory bandwidth provided by the invention further comprises the following steps:

under the condition that a pixel point information writing command is received, writing pixel point information to be written, which is carried by the pixel point information writing command, into a preset pixel line buffer area; the pixel line buffer area is used for buffering the pixel point information to be written of the preset line number of the latest frame image; the pixel point information to be written in the preset line number is written in the pixel line buffer area, and meanwhile, the history cache pixel point information in the pixel line buffer area is cleared; the pixel point information to be written in the pixel line buffer area is the second cache pixel information;

And under the condition that the pixel point information to be written is successfully written into the pixel line buffer area, writing the pixel point information to be written into the video memory.

according to a preset sampling frequency, sampling pixel points in the pixel line buffer area to obtain pixel point information of a complete frame of image;

and caching the pixel point information of the sampled complete one-frame image to a preset data sampling buffer area, wherein the pixel point information of the complete one-frame image cached to the data sampling buffer area for the last time is the first cached pixel information.

according to a preset prediction period, the first cache pixel information is collected from the data sampling buffer area at regular intervals, and the second cache pixel information is collected from the pixel line buffer area;

under the condition that the first cache pixel information and the second cache pixel information are obtained, carrying out pixel prediction based on the first cache pixel information and the second cache pixel information to obtain the predicted pixel block information;

And caching the predicted pixel block information to a preset predicted pixel buffer area.

According to the video memory bandwidth optimization method provided by the invention, under the condition that the video memory bandwidth is insufficient, the step of feeding back the predicted pixel block information of the current frame image to the host for pixel display comprises the following steps:

under the condition that the video memory bandwidth is insufficient, sending a prediction control signal to a preset selector; the prediction control signal is used for indicating the selector to read the predicted pixel block information from the predicted pixel buffer area based on the prediction control signal, and feeding the predicted pixel block information back to a host for pixel display.

According to the video memory bandwidth optimization method provided by the invention, pixel prediction is performed based on the first cache pixel information and the second cache pixel information, and the step of obtaining the predicted pixel block information comprises the following steps:

obtaining a target cache size based on the size of a predicted pixel block and a preset downsampling multiple, wherein the target cache size is obtained by downsampling the predicted pixel block based on the downsampling multiple;

determining the position of the predicted pixel block in the previous frame image and the current frame image based on the target buffer size;

Determining a first reference pixel block based on the position of the predicted pixel block in the previous frame image, and obtaining first reference pixel block information from the first cache pixel information, wherein the first reference pixel block is a pixel block positioned above the predicted pixel block in the previous frame image, the first reference pixel block comprises a plurality of first reference pixel points, the first reference pixel block information comprises a plurality of first reference pixel point information, and the first reference pixel points are in one-to-one correspondence with the first reference pixel point information;

determining a second reference pixel block based on the position of the predicted pixel block in the current frame image, and obtaining second reference pixel block information from the second cache pixel information, wherein the second reference pixel block is a pixel block positioned above the predicted pixel block in the current frame image, the second reference pixel block comprises a plurality of second reference pixel points, the second reference pixel block information comprises a plurality of second reference pixel point information, and the second reference pixel points are in one-to-one correspondence with the second reference pixel point information;

determining an image motion vector direction under the condition that the first reference pixel point information and the second reference pixel point information are different;

And carrying out pixel prediction based on the image motion vector direction to obtain the predicted pixel block information.

According to the video memory bandwidth optimization method provided by the invention, the step of determining the direction of the image motion vector comprises the following steps of:

under the condition that the first reference pixel point information and the second reference pixel point information are different, obtaining a plurality of overlapped pixel block groups by carrying out unit translation operation on the first reference pixel block for a plurality of times; the number of times of translating the first reference pixel block is the same as the number of preset target translation directions; each time the first reference pixel block is subjected to unit translation operation, the first reference pixel block is controlled to translate a pixel point in any target translation direction; the overlapping pixel block group includes: a first overlapping pixel block and a second overlapping pixel block, wherein the first overlapping pixel block refers to a pixel block which is overlapped with the existence position of the second reference pixel block in the first reference pixel block after unit translation, and the second overlapping pixel block refers to a pixel block which is overlapped with the existence position of the first reference pixel block after unit translation in the second reference pixel block;

Obtaining pixel deviation values between the first reference pixel block and the second reference pixel block in each overlapped pixel block group based on the overlapped pixel block group, the first reference pixel point information and the second reference pixel point information;

and determining an image motion vector direction based on the pixel deviation value.

According to the video memory bandwidth optimization method provided by the invention, the step of obtaining the pixel offset value between the first reference pixel block and the second reference pixel block in each overlapped pixel block group based on the overlapped pixel block group, the first reference pixel point information and the second reference pixel point information comprises the following steps:

obtaining first overlapping pixel point information of the first overlapping pixel block and second overlapping pixel point information of the second overlapping pixel block based on the overlapping pixel block group, the first reference pixel point information and the second reference pixel point information;

and obtaining the pixel deviation value based on the first overlapped pixel point information and the second overlapped pixel point information.

According to the video memory bandwidth optimization method provided by the invention, the first coincident pixel point information comprises the following steps: pixel values of a plurality of first coincident pixel points; the second overlapping pixel point information includes: pixel values of a plurality of second overlapping pixels;

The step of obtaining the pixel deviation value based on the first overlapping pixel point information and the second overlapping pixel point information includes:

calculating the difference value between the pixel value of the first coincident pixel point and the pixel value of a second coincident pixel point at a corresponding position to obtain intermediate deviation values, wherein the number of the intermediate deviation values is the same as that of the first coincident pixel points or the second coincident pixel points;

and determining the sum value among all the intermediate deviation values as the pixel deviation value.

According to the video memory bandwidth optimization method provided by the invention, the step of determining the direction of the image motion vector based on the pixel deviation value comprises the following steps:

determining the minimum value of all the pixel deviation values as a target pixel deviation value;

and determining the target translation direction corresponding to the target pixel deviation value as the image motion vector direction.

According to the video memory bandwidth optimization method provided by the invention, the step of carrying out pixel prediction based on the image motion vector direction to obtain the predicted pixel block information comprises the following steps:

obtaining a compensation coefficient group corresponding to the image motion vector direction based on the image motion vector direction;

And carrying out pixel prediction based on the compensation coefficient group and the second reference pixel point information to obtain the predicted pixel block information.

According to the video memory bandwidth optimization method provided by the invention, based on the image motion vector direction, the step of obtaining the compensation coefficient group corresponding to the image motion vector direction comprises the following steps:

obtaining a compensation coefficient group corresponding to the image motion vector direction based on the image motion vector direction and a preset compensation coefficient lookup table, wherein the compensation coefficient lookup table comprises: a plurality of image motion vector directions, and the compensation coefficient sets corresponding to the image motion vector directions one by one; the compensation coefficient set includes: and the compensation coefficients are used for performing shift compensation when pixel prediction is performed.

According to the video memory bandwidth optimization method provided by the invention, pixel prediction is performed based on the compensation coefficient group and the second reference pixel point information, and the step of obtaining the predicted pixel block information comprises the following steps:

for any one of the predicted pixel points in the predicted pixel block, acquiring a plurality of second reference pixel points adjacent to the predicted pixel point in the second reference pixel block;

Determining the second reference pixel point adjacent to the predicted pixel point in the second reference pixel block as a pixel point to be processed;

determining the second reference pixel point information of the pixel point to be processed as pixel point information to be processed;

and carrying out pixel prediction based on the pixel point information to be processed and the compensation coefficient group to obtain the predicted pixel block information.

According to the video memory bandwidth optimization method provided by the invention, the number of compensation coefficients in the compensation coefficient group is the same as the number of pixel point information to be processed; and the compensation coefficients are in one-to-one correspondence with the pixel point information to be processed.

According to the video memory bandwidth optimization method provided by the invention, the step of carrying out pixel prediction based on the pixel point information to be processed and the compensation coefficient group to obtain the predicted pixel block information comprises the following steps:

obtaining a compensation value based on the compensation coefficient and a preset adjustment item, wherein the compensation coefficient corresponds to the adjustment item one by one;

determining the product of the compensation value and the corresponding pixel point information to be processed as an intermediate pixel value;

determining the sum value among all the intermediate pixel values as the pixel information of the current predicted pixel point;

And determining pixel information of all the predicted pixel points as the predicted pixel block information.

According to the video memory bandwidth optimization method provided by the invention, the step of obtaining the compensation value based on the compensation coefficient and the preset adjustment item comprises the following steps:

and determining the sum value between the compensation coefficient and the corresponding adjustment item as the compensation value.

According to the video memory bandwidth optimization method provided by the invention, the pixel point information to be processed comprises the following steps: pixel values of R, G, B three channels of the pixel point to be processed;

the step of determining the product between the compensation value and the corresponding pixel point information to be processed as an intermediate pixel value comprises the following steps:

and multiplying the compensation value by pixel values of the R, G, B three channels corresponding to the pixel point to be processed to obtain the intermediate pixel value.

under the condition that the first reference pixel point information and the second reference pixel point information are the same, determining that the previous frame image and the current frame image are in a relative static state;

and under the condition that the previous frame image and the current frame image are determined to be in the relative static state, determining that all compensation coefficients in a compensation coefficient group are 0, wherein the compensation coefficients are used for carrying out shift compensation when pixel prediction is carried out.

The invention also provides a video memory bandwidth optimization device, which comprises:

the address reading module is used for respectively reading the read video memory address and the write video memory address of the video memory;

the judging module is used for determining that the video memory bandwidth is insufficient under the condition that the read video memory address is larger than the write video memory address;

the optimization module is used for feeding back the predicted pixel block information of the current frame image to the host computer to display pixels under the condition that the video memory bandwidth is insufficient; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information.

The invention also provides a video memory bandwidth optimization system, which comprises:

the memory bandwidth optimizing apparatus according to the above, and the buffer apparatus, the buffer apparatus includes: a pixel line buffer, a data sampling buffer, a predicted pixel buffer; the selector is respectively connected with the video memory bandwidth optimizing device and the buffer device, and the video memory bandwidth optimizing device is connected with the buffer device.

The invention also provides a BMC system, comprising:

the system comprises a video memory and the video memory bandwidth optimization system, wherein the video memory is connected with the video memory bandwidth optimization system.

The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the video memory bandwidth optimization method according to any one of the above when executing the program.

The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a video memory bandwidth optimization method as described in any of the above.

The invention has the beneficial effects that: the invention provides a video memory bandwidth optimization method, a device, a system and a BMC system, wherein a read video memory address and a write video memory address of a video memory are respectively read; under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient; under the condition that the video memory bandwidth is insufficient, the predicted pixel block information of the current frame image is fed back to the host computer so as to display pixels; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain predicted pixel block information. According to the method, the device and the system as well as the BMC system, the problem of insufficient video memory bandwidth can be solved by feeding back the predicted pixel block information under the condition of insufficient video memory bandwidth (the insufficient video memory bandwidth means insufficient memory bandwidth of the BMC system), the smooth display picture is ensured, the problems of flower points, black points and the like are avoided, the stability is high, and the visual experience of a user is ensured.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of a video memory bandwidth optimization method provided by the invention;

FIG. 2 is a schematic diagram of a read/write video memory in the video memory bandwidth optimization method provided by the invention;

FIG. 3 is a schematic diagram of pixel distribution of a buffered image in a pixel line buffer in a video memory bandwidth optimization method according to the present invention;

FIG. 4 is a schematic diagram showing the position distribution of a predicted pixel block in a data sampling buffer, a pixel line buffer, and a current display page in the video memory bandwidth optimization method provided by the present invention;

FIG. 5 is a schematic diagram of overlapping pixel blocks in the video memory bandwidth optimization method provided by the invention;

FIG. 6 is a schematic diagram showing the distribution of image motion vector directions in the video memory bandwidth optimization method provided by the invention;

FIG. 7 is a schematic diagram of a video memory bandwidth optimization device according to the present invention;

FIG. 8 is a schematic diagram of a BMC system according to the present invention;

fig. 9 is a schematic structural diagram of an electronic device provided by the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

By way of example, the method, apparatus, system and BMC system for optimizing video memory bandwidth provided by the invention are described below with reference to FIGS. 1-9.

Referring to fig. 1, the method for optimizing video memory bandwidth provided in this embodiment includes:

s110: and respectively reading the read video memory address and the write video memory address of the video memory.

It should be noted that the read video memory address refers to a position where data is read from the video memory, i.e. a readable position in the video memory. The write video memory address refers to a target position of writing data in the video memory, namely a writable position in the video memory.

It should be mentioned that, as shown in fig. 2, the read-write flow of the video memory is as follows: the data in the video memory is written into a BMC internal integrated video card (the video memory bandwidth optimization device is integrated in the BMC internal integrated video card) by the host, and the data is written into the video memory after being processed by the BMC internal integrated video card. And then, the BMC internally integrates the display card, reads data from the video memory and feeds the data back to the host.

Specifically, the read-write address bus is monitored to obtain the read video memory address and the write video memory address of the video memory. Under the condition that the memory bandwidth of the BMC system is sufficient, namely the memory bandwidth is sufficient, the write memory address of the memory should be always larger than or equal to the read memory address. When the writing video memory address of the video memory is larger than the reading video memory address, the latest data written by the current frame image can be considered to exist in the video memory. Therefore, when a video memory reading command of the host is received, the existing data in the current video memory is directly fed back to the host, so that image display is realized. When the read video memory address is larger than the write video memory address, the latest data of the current frame image is not written yet. In this case, if a read video memory command is received from the host, the data in the video memory read by the host may be not the latest data of the current frame image, but may be the data of the previous frame image or the data that should be emptied. At this time, the data in the memory is erroneous data. Therefore, in this embodiment, in the case where it is determined that the read video memory address is greater than the write video memory address, it is determined that the video memory bandwidth is insufficient.

S120: and under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient.

S130: and under the condition that the video memory bandwidth is insufficient, feeding back the predicted pixel block information of the current frame image to a host computer for pixel display. The predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information.

It should be noted that, under the condition that the video memory bandwidth is determined to be insufficient, the predicted pixel block information of the current frame image is fed back to the host for pixel display, so that the display problem caused by the insufficient video memory bandwidth can be solved to a certain extent, the reading behavior of the video memory is reduced, that is, the video memory reading operation is not required, and therefore the video memory reading and writing bandwidth is reduced to a certain extent, the user experience is effectively improved, the stability is higher, and the practicability is stronger.

It should be noted that, by performing pixel prediction based on the first buffered pixel information of the previous frame image and the second buffered pixel information of the current frame image, that is, the first buffered pixel information of the previous frame image and the second buffered pixel information of the current frame image are organically combined, and pixel prediction is performed, the predicted pixel block information with higher accuracy can be obtained, which is helpful for realizing accurate display.

It should be noted that the predicted pixel block information refers to the currentPixel information of a pixel block to be predicted in a frame image. The current frame image refers to a frame image which is written in the memory last time, and the last frame image refers to a last frame image of the current frame image. The size of the predicted pixel block can be adjusted and configured according to practical situations, such asPixels, etc.

To facilitate reading the second buffered pixel information, in some embodiments, further comprising:

1. under the condition that a pixel point information writing command is received, writing pixel point information to be written, which is carried by the pixel point information writing command, into a preset pixel line buffer area; the pixel line buffer area is used for buffering the pixel point information to be written of the preset line number of the latest frame image; the pixel point information to be written in the preset line number is written in the pixel line buffer area, and meanwhile, the history cache pixel point information in the pixel line buffer area is cleared; and the pixel point information to be written in the pixel line buffer area is the second cache pixel information.

It should be noted that, the pixel line buffer area only buffers the pixel point information to be written of the preset line number of the latest frame of image. Therefore, when data is written into the pixel line buffer area, the historical cache pixel point information in the pixel line buffer area is cleared at the same time, so that the instantaneity of the pixel line buffer area is ensured, and the cache pressure of the pixel line buffer area is reduced.

It should be further noted that the preset number of rows may be set according to actual situations, such as 4 rows or 5 rows, and in general, the preset number of rows is greater than or equal to 2, which is not described herein.

2. And under the condition that the pixel point information to be written is successfully written into the pixel line buffer area, writing the pixel point information to be written into the video memory. Specifically, the pixel point information to be written is written into the pixel line buffer area, and then the pixel point information to be written is written into the video memory.

Fig. 3 is a schematic diagram of pixel distribution of a buffered image in a pixel line buffer in the video memory bandwidth optimization method according to the present embodiment. Referring to fig. 3, 4 lines of pixel point information to be written are buffered in the pixel line buffer in fig. 3. And the 16 pixels of the fifth row (the pixels with diagonal lines in fig. 3) refer to the predicted pixel block that needs to be predicted for the current frame image. The step of obtaining the predicted pixel block information is completed in advance of the step of writing the pixel point information to be written into the pixel line buffer area. The step of predicting the pixels starts to predict from the time when the first cache pixel information and the second cache pixel information are acquired, and timeliness is high.

To facilitate the retrieval or reading of the first buffered pixel information, in some embodiments, further comprises:

1. and sampling the pixel points of the pixel line buffer area according to a preset sampling frequency to obtain pixel point information of a complete frame of image.

2. And caching the pixel point information of the sampled complete one-frame image to a preset data sampling buffer area, wherein the pixel point information of the complete one-frame image cached to the data sampling buffer area for the last time is the first cached pixel information.

It should be noted that the sampling frequency may be set according to practical situations, such as 1 time/second. And carrying out pixel point sampling on the pixel line buffer area according to the sampling frequency, and under the condition that the pixel point information of the complete one-frame image is obtained, caching the obtained pixel point information of the complete one-frame image into the data sampling buffer area, thereby realizing the caching of the first cached pixel information.

In some embodiments, further comprising:

1. and according to a preset prediction period, the first cache pixel information is collected from the data sampling buffer area at regular intervals, and the second cache pixel information is collected from the pixel line buffer area.

2. And under the condition that the first cache pixel information and the second cache pixel information are obtained, carrying out pixel prediction based on the first cache pixel information and the second cache pixel information to obtain the predicted pixel block information.

3. And caching the predicted pixel block information to a preset predicted pixel buffer area.

The step of predicting the pixel is a step performed continuously. Specifically, when the video memory is in an operation state, the steps of first cache pixel information acquisition, second cache pixel information acquisition and pixel prediction are continuously executed. Under the condition of insufficient video memory bandwidth, corresponding predicted pixel block information is directly read from a predicted pixel buffer area, and the predicted pixel block information is fed back to a host for display, so that the real-time performance of pixel prediction and response is ensured, and the optimization of the video memory bandwidth is realized.

It should be further noted that, the predicted pixel buffer only holds the predicted pixel block information of the current frame image that is predicted up to date, i.e. the predicted pixel buffer only holds the predicted pixel block information of the single prediction. With the writing of the latest predicted pixel block information, the historical predicted pixel block information in the predicted pixel buffer will be cleared. Therefore, the buffer burden of the predicted pixel buffer area is reduced, and the running speed of the system is improved.

In some embodiments, in the case that the video memory bandwidth is determined to be insufficient, feeding back the predicted pixel block information of the current frame image to the host for pixel display includes:

Under the condition that the video memory bandwidth is not enough, a prediction control signal is sent to the selector, so that the selector can be controlled to select a prediction pixel buffer area, the prediction pixel block information is read from the prediction pixel buffer area, and the prediction pixel block information is fed back to the host for display, and the real-time performance of pixel prediction and response is ensured.

It should be noted that, under the condition that the video memory bandwidth is determined to be sufficient, a reading control signal is sent to the selector, and the reading control signal is used for indicating the selector to read corresponding information from the video memory, and then the information is fed back to the host for displaying.

Further, the selector reads the buffered information from a preset fifo (First In First Out, first-in first-out) buffer when receiving the read control signal. The fifo buffer is used for caching the latest pixel data or pixel values in the video memory. It will be appreciated that in the case of sufficient memory bandwidth, the selector reads the latest pixel data or pixel values in the memory through the fifo buffer.

The following explains the procedure of pixel prediction in the present invention. In the invention, the mode of predicting the predicted pixel block in the current frame image adopts an intra-frame prediction and inter-frame compensation mode.

In some embodiments, the step of performing pixel prediction based on the first cached pixel information and the second cached pixel information to obtain the predicted pixel block information includes:

1. and obtaining a target buffer size based on the size of the predicted pixel block and a preset downsampling multiple, wherein the target buffer size is obtained by downsampling the predicted pixel block based on the downsampling multiple.

It should be noted that the downsampling multiple may be set according to actual requirements, such as 4. It will be appreciated that the downsampling multiple is used for both the data sample buffer and the pixel line buffer when data buffering is performed. Therefore, the size of the sampling frame of the data sampling buffer (image frame corresponding to the first buffer pixel information) and the sampling frame of the pixel line buffer (image frame corresponding to the second buffer pixel information) is 1/N of the actual frame. Wherein N is a down-sampling multiple. Therefore, the target buffer size is obtained based on the size of the predicted pixel block and the downsampling multiple, so that the pixel prediction can be conveniently performed based on the target buffer size. For example: assume that the predicted pixel block is of size The downsampling multiple is 4, then the corresponding target buffer size is +.>I.e. the size of the predicted pixel block in the data sample buffer and the pixel line buffer is +.>。

2. And determining the position of the predicted pixel block in the previous frame image and the current frame image based on the target buffer size.

3. Determining a first reference pixel block based on the position of the predicted pixel block in the previous frame image, and obtaining first reference pixel block information from the first cache pixel information, wherein the first reference pixel block is a pixel block positioned above the predicted pixel block in the previous frame image, the first reference pixel block comprises a plurality of first reference pixel points, the first reference pixel block information comprises a plurality of first reference pixel point information, and the first reference pixel points are in one-to-one correspondence with the first reference pixel point information.

4. Determining a second reference pixel block based on the position of the predicted pixel block in the current frame image, and obtaining second reference pixel block information from the second cache pixel information, wherein the second reference pixel block is a pixel block positioned above the predicted pixel block in the current frame image, the second reference pixel block comprises a plurality of second reference pixel points, the second reference pixel block information comprises a plurality of second reference pixel point information, and the second reference pixel points are in one-to-one correspondence with the second reference pixel point information.

The first reference pixel block and the second reference pixel block have the same size. The sizes of the first reference pixel block and the second reference pixel block can be adjusted according to practical situations, such asEtc.

5. And determining an image motion vector direction under the condition that the first reference pixel point information and the second reference pixel point information are different.

It should be noted that, by determining the image motion vector direction when the first reference pixel point information and the second reference pixel point information are different, the subsequent pixel prediction based on the image motion vector direction can be facilitated, so as to implement "inter-frame compensation", thereby helping to improve the accuracy of the obtained predicted pixel block information.

6. And carrying out pixel prediction based on the image motion vector direction to obtain the predicted pixel block information.

Fig. 4 is a schematic diagram of the position distribution of the predicted pixel block in the data sampling buffer, the pixel line buffer, and the current display page in the video memory bandwidth optimization method provided in this embodiment. Referring to fig. 4, P1 in fig. 4 represents a previous frame image in the data sampling buffer, P2 represents a sampled image of a current frame image in the pixel line buffer, and P3 represents a normal size image frame of a current display page or a current frame image without downsampling. The hatched portion in P3 indicates a predicted pixel block, i.e., a pixel block that needs to be predicted. The shaded portion in P1 indicates the position of the downsampled predicted pixel block in the previous frame of image in the data sample buffer. The hatched portion in P2 indicates the position of the downsampled predicted pixel block in the current frame image of the pixel row buffer. The rectangle of the inside drawn x in P1 represents the first reference pixel block. The rectangle of the inside drawn x in P2 represents the second reference pixel block. It will be appreciated that the upper half of P2 and P3 are pixels that have been written to the memory, while the lower half are pixels that have not been written to the memory and that need prediction.

In some embodiments, in the case that there is a difference between the first reference pixel point information and the second reference pixel point information, the step of determining the image motion vector direction includes:

1. under the condition that the first reference pixel point information and the second reference pixel point information are different, obtaining a plurality of overlapped pixel block groups by carrying out unit translation operation on the first reference pixel block for a plurality of times; the number of times of translating the first reference pixel block is the same as the number of preset target translation directions; each time the first reference pixel block is subjected to unit translation operation, the first reference pixel block is controlled to translate a pixel point in any target translation direction; the overlapping pixel block group includes: the first overlapping pixel block refers to a pixel block which is overlapped with the existence position of the second reference pixel block in the first reference pixel block after unit translation, and the second overlapping pixel block refers to a pixel block which is overlapped with the existence position of the first reference pixel block after unit translation in the second reference pixel block.

It should be noted that, since the change of the two adjacent frames of images is usually not very large, in this embodiment, the unit shift operation is performed for the first reference pixel block multiple times towards different target shift directions, so that the pixel offset value between the first reference pixel block and the second reference pixel block after the unit shift can be obtained, and the image motion vector direction is determined according to the pixel offset value. The target translation direction includes: upper, lower, left, right, upper left, lower left, upper right, lower right, etc.

2. And obtaining pixel deviation values between the first reference pixel block and the second reference pixel block in each overlapped pixel block group based on the overlapped pixel block group, the first reference pixel point information and the second reference pixel point information.

3. And determining an image motion vector direction based on the pixel deviation value.

Fig. 5 is a schematic diagram of overlapping pixel blocks in the video memory bandwidth optimization method provided in this embodiment. Referring to fig. 5, it is assumed that the first reference pixel block P1 and the second reference pixel block P2 areIs included in the pixel block of (a). By shifting the first reference pixel block P1 one pixel point to the right, a coincident pixel block between the second reference pixel block P2 and the shifted first reference pixel block P1 can be obtained,the other target translation directions are the same.

In some embodiments, the step of obtaining pixel offset values between the first reference pixel block and the second reference pixel block in each of the overlapping pixel block groups based on the overlapping pixel block groups, the first reference pixel point information, and the second reference pixel point information includes:

1. and obtaining first overlapping pixel point information of the first overlapping pixel block and second overlapping pixel point information of the second overlapping pixel block based on the overlapping pixel block group, the first reference pixel point information and the second reference pixel point information.

2. And obtaining the pixel deviation value based on the first overlapped pixel point information and the second overlapped pixel point information.

In some embodiments, the first coincident pixel point information includes: pixel values of a plurality of first coincident pixel points; the second overlapping pixel point information includes: and the pixel values of the second overlapping pixels are overlapped.

Further, the step of obtaining the pixel deviation value based on the first overlapping pixel point information and the second overlapping pixel point information includes:

1. and calculating the difference value between the pixel value of the first coincident pixel point and the pixel value of the second coincident pixel point at the corresponding position to obtain intermediate deviation values, wherein the number of the intermediate deviation values is the same as that of the first coincident pixel points or the second coincident pixel points.

2. And determining the sum value among all the intermediate deviation values as the pixel deviation value. It should be noted that, by acquiring the pixel deviation value, the direction of the motion vector of the image is obtained to be convenient for subsequent determination.

In some embodiments, the step of determining the image motion vector direction based on the pixel deviation value comprises:

1. determining the minimum value of all the pixel deviation values as a target pixel deviation value;

2. And determining the target translation direction corresponding to the target pixel deviation value as the image motion vector direction. The accuracy is high by determining the target translation direction corresponding to the smallest pixel deviation value as the image motion vector direction.

Fig. 6 is a schematic diagram of distribution of image motion vector directions in the video memory bandwidth optimization method provided in this embodiment. In fig. 6, the right direction is defined as 0 °, the clockwise offset direction is defined as positive, and the counterclockwise offset direction is defined as negative. Correspondingly, the upward direction is 270 °, the leftward direction is 180 °, and the downward direction is 90 °.

In some embodiments, the step of performing pixel prediction based on the image motion vector direction to obtain the predicted pixel block information includes:

1. and obtaining a compensation coefficient group corresponding to the image motion vector direction based on the image motion vector direction.

2. And carrying out pixel prediction based on the compensation coefficient group and the second reference pixel point information to obtain the predicted pixel block information. It should be noted that, for the current predicted prediction pixel block, the compensation coefficient set used for each prediction pixel point is the same. By performing pixel prediction based on the compensation coefficient group and the second reference pixel point information, compensation between two adjacent frames of images is better realized.

In some embodiments, based on the image motion vector direction, the step of deriving the set of compensation coefficients corresponding to the image motion vector direction comprises:

Table 1 below is an example of a compensation coefficient lookup table, as shown in table 1:

table 1 compensation coefficient lookup table example

Wherein T1, T2, T3 and T4 are compensation coefficients in the set of compensation coefficients, which are exemplified herein by 4 compensation coefficients. T1, T2, T3 and T4 are used for shift compensation in pixel prediction.

In some embodiments, the step of performing pixel prediction based on the compensation coefficient set and the second reference pixel point information to obtain the predicted pixel block information includes:

1. and for any one of the predicted pixel points in the predicted pixel block, acquiring a plurality of second reference pixel points adjacent to the predicted pixel point in the second reference pixel block.

2. And determining the second reference pixel point adjacent to the predicted pixel point in the second reference pixel block as a pixel point to be processed. It should be noted that the number of the pixel points to be processed may be adjusted according to the actual situation, for example, 4.

3. And determining the second reference pixel point information of the pixel point to be processed as pixel point information to be processed.

4. And carrying out pixel prediction based on the pixel point information to be processed and the compensation coefficient group to obtain the predicted pixel block information.

In some embodiments, the number of compensation coefficients in the set of compensation coefficients is the same as the number of pixel point information to be processed; and the compensation coefficients are in one-to-one correspondence with the pixel point information to be processed.

In some embodiments, the step of performing pixel prediction based on the pixel point information to be processed and the compensation coefficient set to obtain the predicted pixel block information includes:

1. and obtaining a compensation value based on the compensation coefficient and a preset adjustment item, wherein the compensation coefficient corresponds to the adjustment item one by one.

2. And determining the product of the compensation value and the corresponding pixel point information to be processed as an intermediate pixel value.

3. And determining the sum value among all the intermediate pixel values as the pixel information of the current predicted pixel point.

It should be noted that, the mathematical expression for obtaining the pixel information of the predicted pixel point is:

b2(R、G、B)=（0.2+T1）a2(R、G、B)+（0.5+ T2）/>a3(R、G、B)+（0.2+ T3）/>a4(R、G、B)+(0.1+T4)/>a6(R、G、B)…

wherein b2 (R, G, B) represents pixel information of the current predicted pixel point, 0.2, 0.5 and 0.1 are respectively set adjustment items, and the adjustment items are empirical values and can be adaptively adjusted or modified according to actual conditions. a2 (R, G, B), a3 (R, G, B), a4 (R, G, B) and a6 (R, G, B) are all pixels adjacent to the current predicted pixel.

4. And determining pixel information of all the predicted pixel points as the predicted pixel block information.

In some embodiments, the step of obtaining the compensation value based on the compensation coefficient and a preset adjustment term includes:

In some embodiments, the pixel point information to be processed includes: and R, G, B pixel values of the three channels of the pixel points to be processed.

Further, the step of determining the product between the compensation value and the corresponding pixel point information to be processed as an intermediate pixel value includes:

In some embodiments, further comprising:

1. and under the condition that the first reference pixel point information and the second reference pixel point information are determined to be the same, determining that the previous frame image and the current frame image are in a relative static state.

2. And under the condition that the previous frame image and the current frame image are determined to be in the relative static state, determining that all compensation coefficients in a compensation coefficient group are 0, wherein the compensation coefficients are used for carrying out shift compensation when pixel prediction is carried out.

In some embodiments, further comprising:

under the condition that the acquisition of the predicted pixel value fails, feeding back the existing image pixel information in the video memory to the host; and determining that the predicted pixel value acquisition fails under the condition that the current frame image is determined to be the first frame image in the continuous frame images.

The video memory bandwidth optimization device provided by the invention is described below, and the video memory bandwidth optimization device described below and the video memory bandwidth optimization method described above can be referred to correspondingly.

Referring to fig. 7, the video memory bandwidth optimization apparatus provided in this embodiment includes:

an address reading module 710 for reading the read video memory address and the write video memory address of the video memory respectively;

a determining module 720, configured to determine that the video memory bandwidth is insufficient if it is determined that the read video memory address is greater than the write video memory address;

an optimizing module 730, configured to, in case that it is determined that the video memory bandwidth is insufficient, feed back predicted pixel block information of the current frame image to the host for performing pixel display; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information. The address reading module 710, the determining module 720 and the optimizing module 730 are connected. The video memory bandwidth optimization device in the embodiment can compensate the problem of insufficient video memory bandwidth by feeding back the predicted pixel block information under the condition of insufficient video memory bandwidth, ensure smooth display pictures, avoid the problems of flower points, black points and the like, have higher stability, ensure the visual experience of users, have lower cost and have higher practicability.

In some embodiments, further comprising: the pixel point information writing module to be written is used for writing the pixel point information to be written carried by the pixel point information writing command into a preset pixel line buffer area under the condition that the pixel point information writing command is received; the pixel line buffer area is used for buffering the pixel point information to be written of the preset line number of the latest frame image; the pixel point information to be written in the preset line number is written in the pixel line buffer area, and meanwhile, the history cache pixel point information in the pixel line buffer area is cleared; the pixel point information to be written in the pixel line buffer area is the second cache pixel information;

In some embodiments, further comprising: the first buffer pixel information buffer module is used for sampling pixel points of the pixel line buffer area according to a preset sampling frequency so as to obtain pixel point information of a complete frame of image;

In some embodiments, further comprising: the pixel value prediction module is used for periodically collecting the first cache pixel information from the data sampling buffer area and collecting the second cache pixel information from the pixel line buffer area according to a preset prediction period;

In some embodiments, the optimizing module 730 is specifically configured to send a prediction control signal to a preset selector when it is determined that the video memory bandwidth is insufficient; the prediction control signal is used for indicating the selector to read the predicted pixel block information from the predicted pixel buffer area based on the prediction control signal, and feeding the predicted pixel block information back to a host for pixel display.

In some embodiments, the pixel value prediction module is specifically configured to obtain a target buffer size based on a size of a predicted pixel block and a preset downsampling multiple, where the target buffer size is a size obtained by downsampling the predicted pixel block based on the downsampling multiple;

In some embodiments, the pixel value prediction module is further specifically configured to obtain a plurality of overlapping pixel block groups by performing a unit translation operation on the first reference pixel block for a plurality of times when there is a difference between the first reference pixel point information and the second reference pixel point information; the number of times of translating the first reference pixel block is the same as the number of preset target translation directions; each time the first reference pixel block is subjected to unit translation operation, the first reference pixel block is controlled to translate a pixel point in any target translation direction; the overlapping pixel block group includes: a first overlapping pixel block and a second overlapping pixel block, wherein the first overlapping pixel block refers to a pixel block which is overlapped with the existence position of the second reference pixel block in the first reference pixel block after unit translation, and the second overlapping pixel block refers to a pixel block which is overlapped with the existence position of the first reference pixel block after unit translation in the second reference pixel block;

In some embodiments, the pixel value prediction module is further specifically configured to obtain first overlapping pixel point information of the first overlapping pixel block and second overlapping pixel point information of the second overlapping pixel block based on the overlapping pixel block group, the first reference pixel point information, and the second reference pixel point information;

In some embodiments, the pixel value prediction module is further specifically configured to perform difference calculation on the pixel value of the first overlapping pixel point and the pixel value of the second overlapping pixel point at the corresponding position to obtain an intermediate offset value, where the number of the intermediate offset values is the same as the number of the first overlapping pixel points or the number of the second overlapping pixel points;

In some embodiments, the pixel value prediction module is further specifically configured to determine a minimum value of all the pixel deviation values as a target pixel deviation value;

In some embodiments, the pixel value prediction module is further specifically configured to obtain, based on the image motion vector direction, a compensation coefficient set corresponding to the image motion vector direction;

In some embodiments, the pixel value prediction module is further specifically configured to obtain a compensation coefficient set corresponding to the image motion vector direction based on the image motion vector direction and a preset compensation coefficient lookup table, where the compensation coefficient lookup table includes: a plurality of image motion vector directions, and the compensation coefficient sets corresponding to the image motion vector directions one by one; the compensation coefficient set includes: and the compensation coefficients are used for performing shift compensation when pixel prediction is performed.

In some embodiments, the pixel value prediction module is further specifically configured to, for any one of the predicted pixel points in the predicted pixel block, obtain a plurality of the second reference pixel points adjacent to the predicted pixel point in the second reference pixel block;

In some embodiments, the pixel value prediction module is further specifically configured to obtain a compensation value based on the compensation coefficient and a preset adjustment term, where the compensation coefficient corresponds to the adjustment term one to one;

In some embodiments, the pixel value prediction module is further specifically configured to determine a sum value between the compensation coefficient and the corresponding adjustment term as the compensation value.

In some embodiments, the pixel value prediction module is further specifically configured to multiply the compensation value with pixel values of R, G, B three channels corresponding to the pixel point to be processed, to obtain the intermediate pixel value.

In some embodiments, the pixel value prediction module is further specifically configured to determine that the previous frame image and the current frame image are in a relatively still state if the first reference pixel point information and the second reference pixel point information are determined to be the same;

The embodiment also provides a video memory bandwidth optimization system, which comprises:

the memory bandwidth optimizing apparatus according to the above, and the buffer apparatus, the buffer apparatus includes: a pixel line buffer, a data sampling buffer, a predicted pixel buffer; the selector is respectively connected with the video memory bandwidth optimizing device and the buffer device, and the video memory bandwidth optimizing device is connected with the buffer device. The video memory bandwidth optimization system in the embodiment can compensate the problem of insufficient video memory bandwidth by feeding back the predicted pixel block information under the condition of insufficient video memory bandwidth, ensures smooth display pictures, avoids the problems of flower points, black points and the like, has higher stability, ensures the impression experience of users, has lower cost and has higher feasibility.

The embodiment also provides a BMC system, including:

In order to facilitate understanding of the BMC system provided in this embodiment, as shown in fig. 8, the BMC system in this embodiment includes:

control module 820, pixel value prediction module 850, pixel line buffer 830, data sample buffer 840, predicted pixel buffer 860, selector 870, fifo (First In First Out, first-in first-out) buffer 880, and memory 810. The control module 820 and the pixel value prediction module 850 are integrated in the bandwidth optimization system of the video memory 810, and the address reading module 710, the determination module 720 and the optimization module 730 are integrated in the control module 820. Control module 820 is coupled to pixel line buffer 830, data sample buffer 840, predicted pixel buffer 860, and selector 870, respectively. The data sample buffer 840 is coupled to the predicted pixel buffer 860. The data sampling buffer 840 and the predicted pixel buffer 860 are respectively connected to the pixel value prediction module 850, and the pixel value prediction module 850 is connected to the predicted pixel buffer 860, so as to implement reading and writing to the video memory 810 and optimize the bandwidth of the video memory 810. The data line buffer and fifo buffer 880 are connected to the video memory 810, respectively, and the predicted pixel buffer 860 and fifo buffer 880 are connected to the selector 870, respectively. The selector 870 and the control module 820 are respectively connected to the host.

Fig. 9 illustrates a physical schematic diagram of an electronic device, as shown in fig. 9, which may include: processor 910, communication interface (Communications Interface), memory 930, and communication bus 940, wherein processor 910, communication interface 920, and memory 930 communicate with each other via communication bus 940. Processor 910 can invoke logic instructions in memory 930 to perform a memory bandwidth optimization method comprising: reading a read video memory address and a write video memory address of the video memory respectively; under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient; under the condition that the video memory bandwidth is insufficient, the predicted pixel block information of the current frame image is fed back to a host computer so as to display pixels; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information.

Further, the logic instructions in the memory 930 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method for optimizing a video memory bandwidth provided by the above methods, the method comprising: reading a read video memory address and a write video memory address of the video memory respectively; under the condition that the read video memory address is larger than the write video memory address, determining that the video memory bandwidth is insufficient; under the condition that the video memory bandwidth is insufficient, the predicted pixel block information of the current frame image is fed back to a host computer so as to display pixels; the predicted pixel block information comprises predicted pixel point information with preset quantity; the predicted pixel block information is obtained by: and carrying out pixel prediction based on the first cache pixel information of the previous frame image and the second cache pixel information of the current frame image to obtain the predicted pixel block information.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The method for optimizing the video memory bandwidth is characterized by comprising the following steps of:

2. The video memory bandwidth optimization method according to claim 1, further comprising:

3. The video memory bandwidth optimization method according to claim 2, further comprising:

4. The video memory bandwidth optimization method according to claim 3, further comprising:

5. The method according to claim 4, wherein the step of feeding back predicted pixel block information of the current frame image to the host for pixel display in the case where it is determined that the video memory bandwidth is insufficient comprises:

6. The method for optimizing video memory bandwidth according to claim 1 or 4, wherein the step of performing pixel prediction based on the first buffered pixel information and the second buffered pixel information to obtain the predicted pixel block information comprises:

7. The video memory bandwidth optimization method according to claim 6, wherein the step of determining the image motion vector direction in the case where there is a difference between the first reference pixel point information and the second reference pixel point information comprises:

8. The method of claim 7, wherein the step of obtaining pixel offset values between the first reference pixel block and the second reference pixel block in each of the overlapping pixel block groups based on the overlapping pixel block groups, the first reference pixel point information, and the second reference pixel point information comprises:

9. The method for optimizing video memory bandwidth according to claim 8, wherein the first coincident pixel point information includes: pixel values of a plurality of first coincident pixel points; the second overlapping pixel point information includes: pixel values of a plurality of second overlapping pixels;

10. The video memory bandwidth optimization method according to claim 7, wherein the step of determining the image motion vector direction based on the pixel deviation value comprises:

11. The video memory bandwidth optimization method according to claim 6, wherein the step of performing pixel prediction based on the image motion vector direction to obtain the predicted pixel block information includes:

12. The video memory bandwidth optimization method according to claim 11, wherein the step of obtaining a compensation coefficient group corresponding to the image motion vector direction based on the image motion vector direction comprises:

13. The video memory bandwidth optimization method according to claim 11, wherein the step of performing pixel prediction based on the compensation coefficient set and the second reference pixel point information to obtain the predicted pixel block information includes:

14. The method for optimizing video memory bandwidth according to claim 13, wherein the number of compensation coefficients in the compensation coefficient group is the same as the number of pixel information to be processed; and the compensation coefficients are in one-to-one correspondence with the pixel point information to be processed.

15. The video memory bandwidth optimization method according to claim 14, wherein the step of performing pixel prediction based on the pixel point information to be processed and the compensation coefficient group to obtain the predicted pixel block information includes:

16. The video memory bandwidth optimization method according to claim 15, wherein the step of obtaining the compensation value based on the compensation coefficient and a preset adjustment term comprises:

17. The video memory bandwidth optimization method according to claim 15, wherein the pixel point information to be processed includes: pixel values of R, G, B three channels of the pixel point to be processed;

18. The video memory bandwidth optimization method according to claim 6, further comprising:

19. A video memory bandwidth optimization apparatus, comprising:

20. A video memory bandwidth optimization system, comprising:

the memory bandwidth optimization device of claim 19, and a buffering device, the buffering device comprising: a pixel line buffer, a data sampling buffer, a predicted pixel buffer; the selector is respectively connected with the video memory bandwidth optimizing device and the buffer device, and the video memory bandwidth optimizing device is connected with the buffer device.

21. A BMC system, comprising:

the video memory, and the video memory bandwidth optimization system according to claim 20, wherein the video memory is connected to the video memory bandwidth optimization system.

22. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the memory bandwidth optimization method of any one of claims 1 to 18 when the program is executed by the processor.

23. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the memory bandwidth optimization method of any of claims 1 to 18.