CN104268098A - On-chip cache system for transformation on ultrahigh-definition video frame rates - Google Patents
On-chip cache system for transformation on ultrahigh-definition video frame rates Download PDFInfo
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Abstract
The invention provides an on-chip cache system for transformation on ultrahigh-definition video frame rates. The on-chip cache system comprises an access request control module, an on-chip memory array and a data alignment module, wherein the access request control module is responsible for arbitrating external data read and write requests and mapping motion vectors labeled with access requests into address information of data on the on-chip memory array; the on-chip memory array is used for caching image metadata in a search window of a reference frame during transformation on the ultrahigh-definition video frame rates and updating new image metadata from an off-chip memory array in real time, and random accessing and caching of image element blocks different in specification is realized; the data alignment module is used for extracting the effective image metadata after the image metadata are outputted from the on-chip memory array and optimizing organization form of the outputted image metadata by the aid of common characters among the image element blocks different in specification, and logic reuse is achieved. By the on-chip cache system, data throughput rate of the system can be greatly increased, and average access delay and off-chip accessing and caching bandwidth of the system are lowered.
Description
Technical field
The present invention relates to Video post-processing field, particularly, relate to a kind of on the sheet of ultra high-definition video frame rate upconversion caching system.
Background technology
In recent years, people facilitate the flourish of ultra high-definition television industries jointly to the subjective demand of high-quality visual enjoyment and the objective condition of semiconductor technology fast development.But due to the restriction of current transmission system bandwidth, ultra high-definition TV programme can only be transmitted with lower frame per second.Meanwhile, the refresh rate of large-screen display equipment has again larger lifting, and video frame rate is lower than screen refresh rate, and this mismatch directly causes image to occur smear, pause, the phenomenon such as fuzzy, and display effect is not good.Video frame rate upconversion technology, as important Video post-processing means, effectively can promote the frame per second of display video, the display screen of high refresh rate improves the subjective quality of image.
The input of ultra high-definition video frame rate upconversion IP kernel is one group of image sequence fixing frame per second, and after range of motion estimation, vector aftertreatment and interpolating operations, its output is the image sequence of one group of higher frame per second.Wherein estimation, vector aftertreatment and interpose module are based on the piecemeal reduced step by step, need use the pel data in a large number from forward reference frame and backward reference frame.On the one hand, if when needing pel data at every turn just externally memory device send request of data, returning from transmiting a request to data the delay that there is the long period, work efficiency and the system frequency of whole circuit will be affected greatly; On the other hand, there is certain correlativity and repeatability in the Pixel Information required for different access request, to the reading repeatedly of identical data and repeatedly long-time the delay will waste more rnultidock cycle.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, can realize accessing the optimum of buffer memory on sheet, significantly to reduce the outer memory bandwidth of average Memory accessing delay and sheet.
For realizing above object, the invention provides a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, described system comprises request of access control module, on-chip memory array and alignment of data module, wherein:
Described request of access control module, in ultra high-definition video frame rate upconversion system, receives the access request from other module on sheet and sheet external memory module, produces memory access address and read-write enable signal, is optimized scheduling to buffer memory;
Described on-chip memory array, be coupled to described request of access module, for in ultra high-definition video frame rate upconversion system, pel data in storage of reference frames search window, and carry out accessing operation according to memory access address and read-write enable signal, comprising: saved system is from the new data of real-time update sheet; When carry out block-based estimation, vector refinement and interpolating operations time, export the pixel blocks of data of different size corresponding to each operation;
Described alignment of data module, be coupled to described request of access module and described on-chip memory array, according to the control information from described request of access module, export pel data from described on-chip memory array and select valid data and by row alignment, and the output form of different size pixel block is reset, multiplexing with realizing circuit.
Preferably, described request of access control module is according to writing preferential policy response access request, and the outer pel data of preferential guarantee sheet can real-time update.
More preferably, described request of access control module is when after the outer write request of receiving sheet, and read operation streamline is out of service, until more new data writes into memory array.
More preferably, described request of access control module produces memory access address and chip selection signal according to estimation, vector aftertreatment and interpolation three kinds of various level motion vectors.
Preferably, described request of access control module comprises sequence and divides module, coordinate mapping module, image boundary clipping module, search window coordinate calculation module and chip select address computing module, wherein:
Described sequence divides module, after receiving request of access, the pixel block that request of access needs is split as some less sub-block process, to alleviate the pressure of inside modules bandwidth; Be numbered the rule of each sub-block according to setting, this numbering exports along with the streamline of described request of access control module transmits always backward;
Described coordinate mapping module, after receiving described number information, is mapped as coordinate corresponding in image and exports by the position of request of access indication;
Described image boundary clipping module, for receive described coordinate mapping module coordinate after, the request vector exceeding image boundary is carried out border amplitude limit, and the request vector after output violent change;
Described search window coordinate calculation module, for receive described image boundary clipping module amplitude limit after request vector after, be mapped as the logical coordinates of on-chip memory array and amplitude limit to search window horizontal boundary and vertical border, this logical coordinates is exported simultaneously;
Described chip select address computing module, for receive described search window coordinate calculation module logical coordinates after, according to this logical coordinates and numbering, the logical coordinates of on-chip memory is converted into logical address and chip selection signal.
Preferably, described upper storage array, the pel data in the search window of always buffer memory current block group, and maintain the scope of search window.
More preferably, described upper storage array, when processing current block group, upgrades the new pel data of write process needed for next block group, to reduce the reading of repeating data, reduces the outer bandwidth of sheet.
More preferably, described on-chip memory array, supports that 8*128bit data upgrade simultaneously; Support that maximum 12*128bit data read simultaneously; Support that the pixel block of different size exports, comprise estimation 3*33pixs/cc, vector refinement 5*17pixs/cc and interpolation 5*9pixs/cc.
Preferably, described alignment of data module comprises reordering module and data calibration module, wherein:
Described reordering module, for receiving the pixel blocks of data of the different sizes of described on-chip memory array, resets it, and the pixel block forming Unified Form exports;
Described data calibration module, for receiving the pixel blocks of data of the Unified Form of described reordering module, the pixel of locating this pixel block left margin on said sheets memory array exports the position in pixel block, selects valid data with this.
Compared with prior art, the present invention has following beneficial effect:
1, real-time update pel data, reduces the write of repeating data, thus reduces chip external memory bandwidth;
2, take to write preferential access strategy, ensure that system high efficiency runs;
3, support the output of the block of pixels of variable-size, improve system throughput, reduce system Memory accessing delay;
4, rearrangement is exported to difference, improve the multiplexing of circuit, reduce system resource.
To sum up, the present invention can the data throughput of significantly elevator system, reduces Average access delay and the outer memory bandwidth of sheet of system.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is one embodiment of the invention system chart;
Fig. 2 is one embodiment of the invention request of access control module structured flowchart;
Fig. 3 is one embodiment of the invention on-chip memory array storage unit A and B;
Fig. 4 is the storage unit array mode schematic diagram of one embodiment of the invention storer;
Fig. 5 is the address computation schematic diagram of one embodiment of the invention storer;
Fig. 6 is one embodiment of the invention data rearrangement schematic diagram.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some distortion and improvement can also be made.These all belong to protection scope of the present invention.
As shown in Figure 1, the present embodiment provide a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, comprise request of access control module, on-chip memory array and alignment of data module.
Described request of access control module, in ultra high-definition video frame rate upconversion system, receives the access request from other module on sheet and sheet external memory module, produces memory access address and read-write enable signal, is optimized scheduling to buffer memory;
Described on-chip memory array, be coupled to described request of access module, for in ultra high-definition video frame rate upconversion system, pel data in storage of reference frames search window, and carry out accessing operation according to memory access address and read-write enable signal, comprising: saved system is from the new data of real-time update sheet; When carry out block-based estimation, vector refinement and interpolating operations time, export the pixel blocks of data of different size corresponding to each operation;
Described alignment of data module, be coupled to described request of access module and described on-chip memory array, according to the control information from described request of access module, export pel data from described on-chip memory array and select valid data and by row alignment, and the output form of different size pixel block is reset, multiplexing with realizing circuit.
As shown in Figure 2, in one embodiment, described request of access control module, comprises sequence and divides module, coordinate mapping module, image boundary clipping module, search window coordinate calculation module and chip select address computing module, wherein:
Described sequence divides module, after receiving request of access, the pixel block that request of access needs is split as some less sub-block process, to alleviate the pressure of inside modules bandwidth; Particularly, be numbered according to rule each sub-block, the pixel block as the 33*33 size of estimation being accessed is divided into the sub-block of overlapping 3*33, in order 0-15 numbering, and this numbering exports along with the streamline of this request of access control module transmits always backward.
Described coordinate mapping module, after receiving described number information, is mapped as coordinate corresponding in image and exports by the position of request of access indication; This coordinate is obtained by the offset addition that starting point coordinate, access vector and sub block number are corresponding.
Described image boundary clipping module, after receiving described coordinate, carries out border amplitude limit by the request vector exceeding image boundary, and the coordinate after output violent change;
Described search window coordinate calculation module, after receiving the coordinate after described amplitude limit, be mapped as the logical coordinates of on-chip memory and amplitude limit to search window horizontal boundary and vertical border, this logical coordinates is exported simultaneously;
Described chip select address computing module, after receiving described logical coordinates, is converted into logical address and chip selection signal according to this logical coordinates and numbering by the logical coordinates of on-chip memory.
In the present embodiment, described request of access control module, in frame rate up-conversion process, receives read-write requests according to writing preferential principle.The Data Update request of external memory is random, and when it is effective, read pipeline stops, response write request.
In the present embodiment, described request of access control module, while sending request of data to array ram on sheet, the skew of valid data in output word can be passed to alignment of data module in advance, this side-play amount is for characterizing the position of pixel in array ram output block of required block of pixels left margin.
In the present embodiment, described on-chip memory array, in frame rate up-conversion process, the pel data in memory search window, comprises the brightness of RELATED APPLICATIONS frame, chroma data.
In example of the present invention, as a kind of embodiment, described on-chip memory array meets following data throughput and requires: at motion estimation stage, the pixel block of 33*33 size will be divided into the sub-block of 3*33, sub-block number totally 16; Each motion estimation operation needs reading 3 row data in the single cycle, each row of data comprises 33 pixels; At vector elaboration phase, the block of pixels of 17*17 size will be divided into the sub-block of 1*17 and 4*17, sub-block number totally 5; Need reading 4 row data in each vector Refinement operation single cycle, each row of data comprises 17 pixels; In the interpolating operations stage, the pixel block of 9*9 size will be divided into the sub-block of 5*9, sub-block number totally 2; Each interpolating operations needs reading 5 row data in the single cycle, each row of data comprises 9 pixels.In order to meet the demand of above digital independent aspect and Data Update aspect and reduce RAM hardware resource consumption simultaneously as far as possible, the present invention establishes following mapping between image and physical store, as shown in Figure 3: it is 4 128bit words that every two field picture is divided into width, is highly the block of pixels of 4 row; Use RAM that 16 bit wides are 128bit to form to be highly the storage unit of 4 row, be often capablely combined into 512bit by 4 RAM; The Pixel Information of each buffer unit corresponding stored block of pixels; In order to meet the demand reading 5 row Pixel Information simultaneously, vertical direction consecutive storage unit offsets 2 words.If storage unit is placed in represent above-mentioned mapping relations on a two field picture, then in horizontal direction, A (or B) repeated arrangement; On vertical direction, A and B is alternately arranged.Sets forth the possible sheet choosing combination meeting estimation, vector refinement and interpolating operations read request as shown in Figure 4 in black box, wherein line number be 3,4,5 black box represent sheet choosing combination corresponding to estimation, vector refinement and interpolating operations respectively.
In example of the present invention, as a kind of embodiment, the brightness of same pixel and chrominance information are kept in identical RAM, to totally 32 RAM before and after total; Forward direction or backward 16 RAM share same read/write address.Access unit address maps as shown in Figure 5.
In example of the present invention, as a kind of embodiment, as shown in Figure 4, the sheet choosing that estimation, vector refinement and interpolation read requests are corresponding and output are:
Estimation: 4-15 RAM chip selection signal is drawn high, exports the pel data of 3*4*128bit;
Vector refinement: 1,2,3,5,6,7,9,10,11,12,13, No. 15 RAM chip selection signals are drawn high, exports the pel data of 4*3*128bit;
Interpolation: 0,3,4,5,6,7,9,10,13,14, exports 5*2*128bit pel data.
In the present embodiment, described alignment of data module comprises reordering module and data calibration module, wherein:
Described reordering module, for receiving the pixel blocks of data of the different sizes of described on-chip memory array, resets it, and the pixel block forming Unified Form exports;
Described data calibration module, for receiving the pixel blocks of data of the Unified Form of described reordering module, the pixel of locating this pixel block left margin on said sheets memory array exports the position in pixel block, selects valid data with this.
In one embodiment, described alignment of data module, according to the offset information of request of access control module transmission, export the left margin navigating to valid pixel block in pixel block, then find the right margin of valid pixel block according to the size of known pixels block and effective pixel data extracts the most at last.
Further, because each request of access motion vector is different, therefore this side-play amount completely random.In order to multiplex circuit structure as far as possible, first reset the pixel blocks of data in different operating stage, the process of rearrangement as shown in Figure 6.For the 4*3*128bit pixel blocks of data of motion estimation stage, be first rearranged to 3*4*128bit pixel block, be rearranged to 5*2*128bit pixel block further; For the 3*4*128bit pixel blocks of data in motion refinement stage, be rearranged to 5*2*128bit pixel block; For the 5*2*128bit pixel block of interpolation stage, directly export.
Further, described alignment of data module selects valid data in the final output form shown in Fig. 6.
The present embodiment a kind of caching system on the sheet of ultra high-definition video frame rate upconversion, efficient response read-write requests, real-time update data are to keep search window, and different size pixel block can be exported, realize optimal scheduling and the high-throughput of buffer memory on sheet, significantly to reduce average Memory accessing delay and the outer memory bandwidth of sheet.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (10)
1. a caching system on the sheet of ultra high-definition video frame rate upconversion, is characterized in that, described system comprises request of access control module, on-chip memory array and alignment of data module, wherein:
Described request of access control module, for receiving the access request from other module on sheet and sheet external memory module in ultra high-definition video frame rate upconversion system, producing memory access address and read-write enable signal, being optimized scheduling to buffer memory;
Described on-chip memory array, be coupled to described request of access module, for the pel data in storage of reference frames search window in ultra high-definition video frame rate upconversion system, and carry out accessing operation according to memory access address and read-write enable signal, comprising: saved system is from the new data of real-time update sheet; When carry out block-based estimation, vector refinement and interpolating operations time, export the pixel blocks of data of different size corresponding to each operation;
Described alignment of data module, be coupled to described request of access module and described on-chip memory array, according to the control information from described request of access module, export pel data from described on-chip memory array and select valid data and by row alignment, and the output form of different size pixel block is reset, multiplexing with realizing circuit.
2. according to claim 1 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described request of access control module, according to writing preferential policy response access request, preferential ensures that the outer pel data of sheet can real-time update.
3. according to claim 1 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described request of access control module is when after the outer write request of receiving sheet, and read operation streamline is out of service, until more new data writes into memory array.
4. according to claim 1 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described request of access control module produces memory access address and chip selection signal according to estimation, vector aftertreatment and interpolation three kinds of various level motion vectors.
5. a kind of according to any one of claim 1-4 caching system on the sheet of ultra high-definition video frame rate upconversion, it is characterized in that, described request of access control module comprises sequence and divides module, coordinate mapping module, image boundary clipping module, search window coordinate calculation module and chip select address computing module, wherein:
Described sequence divides module, after receiving request of access, the pixel block that request of access needs is split as some less sub-block process, to alleviate the pressure of inside modules bandwidth; Be numbered the rule of each sub-block according to setting, this numbering exports along with the streamline of described request of access control module transmits always backward;
Described coordinate mapping module, after receiving described number information, is mapped as coordinate corresponding in image and exports by the position of request of access indication;
Described image boundary clipping module, for receive described coordinate mapping module coordinate after, the request vector exceeding image boundary is carried out border amplitude limit, and the request vector after output violent change;
Described search window coordinate calculation module, for receive described image boundary clipping module amplitude limit after request vector after, be mapped as the logical coordinates of on-chip memory array and amplitude limit to search window horizontal boundary and vertical border, this logical coordinates is exported simultaneously;
Described chip select address computing module, for receive described search window coordinate calculation module logical coordinates after, according to this logical coordinates and numbering, the logical coordinates of on-chip memory is converted into logical address and chip selection signal.
6. a kind of according to any one of claim 1-4 caching system on the sheet of ultra high-definition video frame rate upconversion, is characterized in that, described upper storage array, the pel data in the search window of always buffer memory current block group, and maintains the scope of search window.
7. according to claim 6 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described upper storage array is when processing current block group, upgrade the new pel data of write process needed for next block group, to reduce the reading of repeating data, reduce the outer bandwidth of sheet.
8. according to claim 7 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described on-chip memory array, support that 8*128bit data upgrade simultaneously; Support that maximum 12*128bit data read simultaneously; Support that the pixel block of different size exports, comprise estimation 3*33pixs/cc, vector refinement 5*17pixs/cc and interpolation 5*9pixs/cc.
9. a kind of according to any one of claim 1-4 caching system on the sheet of ultra high-definition video frame rate upconversion, it is characterized in that, described alignment of data module comprises reordering module and data calibration module, wherein:
Described reordering module, for receiving the pixel blocks of data of the different sizes of described on-chip memory array, resets it, and the pixel block forming Unified Form exports;
Described data calibration module, for receiving the pixel blocks of data of the Unified Form of described reordering module, the pixel of locating this pixel block left margin on said sheets memory array exports the position in pixel block, selects valid data with this.
10. according to claim 9 a kind of on the sheet of ultra high-definition video frame rate upconversion caching system, it is characterized in that, described alignment of data module, according to the offset information of request of access control module transmission, export the left margin navigating to valid pixel block in pixel block, then find the right margin of valid pixel block according to the size of known pixels block and effective pixel data extracts the most at last; Described side-play amount completely random.
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