CN105472442B - Compressibility is cached outside a kind of piece for ultra high-definition frame rate up-conversion - Google Patents
Compressibility is cached outside a kind of piece for ultra high-definition frame rate up-conversion Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
- H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42692—Internal components of the client ; Characteristics thereof for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
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Abstract
The present invention provides a kind of pieces for ultra high-definition frame rate up-conversion to cache compressibility, including compression module and decompression module outside, wherein：The compression module, to be compressed video requency frame data of the Real Time Compression from video input and ultra high-definition video frame rate upconversion process kernel form compressed bit stream, and compressed bit stream are write outside piece in caching；The decompression module, the cache request compressed bit stream to outside piece, caching receives compressed bit stream outside piece；Block of pixels after decompression is exported block of pixels after compressed bit stream real-time decoding formation decompression to ultra high-definition video frame rate upconversion process kernel and output display module by decompression module.The outer memory bandwidth of piece can be greatly reduced in the present invention, and the data throughput of lifting system reduces the power consumption of ultra high-definition video frame rate upconversion system.
Description
Technical field
The present invention relates to field of video processing, and in particular, to is cached outside a kind of piece for ultra high-definition frame rate up-conversion
Compressibility.
Background technology
In recent years, people are total to the objective condition of subjective demand and the semiconductor technology fast development of high-quality visual enjoyment
It is same to promote flourishing for ultra high-definition television industries.However, due to the limitation of current transmission system bandwidth, ultra high-definition TV Festival
Mesh can only be transmitted with lower frame per second.At the same time, the refresh rate of large-screen display equipment has larger promotion, video frame rate again
Less than screen refresh rate, this mismatch directly results in image and phenomena such as smear, pause, obscure, poor display effect occurs.Video
Frame rate up-conversion technology can effectively promote the frame per second of display video as important Video post-processing means, refresh in height
The subjective quality of image is improved on the display screen of rate.
The input of ultra high-definition video frame rate upconversion IP kernel is the image sequence of one group of fixation frame per second, by range of motion
After estimation, vector post-processing and interpolating operations, output is the image sequence of one group of higher frame per second.This leads to ultra high-definition video frame
Rate up conversion IP kernel greatly increases with the reading and writing data throughput cached outside piece.Wherein estimation, vector post-processing and it is interior
Operation is inserted, the pel data of caching reading a large amount of forward reference frames and backward reference frame outside piece is needed；Frame rate up-conversion generates
Interpolated image sequence, need be written piece outside cache；Display output port needs to produce original sequence and frame rate up-conversion
Raw image sequence is read from being cached outside piece to be shown on the screen.
However, under current technological level, the bandwidth for storing access is difficult to meet so high read-write throughput requirement,
The outer caching bandwidth of piece becomes the bottleneck of system for restricting performance.The piece external storage data access of so high read-write throughput simultaneously,
The significant increase power consumption of ultra high-definition video frame rate upconversion IP kernel.
Invention content
For the defects in the prior art, outside the object of the present invention is to provide a kind of piece for ultra high-definition frame rate up-conversion
Compressibility is cached, caching bandwidth is greatly reduced outside ultra high-definition video frame rate upconversion piece to realize, solves the outer caching bandwidth of piece
Bottleneck problem and power problems.
In order to achieve the above object, the present invention provides caches compressibility outside a kind of piece for ultra high-definition frame rate up-conversion,
Including compression module and decompression module, wherein：
The compression module, Real Time Compression wait pressing from video input and ultra high-definition video frame rate upconversion process kernel
Contracting video requency frame data forms compressed bit stream, and compressed bit stream is write outside piece in caching；
The decompression module, the cache request compressed bit stream to outside piece, caching receives compressed bit stream outside piece；Decompress mould
Block of pixels after decompression is exported and is become on ultra high-definition video frame rate to block of pixels after compressed bit stream real-time decoding formation decompression by block
Change process kernel and output display module.
Preferably, the compression module includes：Compression blocks form module, input control module, arbitration modules, first
Sram cache module, compression kernel module, code stream output control module, address generation module, wherein：
The compression blocks form module, and effectively and under the control of input enable signal, video input is received in video input
With the video requency frame data to be compressed of ultra high-definition video frame rate upconversion process kernel, video frame to be compressed is split as several small
Sub-block forms multiple independent to be compressed pieces；
The input control module generates input enable signal under the control that compression blocks form module and arbitration modules,
The data input of video input and ultra high-definition video frame rate upconversion process kernel is controlled respectively；
The arbitration modules, according to the pressure in video input and ultra high-definition video frame rate upconversion process kernel data path
Contracting block forms the state of module, determines to be formed in module from which compression blocks and takes out to be compressed piece of the first sram cache mould of feeding
Block waits for compression processing；
The first sram cache module receives and preserves the block number evidence to be compressed from arbitration modules, then according to compression
The block number to be compressed received is compressed kernel module, to complete compression processing by the state of kernel module according to input successively；
The compression kernel module receives the block number evidence to be compressed from the first sram cache module, completes to wait pressing in real time
Compressed bit stream is exported to form compressed bit stream and gives code stream output control module by the compression processing of contracting block；
The code stream output control module receives the compressed bit stream from compression kernel module, and in address generating module
Under the collaboration for generating address, compressed bit stream is write in being cached outside piece；
It is slow outside piece to generate current compression code stream by the storage strategy cached outside frame plot and piece for described address generation module
Address in depositing, while under the control of address signal, address being written by address bus outside piece and is cached.
It is highly preferred that multiple described to be compressed pieces independent progress compression processings, do not depend between each other；It is waited for described in each
Compression blocks are respectively formed the compressed bit stream of a regular length.
It is highly preferred that in the case where the compression blocks form module and can receive data, the input control module control
Video input and ultra high-definition video frame rate upconversion process kernel input data；Forming module in the compression blocks cannot temporarily connect
In the case of receiving data, the input control module control video input and the pause of ultra high-definition video frame rate upconversion process kernel
Input data.
Preferably, the decompression module includes：Code stream request module, code stream receiving module, the second sram cache mould
Block, decoding kernel module, output control module, display format conversion module and display control module, wherein：
The code stream request module requires number according to output display module and ultra high-definition video frame rate upconversion process kernel
According to the characteristics of and the second sram cache module state, generate the address that is cached outside piece of compressed bit stream, and control and believe in address
Number control under, by address by address bus be written piece outside cache, the cache request compressed bit stream to outside piece；
The code stream receiving module, in code stream request module to outside piece after cache request compressed bit stream, detection data control
Signal processed receives the compressed bit stream on data/address bus in time, and continuous two 256bit, which are assembled into a complete 512bit, to press
Contracting code stream, and the second sram cache module is written into this code stream, wait for decoding process；
The second sram cache module, receives the compressed bit stream of code stream receiving module, and stores it on piece SRAM
In, code stream is exported successively when the decoding kernel module free time can receive code stream and gives decoding kernel module, is decoded processing；
The decoding kernel module receives the compressed bit stream from the second sram cache module, completes compressed bit stream in real time
Decoding process, form block of pixels after decompression, and block of pixels after decompression be sent to output control module；
The output control module gives ultra high-definition video by being exported from block of pixels after the decompression that decoding kernel module receives
Frame rate up-conversion process kernel and output display module；
The display format conversion module will decompress after image according to the data bus protocol between output display module
Plain block is split, and obtains data to be displayed, and this data to be displayed is exported by data/address bus and gives output display module, together
When generate data effectively, frame synchronization, line synchronising signal；
The display control module controls display format under the input enable signal control that output display module provides
The data of conversion module export.
It is highly preferred that only when output display module can receive data, the display format conversion module is just to defeated
Go out display module output data, while notifying the data on output display module data/address bus effective by data valid signal.
In the present invention, compression module and decompression module realize multiplexing：Two-path video frame data source (video input and
The video requency frame data to be compressed of ultra high-definition video frame rate upconversion process kernel) share the same compression module, compressed code circulation
It crosses after decompression module, block of pixels after decompression is exported and shows mould to ultra high-definition video frame rate upconversion process kernel and output
Block.Meanwhile compression, decompression module can be done in real time processing task in the present invention.
Compared with prior art, the present invention has following advantageous effect：
1, video data of the Real Time Compression from original video input and ultra high-definition video frame rate upconversion process kernel, so
It is written outside piece and caches again afterwards, write bandwidth to reduce chip external memory and write the power consumption of data；
2, then real-time decompression compressed bit stream exports aobvious to ultra high-definition video frame rate upconversion process kernel and output again
Show module, to reduce chip external memory tape reading width and read the power consumption of data；
3, all data of the outer buffer memory of piece are all compressed bit streams, therefore the capacity cached outside piece can be greatly reduced.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon：
Fig. 1 is the system block diagram of one embodiment of the invention；
Fig. 2 is the compression module structure diagram of one embodiment of the invention；
Fig. 3 is that the ultra high-definition video frame of one embodiment of the invention splits into be compressed piece of schematic diagram；
Fig. 4 defines for the bit field of video data input data bus in the compression module of one embodiment of the invention；
Fig. 5 forms signal for be compressed piece in the compression module of one embodiment of the invention；
Fig. 6 is arbitration modules resolving strategy in the compression module of one embodiment of the invention；
Fig. 7 is compression kernel compression process in the compression module of one embodiment of the invention；
Fig. 8 is the decompression module structure diagram of one embodiment of the invention；
Fig. 9 be one embodiment of the invention decompression module in decode kernel decoding process.
Specific implementation mode
With reference to specific embodiment, the present invention is described in detail.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, various modifications and improvements can be made.These belong to the present invention
Protection domain.
As shown in Figure 1, compressibility is cached outside a kind of piece for ultra high-definition frame rate up-conversion, including compression module reconciliation
Compression module, wherein：
The compression module, Real Time Compression wait pressing from video input and ultra high-definition video frame rate upconversion process kernel
Contracting video requency frame data forms compressed bit stream, and compressed bit stream is write outside piece in caching；
The decompression module, the cache request compressed bit stream to outside piece, caching receives compressed bit stream outside piece；Decompress mould
Block of pixels after decompression is exported and is become on ultra high-definition video frame rate to block of pixels after compressed bit stream real-time decoding formation decompression by block
Change process kernel and output display module.
As a preferred embodiment, the compression module, by from original video input terminal video requency frame data and come
It is grouped from the interpolation video frame data of ultra high-definition video frame rate upconversion process kernel, to form to be compressed piece, and to every
A to be compressed piece is operated, and obtains compressed bit stream, and compressed bit stream is write outside piece in caching.
Specifically, the compression module includes that compression blocks form module, input control module, arbitration modules, the first SRAM
Cache module, compression kernel module, code stream output control module and address generation module, overall architecture are as shown in Figure 2.
The compression blocks form module, and effectively and under the control of input enable signal, video input is received in video input
With the video requency frame data to be compressed of ultra high-definition video frame rate upconversion process kernel, video frame to be compressed is split as several small
Sub-block forms multiple independent to be compressed pieces.
Video frame to be compressed is split into be compressed piece of process such as Fig. 3 shown in (a), the pixel to be compressed of continuous two row, point
64 pixels and corresponding 32 Cb chromatic components and 32 Cr chromatic components of its luminance component, (a) institute in Fig. 3 are not taken
The mode of showing is combined into be compressed piece of luminance picture and to be compressed piece of coloration image.As a preferred embodiment, brightness here
It is 4 with chroma samples mode：2：2；To be compressed piece includes 128 pixels to be compressed；Each pixel is 10bit；If video input
With in frame rate up-conversion processing procedure use 4：4：4 or 4：2：0 brightness and chroma samples mode, video frame to be compressed are split into
To be compressed piece of process is respectively as shown in (b) and (c) in Fig. 3.
Described to be compressed piece, each independently carries out compression processing, does not depend between each other；Each to be compressed piece forms
The compressed bit stream of one regular length.The selection of compressed bit stream length will not only consider system throughput requirement and the outer SDRAM of piece
Performance, it is also contemplated that the distortion of compression image.Above-mentioned factor is considered, as a preferred embodiment, it is specified that each compression
Code stream length is 512bit.
The input control module generates input enable signal under the control that compression blocks form module and arbitration modules,
The data input of video input and ultra high-definition video frame rate upconversion process kernel is controlled respectively.Forming module in compression blocks can connect
In the case of receiving data, video input and ultra high-definition video frame rate upconversion process kernel input data are controlled；It cannot temporarily connect
In the case of receiving data, halt input data are controlled.Not only can guarantee that data input was too fast in this way causes data to be overflowed, but also can prevent
Input data does not cause system to dally for a long time.
As a preferred embodiment, as shown in Fig. 2, in setting video input and the processing of ultra high-definition video frame rate upconversion
The data-bus width that core and the compression blocks are formed between module is 160, and the bit field definition of the 160 bit wide data/address bus is such as
Shown in Fig. 4,4：2：When 2 sample format, the luminance component of continuous eight pixels in video frame a line is placed on data/address bus
High 80, chroma Cb component is placed on intermediate 40, chrominance C r components are placed on low 40, and only need to once transmit；4：
4：When 4 sample format, luminance component, chroma Cb component and the chrominance C r components of continuous 16 pixels in video frame a line respectively wrap
Data containing 160bit are divided into three times, transmit successively；4：2：When 0 sample format, 32 pixels in two row of video frame, brightness packet
Data containing 320bit, chroma Cb component and chrominance C r components separately include 160bit data, are divided into and transmitting three times：It transmits for the first time
The luminance component of 16 pixels of the first row, second of luminance component for transmitting second 16 pixels of row, third time transmission is to deserved
Chromatic component.In the feelings that Fig. 3 video frame to be compressed splits into be compressed piece of process and 60 bit wide data/address bus bit fields of Figure 41 define
Under condition, data are received from data/address bus, and the process for forming to be compressed piece is as shown in Figure 5.Serial number refers to number in be compressed piece in Fig. 5
According to the precedence of bus data transfer, wherein representing the luminance component of pixel without filling rectangular block, well shape is filled rectangle and is represented
The chroma Cb component of pixel, vertical-shaped filling rectangle represent the chrominance C r components of pixel.
The input control module is in following several, generation input enable signal：
1 compression blocks form the block number evidence to be compressed that module not yet receives the data/address bus from 160 bit wides；
2 compression blocks form the part block number evidence to be compressed that module has received the data/address bus from 160 bit wides, but non-whole
A block number evidence to be compressed；
3 compression blocks form module and have received entire block number evidence to be compressed, and arbitration modules transmit all to be compressed pieces
To the first sram cache module.
Module is formed in the compression blocks and has received entire block number evidence to be compressed, and arbitration modules are not by all to be compressed pieces
In the case of being transferred to the first sram cache module, the input control module does not generate input enable signal.
The arbitration modules, according to the pressure in video input and ultra high-definition video frame rate upconversion process kernel data path
Contracting block forms the state of module, determines to be formed in module from which compression blocks and takes out to be compressed piece of the first sram cache mould of feeding
Block waits for compression processing.On the one hand the resolving strategy of arbitration modules will consider the state that compression blocks are formed, on the other hand also
The characteristics of considering cache writing data outside piece improves data and writes efficiency.
It as a preferred embodiment, is cached outside piece and uses SDRAM, and each timeticks are set and transmit 32byte
(256bit) data, the number that transmission data is write per secondary burst is 8, i.e. address tunnel often exports primary address, and data channel is defeated
Go out the data of 8 256bit.Under the above embodiment, resolving strategy is as shown in fig. 6,4 of wherein same data path wait for
Compression blocks may be split into the data of 8 256bit, can a secondary burst write in SDRAM, therefore 4 of same data path are waited for
Compression blocks are defined as a beat；In one beat, processed number of blocks to be compressed is more all the way for certain, this road is known as current beat
Data path；In beat, the processed number of blocks to be compressed of two-way is identical (including being simultaneously zero), then kernel processes are to work as prosthomere
Beat of data access.The difference that transmission data number is write according to the bit wide of caching SDRAM outside the piece of use and the burst of support, can adopt
Take other modes, to be compressed piece of the number that each beat includes in corresponding resolving strategy also converts accordingly.
The first sram cache module receives the block number evidence to be compressed from arbitration modules, and preserves block number to be compressed
According to, then according to the state of compression kernel module, the block number to be compressed of reception is compressed into kernel module according to input successively, to complete to press
Contracting is handled.
The compression kernel module receives the block number evidence to be compressed from the first sram cache module, completes to wait pressing in real time
The compression processing of contracting block forms compressed bit stream, and compressed bit stream is exported.
As a preferred embodiment, the compression process of the compression kernel module is as shown in fig. 7, its processing procedure
It is packaged including prediction, quantization, inverse quantization and pixel reconstruction, entropy coding, code stream, simplified compression processing and compressed bit stream are formed.Tool
Body：
128 of each to be compressed piece pixels to be compressed are carried out group pixels, are then predicted by the prediction module
With residual noise reduction, the residual error of each pixel to be compressed is obtained.
The residual error of pixel to be compressed obtained by prediction module is passed through quantification treatment by the quantization modules, obtains picture to be compressed
Residual error after the quantization of element.
The inverse quantization and pixel rebuild module and residual error after the quantization of pixel to be compressed are carried out inverse quantization processing and pixel
Reconstruction process obtains the reconstructed value of pixel, is used when being predicted for prediction module.
Residual error carries out entropy coding, pixel residual error after being encoded after the entropy code module quantifies pixel.The present invention is real
In example, as a kind of embodiment, entropy coding mode is encoded using golomb.
Pixel residual values after entropy coding are carried out packing processing, form subcode after being packaged by the code stream packetization module successively
Stream.
The simplified compressing processing module treats compression blocks and carries out simple compression processing, and the code stream length of generation is fixed,
And centainly meet compression ratio requirement.Simplify compressing processing module generate code stream be used as candidate bit stream, by prediction, quantify,
When the code stream of the processing such as entropy coding cannot meet compression ratio requirement, carry out shape using the compression result for simplifying compressing processing module
At compressed bit stream.
The compressed bit stream forms module under compression ratio requirement, controls the length of the compressed bit stream of output, and formation waits for defeated
The compressed bit stream gone out.Module is formed in compressed bit stream, calculates the subcode stream length formed by processing such as prediction, quantizations.If sub
Code stream length is more than the length that directly transmission original pixels need, then subcode stream is substituted for original pixels, then subcode stream is beaten
It is bundled into a code stream.If the length of this code stream meets compression ratio requirement, uses this code stream as code stream after compression, otherwise use
The candidate bit stream of specially treated generation is had compressed as code stream after compression.
The code stream output control module receives the compressed bit stream from compression kernel module, and in address generating module
Under the collaboration for generating address, compressed bit stream is write in being cached outside piece.
As a preferred embodiment, caching uses SDRAM outside described；Address tunnel often exports primary address, data
Channel exports the data of 8 256bit.Under the above embodiment, code stream after bite rate control module compresses the 512bit of reception
The code stream section of two 256bit is split into, and to coming from video input data path and the processing of ultra high-definition video frame rate upconversion
The compressed bit stream of Nuclear Data access is separately handled.When certain reaches 4 compressed bit streams, i.e. 8 256bit code stream sections all the way, control
Address generation module writes out the address stored during 4 compressed bit streams cache outside piece, and under the control of data controlling signal,
This 4 compressed bit streams are written out in being cached outside piece.
It is slow outside piece to generate current compression code stream by the storage strategy cached outside frame plot and piece for described address generation module
Address in depositing, while under the control of address signal, address being written by address bus outside piece and is cached.
As a preferred embodiment, as shown in figure 8, the decompression module caches outside piece reads compressed bit stream,
Real-time decoding is carried out, forms block of pixels after decompression, and block of pixels after decompression is exported and gives the processing of ultra high-definition video frame rate upconversion
Kernel and output display module；The decompression module includes code stream request module, code stream receiving module, the second sram cache mould
Block, decoding kernel module, output control module, display format conversion module and display control module.
The code stream request module requires number according to output display module and ultra high-definition video frame rate upconversion process kernel
According to the characteristics of and the second sram cache module state, generate the address that is cached outside piece of compressed bit stream, and control and believe in address
Number control under, by address by address bus be written piece outside cache, the cache request compressed bit stream to outside piece.
The code stream receiving module, in code stream request module to outside piece after cache request compressed bit stream, detection data control
Signal processed receives the compressed bit stream data on data/address bus in time, and continuous two 256bit are assembled into one completely
512bit code streams, and the second sram cache module is written into this code stream, wait for decoding process.
The second sram cache module, the code stream output and decoding kernel for mainly solving code stream receiving module can receive code
Flow the mismatch between the moment.The second sram cache module receives the code stream of code stream receiving module, stores it on piece
In SRAM, when the decoding kernel module free time can receive code stream, code stream being exported give decoding kernel module successively, being decoded place
Reason；The second sram cache module can also refer to the state notifying code stream request module of itself on piece SRAM to piece for it simultaneously
Outer cache request code stream prevents on piece SRAM spillings or long-time for sky.
The decoding kernel module receives the compressed bit stream from the second sram cache module, completes compressed bit stream in real time
Decoding process, form block of pixels after decompression, and give the block of pixels to output control module.
The output control module exports block of pixels after decompression to ultra high-definition video frame rate upconversion process kernel and defeated
Go out display module.
The display format conversion module will decompress after image according to the data bus protocol between output display module
Plain block is split, and obtains data to be displayed, and this data to be displayed is exported by data/address bus and gives output display module, together
When generate data effectively, frame synchronization, line synchronising signal.
The display control module controls display format under the input enable signal control that output display module provides
The data of conversion module export.Therefore, only when output display module can receive data, display format conversion module is
The data on output display module data/address bus are notified to have to output display module output data, while by data valid signal
Effect.
As a preferred embodiment, the decoding process of the decoding kernel module is as shown in figure 9, its processing procedure
Include mainly code stream analyzing, entropy decoding, inverse quantization, pixel formation, simplify compression processing decodes and block of pixels is restored etc..It is wherein simple
Change compression processing decoder module, for decoding the simplification compression processing code stream for being unsatisfactory for compression ratio requirement in compression module.Cause
It is the inverse process of compression for decompression, the decoding process for decoding kernel module is the compression of compression kernel module shown in Fig. 7
Processing procedure inverse process, specifically：
Code stream analyzing module：Compressed bit stream from the second sram cache is parsed into each independent by entropy coding
Pixel residual values, and give entropy decoder module and carry out entropy decoding process；
Entropy decoder module：It is decoded processing by the pixel residual values of entropy coding by what code stream analyzing module parsed,
Obtain decoded pixel residual values；And this pixel residual values given to inverse quantization module is further to be handled；
Inverse quantization module, the pixel residual values that entropy decoder module is decoded carry out inverse quantization processing, after obtaining inverse quantization
Pixel residual values；And it gives this residual values to pixel and forms module；
Pixel forms module：The pixel residual values that inverse quantization module is formed add its predicted value, obtain rebuilding pixel value.Institute
It states pixel and forms module using obtained reconstruction pixel value by the identical prediction process with step 1, obtain current pixel
Predicted value；
Simplify compression processing decoder module：Compressed bit stream is decoded in the way of simplifying compression processing, is solved
Reconstruction pixel value after code；
Block of pixels restoration module：Pixel forms the reconstruction pixel value that module obtains and is assembled, and obtains candidate decompression after image
Plain block；If the compressed bit stream cached outside piece is the code stream formed by simplifying compression processing, after giving up this candidate's decompression
Block of pixels, using the reconstruction pixel value obtained after the decoding of compression processing decoder module is simplified, assembling forms final decompression after image
Plain block；Otherwise use candidate decompression after image element block as block of pixels after final decompression.
System of the present invention, by by the original video frame data and interpolation in ultra high-definition frame rate up-conversion processing system
It is written outside piece and caches again after video requency frame data compression, and read compressed bit stream from being cached outside piece, exported again after decoding to super
High definition frame rate up-conversion kernel and output display module, can be greatly reduced the readwrite bandwidth of chip external memory, be greatly decreased outside piece
The capacity of caching and the data throughput for greatly improving system, while the work(of ultra high-definition video frame rate upconversion IP kernel is greatly reduced
Consumption.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can make various deformations or amendments within the scope of the claims, this not shadow
Ring the substantive content of the present invention.
Claims (9)
1. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion, which is characterized in that conciliate including compression module
Compression module, wherein：
The compression module, to be compressed regarding of the Real Time Compression from video input and ultra high-definition video frame rate upconversion process kernel
Frequency frame data form compressed bit stream, and compressed bit stream are write outside piece in caching；
The decompression module, the cache request compressed bit stream to outside piece, caching receives compressed bit stream outside piece；Decompression module pair
Compressed bit stream real-time decoding forms block of pixels after decompression, and block of pixels after decompression is exported at ultra high-definition video frame rate upconversion
Manage kernel and output display module；
The compression module includes：Compression blocks formed module, input control module, arbitration modules, the first sram cache module,
Kernel module, code stream output control module, address generation module are compressed, wherein：
The compression blocks formation module effectively and under the control of input enable signal, receives video input and surpasses in video input
Video frame to be compressed is split as several small sons by the video requency frame data to be compressed of HD video frame rate up-conversion process kernel
Block forms multiple independent to be compressed pieces；
The input control module generates input enable signal, respectively under the control that compression blocks form module and arbitration modules
Control the data input of video input and ultra high-definition video frame rate upconversion process kernel；
The arbitration modules, according to the compression blocks in video input and ultra high-definition video frame rate upconversion process kernel data path
The state of module is formed, determines to be formed in module from which compression blocks and takes out to be compressed piece of the first sram cache module of feeding,
Wait for compression processing；
The first sram cache module receives and preserves the block number evidence to be compressed from arbitration modules, then according to compression kernel
The block number to be compressed received is compressed kernel module, to complete compression processing by the state of module according to input successively；
The compression kernel module receives the block number evidence to be compressed from the first sram cache module, completes to be compressed piece in real time
Compression processing to form compressed bit stream, and compressed bit stream is exported and gives code stream output control module；
The code stream output control module receives the compressed bit stream from compression kernel module, and is generated in address generating module
Under the collaboration of address, compressed bit stream is write in being cached outside piece；
Described address generation module, in being cached outside piece by the storage strategy generation current compression code stream cached outside frame plot and piece
Address address passed through into address bus be written outside piece and cache while under the control of address signal.
2. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 1, feature exists
In multiple described to be compressed pieces independent progress compression processings do not depend between each other；Each described to be compressed piece is respectively formed one
The compressed bit stream of a regular length.
3. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 1, feature exists
In, in the case where the compression blocks form module and can receive data, the input control module control video input and superelevation
Clear video frame rate upconversion process kernel input data；The case where module cannot temporarily receive data is formed in the compression blocks
Under, the input control module control video input and ultra high-definition video frame rate upconversion process kernel halt input data.
4. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 1, feature exists
In caching uses SDRAM outside described, and each timeticks are arranged and transmit 32byte data, and transmission data is write per secondary burst
Number be 8, i.e. address tunnel often exports primary address, and data channel exports the data of 8 256bit；Corresponding arbitration plan
Slightly：4 to be compressed piece of compressed bit stream of same data path splits into the data of 8 256bit, and a secondary burst writes SDRAM
In, it is defined as a beat by 4 to be compressed piece of same data path；In one beat, certain is processed to be compressed all the way
Number of blocks is more, this road is known as current beat data path；In beat, the processed number of blocks to be compressed of two-way is identical, then kernel
Processing is current beat data path.
5. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 1, feature exists
In, caching uses SDRAM, address tunnel often to export primary address outside described, and data channel exports the data of 8 256bit,
The 512bit compressed bit streams of reception are split into the code stream section of two 256bit by bite rate control module, and to coming from video input number
It is separately handled according to the compressed bit stream of access and ultra high-definition video frame rate upconversion process kernel data path；When certain reaches 4 all the way
A compressed bit stream, i.e. 8 256bit code stream sections, control address generation module, which writes out during 4 compressed bit streams cache outside piece, to be deposited
The address of storage, and under the control of data controlling signal, this 4 compressed bit streams are written out in being cached outside piece.
6. according to compressibility is cached outside a kind of piece for ultra high-definition frame rate up-conversion of claim 1-5 any one of them,
It is characterized in that, the compression kernel module completes to be compressed piece of compression processing to form compressed bit stream, including prediction in real time
Module, quantization modules, inverse quantization and pixel rebuild module, entropy code module, code stream packetization module, simplify compressing processing module and
Compressed bit stream forms module；
Each to be compressed piece of pixel to be compressed is carried out group pixels, then carried out at prediction and residual error by the prediction module
Reason obtains the residual error of each pixel to be compressed；
The residual error of pixel to be compressed obtained by prediction module is passed through quantification treatment by the quantization modules, obtains pixel to be compressed
Residual error after quantization；
The inverse quantization rebuilds module with pixel and rebuilds residual error progress inverse quantization processing after the quantization of pixel to be compressed with pixel
Process obtains the reconstructed value of pixel, is used when being predicted for prediction module；
Residual error carries out entropy coding, pixel residual error after being encoded after the entropy code module quantifies pixel；
Pixel residual values after entropy coding are carried out packing processing, form subcode stream after being packaged by the code stream packetization module successively；
The simplified compressing processing module treats compression blocks and carries out simple compression processing, and the code stream length of generation is fixed, and one
Surely meet compression ratio requirement；Simplify the code stream of compressing processing module generation as candidate bit stream, in above-mentioned prediction module, quantization mould
When the code stream that block, entropy code module are handled cannot meet compression ratio requirement, the compression knot for simplifying compressing processing module is used
Fruit forms compressed bit stream；
The compressed bit stream forms module under compression ratio requirement, controls the length of the compressed bit stream of output, is formed to be output
Compressed bit stream；Module is formed in compressed bit stream, calculates the subcode stream length formed by prediction module, quantization modules processing, if
Subcode stream length is more than the length of directly transmission original pixels needs, then subcode stream is substituted for original pixels, then by subcode stream
It is packaged into a code stream；If the length of this code stream meets compression ratio requirement, uses this code stream as code stream after compression, otherwise make
Use the candidate bit stream for having compressed specially treated generation code stream as after compressing.
7. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 1, feature exists
In the decompression module includes：Code stream request module, code stream receiving module, the second sram cache module, decoding kernel mould
Block, output control module, display format conversion module and display control module, wherein：
The code stream request module requires data according to output display module and ultra high-definition video frame rate upconversion process kernel
The state of feature and the second sram cache module generates the address that compressed bit stream caches outside piece, and in address control signal
Under control, address is written by address bus outside piece and is cached, the cache request compressed bit stream to outside piece；
The code stream receiving module, in code stream request module to outside piece after cache request compressed bit stream, detection data control letter
Number in time receive data/address bus on compressed bit stream data, continuous two 256bit are assembled into a complete 512bit code
Stream, and the second sram cache module is written into this code stream, wait for decoding process；
The second sram cache module, receives the compressed bit stream of code stream receiving module, and stores it on piece SRAM,
Code stream is exported successively when the decoding kernel module free time can receive code stream and gives decoding kernel module, is decoded processing；
The decoding kernel module receives the compressed bit stream from the second sram cache module, completes the solution of compressed bit stream in real time
Code processing, forms block of pixels after decompression, and block of pixels after decompression is sent to output control module；
The output control module gives ultra high-definition video frame rate by being exported from block of pixels after the decompression that decoding kernel module receives
Up-conversion process kernel and output display module；
The display format conversion module, according to the data bus protocol between output display module, by block of pixels after decompression
It is split, obtains data to be displayed, and this data to be displayed is exported by data/address bus and gives output display module, produce simultaneously
Raw data effectively, frame synchronization, line synchronising signal；
The display control module, under the input enable signal control that output display module provides, control display format conversion
The data of module export.
8. caching compressibility outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 7, feature exists
In only when output display module can receive data, the display format conversion module is just to output display module output
Data, while notifying the data on output display module data/address bus effective by data valid signal.
9. caching compressibility, feature outside a kind of piece for ultra high-definition frame rate up-conversion according to claim 7 or 8
Be, the decoding kernel module completes the decoding process of compressed bit stream in real time, including code stream analyzing module, entropy decoder module,
Inverse quantization module, pixel form module, simplify compression processing decoding and block of pixels restoration module, wherein：
Code stream analyzing module：Compressed bit stream from the second sram cache is parsed into each independent pixel by entropy coding
Residual values, and give entropy decoder module and carry out entropy decoding process；
Entropy decoder module：The pixel residual values by entropy coding that code stream analyzing module parses are decoded processing, are obtained
Decoded pixel residual values；And this pixel residual values given to inverse quantization module is further to be handled；
Inverse quantization module, the pixel residual values that entropy decoder module is decoded carry out inverse quantization processing, obtain the picture after inverse quantization
Plain residual values；And it gives this residual values to pixel and forms module；
Pixel forms module：The pixel residual values that inverse quantization module is formed add its predicted value, obtain rebuilding pixel value, described
Pixel forms module and passes through with step 1 identical prediction process using obtained reconstruction pixel value, obtains current pixel
Predicted value；
Simplify compression processing decoder module：Compressed bit stream is decoded in the way of simplifying compression processing, after obtaining decoding
Reconstruction pixel value；
Block of pixels restoration module：Pixel forms the reconstruction pixel value that module obtains and is assembled, and obtains candidate decompression after image element block；
If the compressed bit stream cached outside piece is the code stream formed by simplifying compression processing, give up this candidate's decompression after image element
Block, using the reconstruction pixel value obtained after the decoding of compression processing decoder module is simplified, assembling forms block of pixels after final decompression；
Otherwise use candidate decompression after image element block as block of pixels after final decompression.
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