CN105472442A - Out-chip buffer compression system for superhigh-definition frame rate up-conversion - Google Patents
Out-chip buffer compression system for superhigh-definition frame rate up-conversion Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
- H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42692—Internal components of the client ; Characteristics thereof for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
Abstract
The invention provides an out-chip buffer compression system for superhigh-definition frame rate up-conversion, and the system comprises a compression module and a decompression module. The compression module compresses to-be-compressed video frame data from video input and a superhigh-definition frame rate up-conversion processing core, forming a compressed code stream, and enables the compressed code stream to be written into an out-chip buffer; a decompression module which requests the compressed code stream for the out-chip buffer, and receives the compressed code stream from the out-chip buffer. The decompression module carries out the real-time decoding of the compressed code stream, forms a decompressed pixel block, and enables the decompressed pixel block to be outputted to the superhigh-definition frame rate up-conversion processing core and an output display module. The method can greatly reduce the bandwidth of the out-chip buffer, improves the data throughput rate, and reduces the power consumption of an uperhigh-definition frame rate up-conversion system.
Description
Technical field
The present invention relates to field of video processing, particularly, relate to the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion.
Background technology
In recent years, people facilitate the flourish of ultra high-definition television industries jointly to the subjective demand of high-quality visual enjoyment and the objective condition of semiconductor technology fast development.But due to the restriction of current transmission system bandwidth, ultra high-definition TV programme can only be transmitted with lower frame per second.Meanwhile, the refresh rate of large-screen display equipment has again larger lifting, and video frame rate is lower than screen refresh rate, and this mismatch directly causes image to occur smear, pause, the phenomenon such as fuzzy, and display effect is not good.Video frame rate upconversion technology, as important Video post-processing means, effectively can promote the frame per second of display video, the display screen of high refresh rate improves the subjective quality of image.
The input of ultra high-definition video frame rate upconversion IP kernel is one group of image sequence fixing frame per second, and after range of motion estimation, vector reprocessing and interpolating operations, its output is the image sequence of one group of higher frame per second.This causes the reading and writing data throughput of ultra high-definition video frame rate upconversion IP kernel and the outer buffer memory of sheet to increase greatly.Wherein estimation, vector reprocessing and interpolating operations, needs buffer memory from sheet to read the pel data of a large amount of forward reference frame and backward reference frame; The interpolated image sequence that frame rate up-conversion produces, needs the outer buffer memory of write sheet; Display translation port needs original sequence and frame rate up-conversion generation image sequence to read from buffer memory sheet to show at screen.
But under current technological level, the bandwidth of memory access is difficult to meet so high read-write throughput requirement, the outer buffer memory bandwidth of sheet becomes the bottleneck of system for restricting performance.The simultaneously so sheet external memory data access of high read-write throughput, also the significant increase power consumption of ultra high-definition video frame rate upconversion IP kernel.
Summary of the invention
For defect of the prior art, the object of this invention is to provide the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion, significantly reduce to realize the outer buffer memory bandwidth of ultra high-definition video frame rate upconversion sheet, solve the outer buffer memory bandwidth bottleneck problem of sheet and power problems.
For realizing above object, the invention provides the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion, comprising compression module and decompression module, wherein:
Described compression module, Real Time Compression, from the video requency frame data to be compressed of video input and ultra high-definition video frame rate upconversion process kernel, forms compressed bit stream, and is write by compressed bit stream in the outer buffer memory of sheet;
Described decompression module, cache request compressed bit stream outside sheet, from sheet, buffer memory receives compressed bit stream; Block of pixels after decompress(ion) to block of pixels after compressed bit stream real-time decoding formation decompress(ion), and is exported to ultra high-definition video frame rate upconversion process kernel and output display module by decompression module.
Preferably, described compression module comprises: compression blocks forms module, input control module, arbitration modules, the first sram cache module, compression kernel module, code stream output control module, address generation module, wherein:
Described compression blocks forms module, at video input effectively and under the control of input enable signal, the video requency frame data to be compressed of receiver, video input and ultra high-definition video frame rate upconversion process kernel, is split as some little sub-blocks by frame of video to be compressed, forms multiple independently to be compressed piece;
Described input control module, under the control that compression blocks forms module and arbitration modules, produces input enable signal, controls the data input of video input and ultra high-definition video frame rate upconversion process kernel respectively;
Described arbitration modules, the state of module is formed according to the compression blocks in video input and ultra high-definition video frame rate upconversion process kernel data path, determine from which compression blocks to be formed module to take out to be compressed piece of feeding the first sram cache module, wait pending compression to process;
Described first sram cache module, receives and preserves the blocks of data to be compressed from arbitration modules, then according to compressing the state of kernel module, the blocks of data input compression kernel module to be compressed that will receive successively, to complete compression process;
Described compression kernel module, receives the blocks of data to be compressed from the first sram cache module, completes the compression process of to be compressed piece in real time to form compressed bit stream, and compressed bit stream is exported to code stream output control module;
Described code stream output control module, receives the compressed bit stream from compression kernel module, and under address generating module produces working in coordination with of address, is write by compressed bit stream in the outer buffer memory of sheet;
Described address generation module, generates the address of current compression code stream in the outer buffer memory of sheet by the storage policy of frame plot and the outer buffer memory of sheet, simultaneously under the control of address signal, by address by the outer buffer memory of address bus write sheet.
More preferably, multiple described to be compressed piece is all independently carried out compression process, does not rely on each other; Each described to be compressed piece all forms the compressed bit stream of a regular length.
More preferably, when described compression blocks formation module can receive data, described input control module controls video input and ultra high-definition video frame rate upconversion process kernel input data; When described compression blocks formation module temporarily can not receive data, described input control module controls video input and ultra high-definition video frame rate upconversion process kernel halt input data.
Preferably, described decompression module comprises: code stream request module, code stream receiver module, the second sram cache module, decoding kernel module, output control module, display format modular converter and display control module, wherein:
Described code stream request module, according to output display module and the feature of ultra high-definition video frame rate upconversion process kernel requests data and the state of the second sram cache module, generate the address of compressed bit stream at the outer buffer memory of sheet, and under the control of address control signal, by address by the outer buffer memory of address bus write sheet, cache request compressed bit stream outside sheet;
Described code stream receiver module, in code stream request module to after cache request compressed bit stream outside sheet, detection data controlling signal receives the compressed bit stream on data/address bus in time, continuous print two 256bit are assembled into a complete 512bit compressed bit stream, and this code stream is write the second sram cache module, wait process to be decoded;
Described second sram cache module, receives the compressed bit stream of code stream receiver module, and is stored on sheet in SRAM, successively code stream is exported to decoding kernel module when the kernel module free time of decoding can receive code stream, carries out decoding process;
Described decoding kernel module, receives the compressed bit stream from the second sram cache module, completes the decoding process of compressed bit stream in real time, block of pixels after formation decompress(ion), and block of pixels after decompress(ion) is sent to output control module;
Described output control module, exports to ultra high-definition video frame rate upconversion process kernel and output display module by block of pixels after the decompress(ion) received from decoding kernel module;
Described display format modular converter, according to the data bus protocol between output display module, block of pixels after decompress(ion) is split, obtain data to be displayed, and this data to be displayed is exported to output display module by data/address bus, produce simultaneously data effectively, frame synchronization, line synchronizing signal;
Described display control module, under the input enable signal control that output display module provides, the data controlling display format modular converter export.
More preferably, only when output display module can receive data, described display format modular converter just exports data to output display module, simultaneously effective by the data in data valid signal notice output display module data bus.
In the present invention, compression module and decompression module all achieve multiplexing: two-path video frame data source (video requency frame data to be compressed of video input and ultra high-definition video frame rate upconversion process kernel) shares same compression module, block of pixels after decompress(ion), by after decompression module, is exported to ultra high-definition video frame rate upconversion process kernel and output display module by compressed bit stream.Meanwhile, in the present invention, compression, decompression module can be done in real time Processing tasks.
Compared with prior art, the present invention has following beneficial effect:
1, Real Time Compression is from original video input and the video data of ultra high-definition video frame rate upconversion process kernel, and then writes the outer buffer memory of sheet, thus reduces chip external memory and write bandwidth and write the power consumption of data;
2, real-time decompression compressed bit stream, and then export to ultra high-definition video frame rate upconversion process kernel and output display module, thus the tape reading of reduction chip external memory is wide and the power consumption of read data;
3, all data of the outer buffer memory of sheet are all compressed bit streams, therefore significantly can reduce the capacity of the outer buffer memory of sheet.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the system block diagram of one embodiment of the invention;
Fig. 2 is the compression module structured flowchart of one embodiment of the invention;
Fig. 3 is that the ultra high-definition frame of video of one embodiment of the invention splits into be compressed piece of schematic diagram;
Fig. 4 is the bit field definition of video data input data bus in the compression module of one embodiment of the invention;
Fig. 5 is to be compressed piece of formation signal in the compression module of one embodiment of the invention;
Fig. 6 is arbitration modules resolving strategy in the compression module of one embodiment of the invention;
Fig. 7 compresses kernel compression process in the compression module of one embodiment of the invention;
Fig. 8 is the decompression module structured flowchart of one embodiment of the invention;
Fig. 9 is the decoding process of kernel of decoding in the decompression module of one embodiment of the invention.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some distortion and improvement can also be made.These all belong to protection scope of the present invention.
As shown in Figure 1, the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion, comprises compression module and decompression module, wherein:
Described compression module, Real Time Compression, from the video requency frame data to be compressed of video input and ultra high-definition video frame rate upconversion process kernel, forms compressed bit stream, and is write by compressed bit stream in the outer buffer memory of sheet;
Described decompression module, cache request compressed bit stream outside sheet, from sheet, buffer memory receives compressed bit stream; Block of pixels after decompress(ion) to block of pixels after compressed bit stream real-time decoding formation decompress(ion), and is exported to ultra high-definition video frame rate upconversion process kernel and output display module by decompression module.
As a preferred implementation, described compression module, by the video requency frame data from original video input with divide into groups from the interpolation video frame data of ultra high-definition video frame rate upconversion process kernel, to form to be compressed piece, and each to be compressed piece is operated, obtain compressed bit stream, and compressed bit stream is write in the outer buffer memory of sheet.
Particularly, described compression module comprises compression blocks and forms module, input control module, arbitration modules, the first sram cache module, compression kernel module, code stream output control module and address generation module, and its overall architecture as shown in Figure 2.
Described compression blocks forms module, at video input effectively and under the control of input enable signal, the video requency frame data to be compressed of receiver, video input and ultra high-definition video frame rate upconversion process kernel, is split as some little sub-blocks by frame of video to be compressed, forms multiple independently to be compressed piece.
Frame of video to be compressed splits into be compressed piece of process as shown in (a) in Fig. 3, the pixel to be compressed of continuous two row, get 64 pixels of its luminance component and 32 Cb chromatic components of correspondence and 32 Cr chromatic components respectively, be combined into be compressed piece of luminance picture and chromatic diagram as to be compressed piece according to mode (a) in Fig. 3 Suo Shi.As a preferred implementation, brightness here and chroma samples mode are 4:2:2; To be compressed piece comprises 128 pixels to be compressed; Each pixel is 10bit; If adopt brightness and the chroma samples mode of 4:4:4 or 4:2:0 in video input and frame rate up-conversion processing procedure, frame of video to be compressed splits into the process of to be compressed piece respectively as shown in (b) He (c) in Fig. 3.
Described to be compressed piece, each independently carry out compression process, do not rely on each other; The compressed bit stream of each to be compressed piece of formation regular length.The selection of compressed bit stream length not only will consider that system throughput requires and the outer SDRAM performance of sheet, also will consider the distortion of compressed image.Consider above-mentioned factor, as a preferred implementation, specify that each compressed bit stream length is 512bit.
Described input control module, under the control that compression blocks forms module and arbitration modules, produces input enable signal, controls the data input of video input and ultra high-definition video frame rate upconversion process kernel respectively.When compression blocks formation module can receive data, control video input and ultra high-definition video frame rate upconversion process kernel input data; When temporarily can not receive data, control halt input data.So both can ensure that data input was too fast and cause data from overflow, and can prevent again not inputting data for a long time and cause system to dally.
As a preferred implementation, as shown in Figure 2, arranging video input and ultra high-definition video frame rate upconversion process kernel and the described compression blocks data-bus width formed between module is 160, the bit field definition of described 160 bit wide data/address buss as shown in Figure 4, during 4:2:2 sample format, high 80, chroma Cb component that the luminance component of continuous eight pixels in frame of video a line is placed on data/address bus are placed on middle 40, chrominance C r component is placed on low 40, and only need once transmits; During 4:4:4 sample format, the luminance component of continuous 16 pixels in frame of video a line, chroma Cb component and chrominance C r component respectively comprise 160bit data, are divided into three times, transmit successively; During 4:2:0 sample format, 32 pixels in frame of video two row, brightness comprises 320bit data, chroma Cb component and chrominance C r component comprise 160bit data respectively, be divided into three transmission: the luminance component of first time transmission the first row 16 pixels, the luminance component of second time transmission the second row 16 pixels, third time transmits corresponding chromatic component.When Fig. 3 frame of video to be compressed splits into be compressed piece of process and the definition of Figure 41 60 bit wide data/address bus bit field, receive data from data/address bus, and the process forming to be compressed piece as shown in Figure 5.In Fig. 5, sequence number refers to the precedence of data/address bus transfer of data in be compressed piece, and wherein without the luminance component of filling rectangular block represent pixel, well shape fills the chroma Cb component of rectangle represent pixel, the chrominance C r component of vertical-shaped filling rectangle represent pixel.
Described input control module, in following several situation, produces input enable signal:
1 compression blocks forms the blocks of data to be compressed that module not yet receives the data/address bus from 160 bit wides;
2 compression blocks formation modules have received the part blocks of data to be compressed from the data/address bus of 160 bit wides, but non-whole blocks of data to be compressed;
3 compression blocks form module and have received whole blocks of data to be compressed, and all Bulk transport to be compressed are given the first sram cache module by arbitration modules.
Form module at described compression blocks and received whole blocks of data to be compressed, and when all Bulk transport to be compressed are not given the first sram cache module by arbitration modules, described input control module does not produce input enable signal.
Described arbitration modules, the state of module is formed according to the compression blocks in video input and ultra high-definition video frame rate upconversion process kernel data path, determine from which compression blocks to be formed module to take out to be compressed piece of feeding the first sram cache module, wait pending compression to process.The resolving strategy of arbitration modules will consider the state that compression blocks is formed on the one hand, also will consider the feature of the outer cache writing data of sheet on the other hand, improves data and writes efficiency.
As a preferred implementation, the outer buffer memory of sheet adopts SDRAM, and arranges each timeticks transmission 32byte (256bit) data, and the number that every secondary burst writes transmission data is 8, namely address tunnel often exports primary address, and data channel exports the data of 8 256bit.Under above-mentioned execution mode, as shown in Figure 6, wherein 4 to be compressed piece of same data path may be split into the data of 8 256bit to resolving strategy, can write in SDRAM by a secondary burst, therefore be defined as a beat by 4 of same data path to be compressed piece; In a beat, the processed number of blocks to be compressed in a certain road is many, and this road is called current beat data path; In beat, the number of blocks to be compressed identical (comprise is zero simultaneously) that two-way is processed, then kernel processes is current beat data path.Write the difference of transmission data amount check according to the outer bit wide of buffer memory SDRAM of the sheet adopted and the burst of support, can take other mode, the number of to be compressed piece that in corresponding resolving strategy, each beat comprises also converts accordingly.
Described first sram cache module, receives the blocks of data to be compressed from arbitration modules, and preserves blocks of data to be compressed, then according to compressing the state of kernel module, the blocks of data input compression kernel module to be compressed that will receive successively, processes to complete compression.
Described compression kernel module, receives the blocks of data to be compressed from the first sram cache module, completes the compression process of to be compressed piece in real time, forms compressed bit stream, and is exported by compressed bit stream.
As a preferred implementation, as shown in Figure 7, its processing procedure comprises prediction, quantification, inverse quantization and pixel reconstruction, entropy code, code stream packing, simplifies compression process and compressed bit stream formation the compression process of described compression kernel module.Concrete:
Each to be compressed piece 128 pixels to be compressed are carried out group pixels, are then carried out predicting and residual noise reduction, obtain the residual error of each pixel to be compressed by described prediction module.
The residual error of the pixel to be compressed of prediction module gained through quantification treatment, is obtained residual error after the quantification of pixel to be compressed by described quantization modules.
Described inverse quantization and pixel are rebuild module and residual error after the quantification of pixel to be compressed are carried out inverse quantization process and pixel process of reconstruction, obtain the reconstructed value of pixel, when predicting for prediction module.
After pixel quantizes by described entropy code module, residual error carries out entropy code, pixel residual error after obtaining encoding.In example of the present invention, as a kind of embodiment, entropy code mode adopts golomb to encode.
Described code stream packetization module, carries out packing process successively by pixel residual values after entropy code, form the rear subcode stream of packing.
Described simplification compression processing module, treat compression blocks and simply compress process, the code stream length of generation is fixed, and necessarily meets compression ratio requirement.The code stream alternatively code stream that simplification compression processing module produces, when the code stream through process such as prediction, quantification, entropy code can not meet compression ratio requirement, uses the compression result simplifying compression processing module to form compressed bit stream.
Described compressed bit stream forms module under compression ratio requires, controls the length of the compressed bit stream exported, forms compressed bit stream to be output.Form module at compressed bit stream, calculate the subcode stream length formed through process such as prediction, quantifications.If subcode stream length is greater than the length of directly transmission original pixels needs, then subcode stream is replaced to original pixels, then subcode stream is packaged into a code stream.If the length of this code stream meets compression ratio requirement, then use this code stream as code stream after compression, otherwise use the candidate bit stream that have compressed special processing generation as code stream after compression.
Described code stream output control module, receives the compressed bit stream from compression kernel module, and under address generating module produces working in coordination with of address, is write by compressed bit stream in the outer buffer memory of sheet.
As a preferred implementation, described outer buffer memory adopts SDRAM; Address tunnel often exports primary address, and data channel exports the data of 8 256bit.Under above-mentioned execution mode, the 512bit of reception is compressed the code stream section that rear code stream splits into two 256bit by bite rate control module, and to the separately process of the compressed bit stream from video input data path and ultra high-definition video frame rate upconversion process kernel data path.When a certain road reaches 4 compressed bit streams, i.e. 8 256bit code stream sections, control address generation module writes out the address that these 4 compressed bit streams store in the outer buffer memory of sheet, and under the control of data controlling signal, is written out to by these 4 compressed bit streams in the outer buffer memory of sheet.
Described address generation module, generates the address of current compression code stream in the outer buffer memory of sheet by the storage policy of frame plot and the outer buffer memory of sheet, simultaneously under the control of address signal, by address by the outer buffer memory of address bus write sheet.
As a preferred implementation, as shown in Figure 8, described decompression module gets compressed bit stream from cache read sheet, carries out real-time decoding, block of pixels after formation decompress(ion), and block of pixels after decompress(ion) is exported to ultra high-definition video frame rate upconversion process kernel and output display module; Described decompression module comprises code stream request module, code stream receiver module, the second sram cache module, decoding kernel module, output control module, display format modular converter and display control module.
Described code stream request module, according to output display module and the feature of ultra high-definition video frame rate upconversion process kernel requests data and the state of the second sram cache module, generate the address of compressed bit stream at the outer buffer memory of sheet, and under the control of address control signal, by address by the outer buffer memory of address bus write sheet, cache request compressed bit stream outside sheet.
Described code stream receiver module, in code stream request module to after cache request compressed bit stream outside sheet, detect data controlling signal, compressed bit stream data on timely reception data/address bus, continuous print two 256bit are assembled into a complete 512bit code stream, and this code stream is write the second sram cache module, wait process to be decoded.
Described second sram cache module, the code stream output and the decoding kernel that mainly solve code stream receiver module can receive not mating between the code stream moment.Described second sram cache module receives the code stream of code stream receiver module, is stored on sheet in SRAM, when the kernel module free time of decoding can receive code stream, successively code stream is exported to decoding kernel module, carries out decoding process; Second sram cache module also by the state notifying code stream request module of SRAM on self sheet, for it with reference to cache request code stream outside sheet, can prevent SRAM spilling or long-time for empty on sheet simultaneously.
Described decoding kernel module, receives the compressed bit stream from the second sram cache module, completes the decoding process of compressed bit stream in real time, block of pixels after formation decompress(ion), and gives output control module by this block of pixels.
Described output control module, exports to ultra high-definition video frame rate upconversion process kernel and output display module by block of pixels after decompress(ion).
Described display format modular converter, according to the data bus protocol between output display module, block of pixels after decompress(ion) is split, obtain data to be displayed, and this data to be displayed is exported to output display module by data/address bus, produce simultaneously data effectively, frame synchronization, line synchronizing signal.
Described display control module, under the input enable signal control that output display module provides, the data controlling display format modular converter export.Therefore, only when output display module can receive data, display format modular converter just exports data to output display module, simultaneously effective by the data in data valid signal notice output display module data bus.
As a preferred implementation, as shown in Figure 9, its processing procedure mainly comprises code stream analyzing, entropy decoding, inverse quantization, pixel formation, simplifies compression process decoding and block of pixels recovery etc. the decoding process of described decoding kernel module.Wherein simplify compression process decoder module, be used for decoding does not meet the simplification compression process code stream of compression ratio requirement in compression module.Be the inverse process of compression because decompress, the decoding process of decoding kernel module is the compression process inverse process of the kernel module of compression shown in Fig. 7, particularly:
Code stream analyzing module: the compressed bit stream from the second sram cache is resolved to each independently through the pixel residual values of entropy code, and give entropy decoder module carry out entropy decoding process;
Entropy decoder module: the pixel residual values through entropy code code stream analyzing module parsed carries out decoding process, obtains decoded pixel residual values; And give inverse quantization module by this pixel residual values and do further process;
Inverse quantization module, the pixel residual values gone out by entropy decoding module decodes carries out inverse quantization process, obtains the pixel residual values after inverse quantization; And this residual values is given pixel formation module;
Pixel forms module: the pixel residual values that inverse quantization module is formed adds its predicted value, obtains rebuilding pixel value.Described pixel forms module and uses the reconstruction pixel value obtained through the forecasting process identical with step one, obtains the predicted value of current pixel;
Simplify compression process decoder module: decoded according to the mode simplifying compression process by compressed bit stream, obtain decoded reconstruction pixel value;
Block of pixels restoration module: the reconstruction pixel value that pixel formation module obtains is assembled, obtains candidate's decompress(ion) after image element block; If be through the code stream simplifying compression process and formed from the compressed bit stream of buffer memory outside sheet, then give up this candidate's decompress(ion) after image element block, the reconstruction pixel value that use obtains after simplifying compression process decoding module decodes, block of pixels after the decompress(ion) that assembling formation is final; Otherwise use candidate's decompress(ion) after image element block as block of pixels after final decompress(ion).
System of the present invention, by writing the outer buffer memory of sheet again by after the original video frame data in ultra high-definition frame rate up-conversion treatment system and the compression of interpolation video frame data, and compressed bit stream is read from buffer memory sheet, ultra high-definition frame rate up-conversion kernel and output display module is exported to again after decoding, significantly can reduce the readwrite bandwidth of chip external memory, significantly reduce the capacity of the outer buffer memory of sheet and significantly improve the data throughput of system, significantly reducing the power consumption of ultra high-definition video frame rate upconversion IP kernel simultaneously.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (10)
1., for the outer buffer memory compressibility of sheet of ultra high-definition frame rate up-conversion, it is characterized in that, comprise compression module and decompression module, wherein:
Described compression module, Real Time Compression, from the video requency frame data to be compressed of video input and ultra high-definition video frame rate upconversion process kernel, forms compressed bit stream, and is write by compressed bit stream in the outer buffer memory of sheet;
Described decompression module, cache request compressed bit stream outside sheet, from sheet, buffer memory receives compressed bit stream; Block of pixels after decompress(ion) to block of pixels after compressed bit stream real-time decoding formation decompress(ion), and is exported to ultra high-definition video frame rate upconversion process kernel and output display module by decompression module.
2. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 1, it is characterized in that, described compression module comprises: compression blocks forms module, input control module, arbitration modules, the first sram cache module, compression kernel module, code stream output control module, address generation module, wherein:
Described compression blocks forms module, at video input effectively and under the control of input enable signal, the video requency frame data to be compressed of receiver, video input and ultra high-definition video frame rate upconversion process kernel, is split as some little sub-blocks by frame of video to be compressed, forms multiple independently to be compressed piece;
Described input control module, under the control that compression blocks forms module and arbitration modules, produces input enable signal, controls the data input of video input and ultra high-definition video frame rate upconversion process kernel respectively;
Described arbitration modules, the state of module is formed according to the compression blocks in video input and ultra high-definition video frame rate upconversion process kernel data path, determine from which compression blocks to be formed module to take out to be compressed piece of feeding the first sram cache module, wait pending compression to process;
Described first sram cache module, receives and preserves the blocks of data to be compressed from arbitration modules, then according to compressing the state of kernel module, the blocks of data input compression kernel module to be compressed that will receive successively, to complete compression process;
Described compression kernel module, receives the blocks of data to be compressed from the first sram cache module, completes the compression process of to be compressed piece in real time to form compressed bit stream, and compressed bit stream is exported to code stream output control module;
Described code stream output control module, receives the compressed bit stream from compression kernel module, and under address generating module produces working in coordination with of address, is write by compressed bit stream in the outer buffer memory of sheet;
Described address generation module, generates the address of current compression code stream in the outer buffer memory of sheet by the storage policy of frame plot and the outer buffer memory of sheet, simultaneously under the control of address signal, by address by the outer buffer memory of address bus write sheet.
3. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 2, is characterized in that, multiple described to be compressed piece is all independently carried out compression process, do not rely on each other; Each described to be compressed piece all forms the compressed bit stream of a regular length.
4. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 2, it is characterized in that, when described compression blocks formation module can receive data, described input control module controls video input and ultra high-definition video frame rate upconversion process kernel input data; When described compression blocks formation module temporarily can not receive data, described input control module controls video input and ultra high-definition video frame rate upconversion process kernel halt input data.
5. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 2, it is characterized in that, described outer buffer memory adopts SDRAM, and each timeticks transmission 32byte data are set, the number that every secondary burst writes transmission data is 8, namely address tunnel often exports primary address, and data channel exports the data of 8 256bit; Corresponding resolving strategy: the compressed bit stream of 4 to be compressed piece of same data path splits into the data of 8 256bit, and a secondary burst is write in SDRAM, is defined as a beat by 4 of same data path to be compressed piece; In a beat, the processed number of blocks to be compressed in a certain road is many, and this road is called current beat data path; In beat, the processed number of blocks to be compressed of two-way is identical, then kernel processes is current beat data path.
6. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 2, it is characterized in that, described outer buffer memory adopts SDRAM, address tunnel often exports primary address, data channel exports the data of 8 256bit, the 512bit compressed bit stream of reception is split into the code stream section of two 256bit by bite rate control module, and to the separately process of the compressed bit stream from video input data path and ultra high-definition video frame rate upconversion process kernel data path; When a certain road reaches 4 compressed bit streams, i.e. 8 256bit code stream sections, control address generation module writes out the address that these 4 compressed bit streams store in the outer buffer memory of sheet, and under the control of data controlling signal, is written out to by these 4 compressed bit streams in the outer buffer memory of sheet.
7. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to any one of claim 2-6, it is characterized in that, described compression kernel module completes the compression process of to be compressed piece in real time to form compressed bit stream, comprises prediction module, quantization modules, inverse quantization and pixel and rebuilds module, entropy code module, code stream packetization module, simplifies compression processing module and compressed bit stream formation module;
Described prediction module, carries out group pixels by the pixel to be compressed of each to be compressed piece, then carries out predicting and residual noise reduction, obtains the residual error of each pixel to be compressed;
The residual error of the pixel to be compressed of prediction module gained through quantification treatment, is obtained residual error after the quantification of pixel to be compressed by described quantization modules;
Described inverse quantization and pixel are rebuild module and residual error after the quantification of pixel to be compressed are carried out inverse quantization process and pixel process of reconstruction, obtain the reconstructed value of pixel, when predicting for prediction module;
After pixel quantizes by described entropy code module, residual error carries out entropy code, pixel residual error after obtaining encoding;
Described code stream packetization module, carries out packing process successively by pixel residual values after entropy code, form the rear subcode stream of packing;
Described simplification compression processing module, treat compression blocks and simply compress process, the code stream length of generation is fixed, and necessarily meets compression ratio requirement; Simplify the code stream alternatively code stream that compression processing module produces, when the code stream of above-mentioned prediction module, quantization modules, entropy code resume module can not meet compression ratio requirement, use the compression result simplifying compression processing module to form compressed bit stream;
Described compressed bit stream forms module under compression ratio requires, controls the length of the compressed bit stream exported, forms compressed bit stream to be output; Module is formed at compressed bit stream, calculate the subcode stream length formed through prediction module, quantization modules process, if subcode stream length is greater than the length of directly transmission original pixels needs, then subcode stream is replaced to original pixels, then subcode stream is packaged into a code stream; If the length of this code stream meets compression ratio requirement, then use this code stream as code stream after compression, otherwise use the candidate bit stream that have compressed special processing generation as code stream after compression.
8. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 1, it is characterized in that, described decompression module comprises: code stream request module, code stream receiver module, the second sram cache module, decoding kernel module, output control module, display format modular converter and display control module, wherein:
Described code stream request module, according to output display module and the feature of ultra high-definition video frame rate upconversion process kernel requests data and the state of the second sram cache module, generate the address of compressed bit stream at the outer buffer memory of sheet, and under the control of address control signal, by address by the outer buffer memory of address bus write sheet, cache request compressed bit stream outside sheet;
Described code stream receiver module, in code stream request module to after cache request compressed bit stream outside sheet, detection data controlling signal receives the compressed bit stream data on data/address bus in time, continuous print two 256bit are assembled into a complete 512bit code stream, and this code stream is write the second sram cache module, wait process to be decoded;
Described second sram cache module, receives the compressed bit stream of code stream receiver module, and is stored on sheet in SRAM, successively code stream is exported to decoding kernel module when the kernel module free time of decoding can receive code stream, carries out decoding process;
Described decoding kernel module, receives the compressed bit stream from the second sram cache module, completes the decoding process of compressed bit stream in real time, block of pixels after formation decompress(ion), and block of pixels after decompress(ion) is sent to output control module;
Described output control module, exports to ultra high-definition video frame rate upconversion process kernel and output display module by block of pixels after the decompress(ion) received from decoding kernel module;
Described display format modular converter, according to the data bus protocol between output display module, block of pixels after decompress(ion) is split, obtain data to be displayed, and this data to be displayed is exported to output display module by data/address bus, produce simultaneously data effectively, frame synchronization, line synchronizing signal;
Described display control module, under the input enable signal control that output display module provides, the data controlling display format modular converter export.
9. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 8, it is characterized in that, only when output display module can receive data, described display format modular converter just exports data to output display module, simultaneously effective by the data in data valid signal notice output display module data bus.
10. the outer buffer memory compressibility of a kind of sheet for ultra high-definition frame rate up-conversion according to claim 8 or claim 9, it is characterized in that, described decoding kernel module completes the decoding process of compressed bit stream in real time, comprise code stream analyzing module, entropy decoder module, inverse quantization module, pixel forms module, simplification compression process is decoded and block of pixels restoration module, wherein:
Code stream analyzing module: the compressed bit stream from the second sram cache is resolved to each independently through the pixel residual values of entropy code, and give entropy decoder module carry out entropy decoding process;
Entropy decoder module: the pixel residual values through entropy code code stream analyzing module parsed carries out decoding process, obtains decoded pixel residual values; And give inverse quantization module by this pixel residual values and do further process;
Inverse quantization module, the pixel residual values gone out by entropy decoding module decodes carries out inverse quantization process, obtains the pixel residual values after inverse quantization; And this residual values is given pixel formation module;
Pixel forms module: the pixel residual values that inverse quantization module is formed adds its predicted value, obtains rebuilding pixel value.Described pixel forms module and uses the reconstruction pixel value obtained through the forecasting process identical with step one, obtains the predicted value of current pixel;
Simplify compression process decoder module: decoded according to the mode simplifying compression process by compressed bit stream, obtain decoded reconstruction pixel value;
Block of pixels restoration module: the reconstruction pixel value that pixel formation module obtains is assembled, obtains candidate's decompress(ion) after image element block; If be through the code stream simplifying compression process and formed from the compressed bit stream of buffer memory outside sheet, then give up this candidate's decompress(ion) after image element block, the reconstruction pixel value that use obtains after simplifying compression process decoding module decodes, block of pixels after the decompress(ion) that assembling formation is final; Otherwise use candidate's decompress(ion) after image element block as block of pixels after final decompress(ion).
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